From 1ca5d1b49a5822546040199cb2466cf37a2ada3d Mon Sep 17 00:00:00 2001 From: Todd Frederick Date: Tue, 2 Mar 2010 17:18:49 -0600 Subject: [PATCH] SymEval: Use MachRegister interface --- symEval/rose/SgAsmExpression.h | 2 +- symEval/rose/SgAsmInstruction.h | 2 +- symEval/rose/SgAsmType.h | 2 +- symEval/rose/SgAsmx86Instruction.h | 2 +- symEval/src/RoseImpl.C | 2 +- symEval/src/SymEval.C | 365 +------------------------------------ symEval/src/SymEval.h | 2 +- symEval/src/SymEvalPolicy.C | 59 +++--- 8 files changed, 38 insertions(+), 398 deletions(-) diff --git a/symEval/rose/SgAsmExpression.h b/symEval/rose/SgAsmExpression.h index 6578814..439dede 100644 --- a/symEval/rose/SgAsmExpression.h +++ b/symEval/rose/SgAsmExpression.h @@ -1,7 +1,7 @@ #if !defined(SG_ASM_EXPR_H) #define SG_ASM_EXPR_H -#include "enums.h" +#include "external/rose/rose-compat.h" #include "SgNode.h" class SgAsmExpression : public SgNode { diff --git a/symEval/rose/SgAsmInstruction.h b/symEval/rose/SgAsmInstruction.h index ee26824..8fde77c 100644 --- a/symEval/rose/SgAsmInstruction.h +++ b/symEval/rose/SgAsmInstruction.h @@ -8,7 +8,7 @@ #if !defined(SG_ASM_INSN_H) #define SG_ASM_INSN_H -#include "enums.h" +#include "external/rose/rose-compat.h" #include "typedefs.h" #include "SgNode.h" diff --git a/symEval/rose/SgAsmType.h b/symEval/rose/SgAsmType.h index f4426fe..188fbce 100644 --- a/symEval/rose/SgAsmType.h +++ b/symEval/rose/SgAsmType.h @@ -2,7 +2,7 @@ #define SG_ASM_TYPE_H #include "SgNode.h" -#include "enums.h" +#include "external/rose/rose-compat.h" class SgAsmType : public SgNode { public: diff --git a/symEval/rose/SgAsmx86Instruction.h b/symEval/rose/SgAsmx86Instruction.h index 4571915..f52c95f 100644 --- a/symEval/rose/SgAsmx86Instruction.h +++ b/symEval/rose/SgAsmx86Instruction.h @@ -7,7 +7,7 @@ // All methods that do not appear to be used by x86InstructionSemantics.h // have been commented out. -#include "enums.h" +#include "external/rose/rose-compat.h" #include "typedefs.h" #include "SgNode.h" diff --git a/symEval/src/RoseImpl.C b/symEval/src/RoseImpl.C index ad2dff2..4aa8aea 100644 --- a/symEval/src/RoseImpl.C +++ b/symEval/src/RoseImpl.C @@ -34,7 +34,7 @@ #include #include "../rose/SgAsmx86Instruction.h" -#include "../rose/enums.h" +#include "external/rose/rose-compat.h" #include "../rose/x86InstructionSemantics.h" // SgAsmType.h diff --git a/symEval/src/SymEval.C b/symEval/src/SymEval.C index c8058b0..5d7c452 100644 --- a/symEval/src/SymEval.C +++ b/symEval/src/SymEval.C @@ -204,366 +204,17 @@ void ExpressionConversionVisitor::visit(Immediate* immed) { void ExpressionConversionVisitor::visit(RegisterAST* regast) { // has no children - X86RegisterClass rreg_class; + int rreg_class; int rreg_num; - X86PositionInRegister rreg_pos; - - unsigned int ireg_id = regast->getID(); - - // this will likely need to change when rose supports 64-bit - - // TODO resolve naming inconsistencies between register naming - // are there 16 cr, dr, xmm regs? - // don't care about tr in rose? - // what are spl, bpl, sil, dil - - // set register class and number - switch (ireg_id) { - case r_AH: - case r_AL: - case r_AX: - case r_eAX: - case r_EAX: - case r_rAX: - case r_RAX: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_ax; - break; - case r_BH: - case r_BL: - case r_BX: - case r_eBX: - case r_EBX: - case r_rBX: - case r_RBX: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_bx; - break; - case r_CH: - case r_CL: - case r_CX: - case r_eCX: - case r_ECX: - case r_rCX: - case r_RCX: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_cx; - break; - case r_DH: - case r_DL: - case r_DX: - case r_eDX: - case r_EDX: - case r_rDX: - case r_RDX: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_dx; - break; - case r_SI: - case r_eSI: - case r_ESI: - case r_rSI: - case r_RSI: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_si; - break; - case r_DI: - case r_eDI: - case r_EDI: - case r_rDI: - case r_RDI: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_di; - break; - case r_eSP: - case r_ESP: - case r_rSP: - case r_RSP: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_sp; - break; - case r_eBP: - case r_EBP: - case r_rBP: - case r_RBP: - rreg_class = x86_regclass_gpr; - rreg_num = x86_gpr_bp; - break; - case r_EFLAGS: - rreg_class = x86_regclass_flags; - rreg_num = 0; - break; - case r_CS: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_cs; - break; - case r_DS: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_ds; - break; - case r_ES: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_es; - break; - case r_FS: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_fs; - break; - case r_GS: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_gs; - break; - case r_SS: - rreg_class = x86_regclass_segment; - rreg_num = x86_segreg_ss; - break; - case r_EIP: - case r_RIP: - rreg_class = x86_regclass_ip; - rreg_num = 0; - break; - case r_XMM0: - rreg_class = x86_regclass_xmm; - rreg_num = 0; - break; - case r_XMM1: - rreg_class = x86_regclass_xmm; - rreg_num = 1; - break; - case r_XMM2: - rreg_class = x86_regclass_xmm; - rreg_num = 2; - break; - case r_XMM3: - rreg_class = x86_regclass_xmm; - rreg_num = 3; - break; - case r_XMM4: - rreg_class = x86_regclass_xmm; - rreg_num = 4; - break; - case r_XMM5: - rreg_class = x86_regclass_xmm; - rreg_num = 5; - break; - case r_XMM6: - rreg_class = x86_regclass_xmm; - rreg_num = 6; - break; - case r_XMM7: - rreg_class = x86_regclass_xmm; - rreg_num = 7; - break; - case r_MM0: - rreg_class = x86_regclass_mm; - rreg_num = 0; - break; - case r_MM1: - rreg_class = x86_regclass_mm; - rreg_num = 1; - break; - case r_MM2: - rreg_class = x86_regclass_mm; - rreg_num = 2; - break; - case r_MM3: - rreg_class = x86_regclass_mm; - rreg_num = 3; - break; - case r_MM4: - rreg_class = x86_regclass_mm; - rreg_num = 4; - break; - case r_MM5: - rreg_class = x86_regclass_mm; - rreg_num = 5; - break; - case r_MM6: - rreg_class = x86_regclass_mm; - rreg_num = 6; - break; - case r_MM7: - rreg_class = x86_regclass_mm; - rreg_num = 7; - break; - case r_ST0: - rreg_class = x86_regclass_st; - rreg_num = 0; - break; - case r_ST1: - rreg_class = x86_regclass_st; - rreg_num = 1; - break; - case r_ST2: - rreg_class = x86_regclass_st; - rreg_num = 2; - break; - case r_ST3: - rreg_class = x86_regclass_st; - rreg_num = 3; - break; - case r_ST4: - rreg_class = x86_regclass_st; - rreg_num = 4; - break; - case r_ST5: - rreg_class = x86_regclass_st; - rreg_num = 5; - break; - case r_ST6: - rreg_class = x86_regclass_st; - rreg_num = 6; - break; - case r_ST7: - rreg_class = x86_regclass_st; - rreg_num = 7; - break; - case r_DR0: - rreg_class = x86_regclass_dr; - rreg_num = 0; - break; - case r_DR1: - rreg_class = x86_regclass_dr; - rreg_num = 1; - break; - case r_DR2: - rreg_class = x86_regclass_dr; - rreg_num = 2; - break; - case r_DR3: - rreg_class = x86_regclass_dr; - rreg_num = 3; - break; - case r_DR4: - rreg_class = x86_regclass_dr; - rreg_num = 4; - break; - case r_DR5: - rreg_class = x86_regclass_dr; - rreg_num = 5; - break; - case r_DR6: - rreg_class = x86_regclass_dr; - rreg_num = 6; - break; - case r_DR7: - rreg_class = x86_regclass_dr; - rreg_num = 7; - break; - case r_CR0: - rreg_class = x86_regclass_cr; - rreg_num = 0; - break; - case r_CR1: - rreg_class = x86_regclass_cr; - rreg_num = 1; - break; - case r_CR2: - rreg_class = x86_regclass_cr; - rreg_num = 2; - break; - case r_CR3: - rreg_class = x86_regclass_cr; - rreg_num = 3; - break; - case r_CR4: - rreg_class = x86_regclass_cr; - rreg_num = 4; - break; - case r_CR5: - rreg_class = x86_regclass_cr; - rreg_num = 5; - break; - case r_CR6: - rreg_class = x86_regclass_cr; - rreg_num = 6; - break; - case r_CR7: - rreg_class = x86_regclass_cr; - rreg_num = 7; - break; - default: - rreg_class = x86_regclass_unknown; - rreg_num = 0; - rreg_pos = x86_regpos_unknown; - } + int rreg_pos; - // set register position - // TODO will be ever be in 16-bit mode? If so, then fix e implied regs. - switch (ireg_id) { - case r_AH: - case r_BH: - case r_CH: - case r_DH: - rreg_pos = x86_regpos_high_byte; - break; - case r_AL: - case r_BL: - case r_CL: - case r_DL: - rreg_pos = x86_regpos_low_byte; - break; - case r_AX: - case r_BX: - case r_CX: - case r_DX: - case r_SI: - case r_DI: - rreg_pos = x86_regpos_word; - break; - case r_eAX: - case r_eBX: - case r_eCX: - case r_eDX: - case r_eSI: - case r_eDI: - case r_eSP: - case r_eBP: - case r_EAX: - case r_EBX: - case r_ECX: - case r_EDX: - case r_ESI: - case r_EDI: - case r_ESP: - case r_EBP: - rreg_pos = x86_regpos_dword; - break; - case r_rAX: - case r_rBX: - case r_rCX: - case r_rDX: - case r_rSI: - case r_rDI: - case r_rSP: - case r_rBP: - std::cerr << "FIXME forcing 32-bit conversion!" << std::endl; - rreg_pos = x86_regpos_dword; - break; - case r_RAX: - case r_RBX: - case r_RCX: - case r_RDX: - case r_RSI: - case r_RDI: - case r_RSP: - case r_RBP: - case r_R8: - case r_R9: - case r_R10: - case r_R11: - case r_R12: - case r_R13: - case r_R14: - case r_R15: - rreg_pos = x86_regpos_qword; - break; - default: - fprintf(stderr, "Odd: got register %d\n", ireg_id); - rreg_pos = x86_regpos_all; - } + unsigned int machRegID = regast->getID(); + MachRegister machReg(machRegID); + machReg.getROSERegister(rreg_class, rreg_num, rreg_pos); - roseExpression = new SgAsmx86RegisterReferenceExpression(rreg_class, rreg_num, rreg_pos); + roseExpression = new SgAsmx86RegisterReferenceExpression((X86RegisterClass)rreg_class, + rreg_num, + (X86PositionInRegister)rreg_pos); } void ExpressionConversionVisitor::visit(Dereference* deref) { diff --git a/symEval/src/SymEval.h b/symEval/src/SymEval.h index e1b44ef..ac14fcd 100644 --- a/symEval/src/SymEval.h +++ b/symEval/src/SymEval.h @@ -43,7 +43,7 @@ #include "Absloc.h" #include "AST.h" -#include "../rose/enums.h" +#include "external/rose/rose-compat.h" class SgAsmx86Instruction; class SgAsmExpression; diff --git a/symEval/src/SymEvalPolicy.C b/symEval/src/SymEvalPolicy.C index 967f529..6b54096 100644 --- a/symEval/src/SymEvalPolicy.C +++ b/symEval/src/SymEvalPolicy.C @@ -22,7 +22,7 @@ SymEvalPolicy::SymEvalPolicy(SymEval::Result &r) : else { // Use sufficiently-unique (Heap,0) Absloc // to represent a definition to a memory absloc - aaMap[Absloc(Absloc::Heap, 0)] = a; + aaMap[Absloc(0)] = a; } } } @@ -36,111 +36,100 @@ void SymEvalPolicy::finishInstruction(SgAsmx86Instruction *) { Absloc SymEvalPolicy::convert(X86GeneralPurposeRegister r) { - int id; + MachRegister mreg; switch (r) { case x86_gpr_ax: - id = r_EAX; + mreg = x86::eax; break; case x86_gpr_cx: - id = r_ECX; + mreg = x86::ecx; break; case x86_gpr_dx: - id = r_EDX; + mreg = x86::edx; break; case x86_gpr_bx: - id = r_EBX; + mreg = x86::ebx; break; case x86_gpr_sp: - id = r_ESP; + mreg = x86::esp; break; case x86_gpr_bp: - id = r_EBP; + mreg = x86::ebp; break; case x86_gpr_si: - id = r_ESI; + mreg = x86::esi; break; case x86_gpr_di: - id = r_EDI; + mreg = x86::edi; break; default: - id = 0; // error + break; } - return Absloc(Absloc::Register, id);; + return Absloc(mreg);; } Absloc SymEvalPolicy::convert(X86SegmentRegister r) { - int id; + MachRegister mreg; switch (r) { case x86_segreg_es: - id = r_ES; + mreg = x86::es; break; case x86_segreg_cs: - id = r_CS; + mreg = x86::cs; break; case x86_segreg_ss: - id = r_SS; + mreg = x86::ss; break; case x86_segreg_ds: - id = r_DS; + mreg = x86::ds; break; case x86_segreg_fs: - id = r_FS; + mreg = x86::fs; break; case x86_segreg_gs: - id = r_GS; + mreg = x86::gs; break; default: - id = 0; //error + break; } - return Absloc(Absloc::Register, id); + return Absloc(mreg); } Absloc SymEvalPolicy::convert(X86Flag f) { - int id; + return Absloc(x86::flags); + switch (f) { case x86_flag_cf: - id = r_CF; break; case x86_flag_pf: - id = r_PF; break; case x86_flag_af: - id = r_AF; break; case x86_flag_zf: - id = r_ZF; break; case x86_flag_sf: - id = r_SF; break; case x86_flag_tf: - id = r_TF; break; case x86_flag_if: - id = r_IF; break; case x86_flag_df: - id = r_DF; break; case x86_flag_of: - id = r_OF; break; case x86_flag_nt: - id = r_NT; break; case x86_flag_rf: - id = r_RF; break; default: std::cerr << "Failed to find flag " << f << std::endl; assert(0); - id = 0; // error } - return Absloc(Absloc::Register, id); + } -- 1.8.3.1