dyninst.git
2 years agofix addressing mode for emitLoadRelative ER/StoreShared
LER0ever [Wed, 20 Feb 2019 20:25:11 +0000 (14:25 -0600)]
fix addressing mode for emitLoadRelative

2 years agomovePCToReg still not working
LER0ever [Wed, 20 Feb 2019 20:03:51 +0000 (14:03 -0600)]
movePCToReg still not working

2 years agoaarch64 broken movePCToReg implementation
LER0ever [Fri, 8 Feb 2019 22:58:24 +0000 (16:58 -0600)]
aarch64 broken movePCToReg implementation

2 years agofix break on dynamic mode 545/head
LER0ever [Fri, 1 Feb 2019 21:06:19 +0000 (15:06 -0600)]
fix break on dynamic mode

2 years agoadd rewriter mode check
LER0ever [Fri, 1 Feb 2019 20:43:59 +0000 (14:43 -0600)]
add rewriter mode check
delete unwanted functions

2 years agoremoved all the debug printout for imfc
LER0ever [Wed, 30 Jan 2019 04:51:44 +0000 (22:51 -0600)]
removed all the debug printout for imfc

2 years agofix memory access mistakes, now uses offset mode
LER0ever [Wed, 30 Jan 2019 04:45:00 +0000 (22:45 -0600)]
fix memory access mistakes, now uses offset mode

2 years agoImplement AArch64 InterModule Function call
LER0ever [Mon, 14 Jan 2019 19:26:48 +0000 (13:26 -0600)]
Implement AArch64 InterModule Function call
Debug message needs to be removed after finding out
* why X0 is kept being used
* why putting X0 address value back to itself does not work

2 years agofmt mixed-indented line changes to space-indented
LER0ever [Thu, 27 Dec 2018 06:49:50 +0000 (00:49 -0600)]
fmt mixed-indented line changes to space-indented

2 years agoimplement params ref for more than 8 args for AArch64
LER0ever [Thu, 27 Dec 2018 06:45:48 +0000 (00:45 -0600)]
implement params ref for more than 8 args for AArch64
test1_36 now passes on ARMv8

2 years agoGenerating Load and Store of 1, 2, 4 or 8 bytes
Sasha @leela [Sat, 22 Dec 2018 01:35:40 +0000 (19:35 -0600)]
Generating Load and Store of 1, 2, 4 or 8 bytes
for general purpose registers.
The function generateMemAccess32or64 has been renamed
to generateMemAccess, and the boolean parameter changed
to integer to hold the size of bytes to be loaded or
stored.
test_snip_ref_shlib_var passes.

2 years agoFix modifyData to correctly emit instructions
Sasha @leela [Fri, 14 Dec 2018 01:38:22 +0000 (19:38 -0600)]
Fix modifyData to correctly emit instructions
when the offset of LDR (literal) instructions, after a relocation,
is larger than +-1MB.
test_reloc passes.

2 years agoEnable detach from process and leave stopped
Benjamin Welton [Fri, 7 Dec 2018 23:13:57 +0000 (17:13 -0600)]
Enable detach from process and leave stopped

Enables the ability to detach from a process but leave it in a stopped state

(cherry picked from commit 8470129b60a6c13b21839234f9804c355a73d8a4)

2 years agoImplements getDynamicCallSiteArgs to monitor dynamic call sites.
Sasha @leela [Thu, 6 Dec 2018 00:14:08 +0000 (18:14 -0600)]
Implements getDynamicCallSiteArgs to monitor dynamic call sites.
Implements emitLoadOrigRegister to get frame pointer register.
Test1_40 passes.

2 years agoMerge branch 'master' into ARMv8
Sasha @leela [Wed, 28 Nov 2018 23:26:46 +0000 (17:26 -0600)]
Merge branch 'master' into ARMv8

2 years agoFix wrong handling for PTRACE_EVENT_EXIT in proccontrol. Currently, each time we...
Xiaozhu Meng [Wed, 28 Nov 2018 21:56:15 +0000 (15:56 -0600)]
Fix wrong handling for PTRACE_EVENT_EXIT in proccontrol. Currently, each time we see PTRACE_EVENT_EXIT, we assume the mutatee exited normally. However, this is a wrong assumption. Based on the man page of PTRACE:

PTRACE_EVENT_EXIT will happen before actual death,  This applies to exits via
exit(2), exit_group(2), and signal deaths

PTRACE_EVENT_EXIT will also be delivered to proccontrol when the mutatee
died of crashes/signals. So, we need to check whether the waitpid status
represents a normal exit or a signal exit

2 years agoFix long branch generation.
Sasha @leela [Wed, 21 Nov 2018 19:40:47 +0000 (13:40 -0600)]
Fix long branch generation.
Fix emit load register indirect.
Implements hasBeenBound for ARM.
Tests passing now: test1_14, 24, 26, 27, 28, 29, and 39.

2 years agoUpdate README.md
Xiaozhu Meng [Mon, 19 Nov 2018 17:02:42 +0000 (11:02 -0600)]
Update README.md

2 years agoImplementing emitLoadOrigRegRelative and emitStoreIndir.
Sasha @leela [Sat, 17 Nov 2018 01:21:32 +0000 (19:21 -0600)]
Implementing emitLoadOrigRegRelative and emitStoreIndir.
Adding case of loadRegRelativeOp and storeIndirOp for emitVload.
test1_23 passes.

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Fri, 9 Nov 2018 17:41:29 +0000 (11:41 -0600)]
Merge branch 'master' of https://github.com/dyninst/dyninst

2 years agoMerge branch 'master' into ARMv8
Sasha @leela [Fri, 9 Nov 2018 17:01:06 +0000 (11:01 -0600)]
Merge branch 'master' into ARMv8

2 years agoUpdate latex based manuals v10.0.0
Xiaozhu Meng [Fri, 9 Nov 2018 16:48:08 +0000 (10:48 -0600)]
Update latex based manuals

2 years agoMerge branch 'master' into ARMv8
Sasha @leela [Fri, 9 Nov 2018 16:28:31 +0000 (10:28 -0600)]
Merge branch 'master' into ARMv8

2 years agoMore updates to README and docx based manuals
Xiaozhu Meng [Fri, 9 Nov 2018 16:17:46 +0000 (10:17 -0600)]
More updates to README and docx based manuals

2 years agoFix generateLongBranch to make Replace Function work.
Sasha @leela [Fri, 9 Nov 2018 00:50:47 +0000 (18:50 -0600)]
Fix generateLongBranch to make Replace Function work.
test1_22 passes.

2 years agoClear debugging output
Xiaozhu Meng [Thu, 8 Nov 2018 21:57:08 +0000 (15:57 -0600)]
Clear debugging output

2 years agoUpdate README.md
Sasha NĂ­colas [Thu, 8 Nov 2018 21:40:02 +0000 (15:40 -0600)]
Update README.md

2 years agoCorrect LDR/STR instructions for SIMD&FP
Sasha @leela [Thu, 8 Nov 2018 21:22:27 +0000 (15:22 -0600)]
Correct LDR/STR instructions for SIMD&FP
Saving all FP registers in BaseTramp
Remove #if for DYNINST_snippetBreakpoint

2 years agoBump the version number to 10.0.0
Xiaozhu Meng [Thu, 8 Nov 2018 18:27:47 +0000 (12:27 -0600)]
Bump the version number to 10.0.0

2 years agoUpdate Spack information
Xiaozhu Meng [Thu, 8 Nov 2018 17:54:07 +0000 (11:54 -0600)]
Update Spack information

2 years agoUpdate README.md to rewrite install documentation
Xiaozhu Meng [Thu, 8 Nov 2018 16:52:28 +0000 (10:52 -0600)]
Update README.md to rewrite install documentation

2 years agoUpdate cmake setup explanation in README.md
Xiaozhu Meng [Wed, 7 Nov 2018 22:47:15 +0000 (16:47 -0600)]
Update cmake setup explanation in README.md

2 years agoRemove old files and start to update README.md
Xiaozhu Meng [Wed, 7 Nov 2018 21:10:03 +0000 (15:10 -0600)]
Remove old files and start to update README.md

2 years agoImplementing DynFrameHelper::allocatesFrame
Sasha @leela [Wed, 7 Nov 2018 19:18:45 +0000 (13:18 -0600)]
Implementing DynFrameHelper::allocatesFrame
Implementing StackwalkInstrumentationHelper::isInstrumentation
Implementing writeFunctionPtr
Removing #if for DYNINST_instForkEntry
test_thread_*, test_fork_* passing.

2 years agoClean up change log
Xiaozhu Meng [Wed, 7 Nov 2018 17:27:05 +0000 (11:27 -0600)]
Clean up change log

2 years agoUpdate change log since v9.3.2 for v10.0.0
Xiaozhu Meng [Wed, 7 Nov 2018 16:03:19 +0000 (10:03 -0600)]
Update change log since v9.3.2 for v10.0.0

2 years agoAdded/updated support for 271 new power instructions
Benjamin Welton [Tue, 6 Nov 2018 06:07:15 +0000 (22:07 -0800)]
Added/updated support for 271 new power instructions

Added full/partial support for the following instructions:

vsldoi ,maddhd ,maddhdu ,maddld ,vbpermq ,extended ,bcdctsq ,bcdcfsq ,bcdctz ,bcdctn ,bcdcfz ,bcdcfn ,bcdsetsgn ,vclzlsbb ,vctzlsbb ,vnegw ,vnegd ,vprtybw ,vprtybd ,vprtybq ,vextsb2w ,vextsh2w ,vextsb2d ,vextsh2d ,vextsw2d ,vctzb ,vctzh ,vctzw ,vctzd ,dcbst ,wait ,td ,lxsiwax ,stfpdux ,slbiag ,cmpeqb ,cmprb ,cnttzw ,cnttzd ,cp_abort ,darn ,extswsl ,ldat ,lwat ,mcrxrx ,mfvsrld ,modsd ,modud ,modsw ,moduw ,msgsnd ,msgclr ,msgsndp ,msgclrp ,msgsync ,mtvsrdd ,mfvsrwz ,mtvsrd ,mtvsrwa ,mtvsrwz ,mtvsrws ,setb ,slbieg ,slbsync ,stdat ,stwat ,clrbhrb ,mfbhrbe ,icbt ,lqarx ,stqcx ,tbegin ,tend ,tabort ,tabortwc ,tabortwci ,tabortdc ,tabortdci ,tsr ,tcheck ,treclaim ,trechkpt ,addg6s ,cdtbcd ,cbcdtd ,divde ,divdeu ,modsd ,lbarx ,lharx ,ldbrx ,stbcx ,stdbrx ,sthcx ,lbzcix ,lwzcix ,ldcix ,stbcix ,sthcix ,stwcix ,stdcix ,lfdpx ,stfdpx ,prtyd ,prtyw ,slbfee ,slbfee ,slbmfee ,slbmfev ,mfocrf ,isel ,tlbiel ,slbmte ,subfze ,mtmsrd ,mtmsr ,copy ,paste ,extswsli ,stxvb16x ,wait ,lxsiwax ,mfvsrd ,bpermd ,divwe ,divweu ,lfiwzx ,cmpb ,lfiwax ,lhzcix ,slbia ,slbie ,dtstsfi ,dcffix ,fcfids ,fcfidus ,dadd ,dcmpo ,dcmpu ,dctdp ,dctfix ,ddedpd ,ddiv ,denbcd ,diex ,dmul ,dquai ,dqua ,drintn ,drintx ,drrnd ,drsp ,dscli ,dscri ,dsub ,dtstdc ,dtstdg ,dtstex ,dtstsf ,frsqrtes ,dxex ,xxpermdi ,xvtdivsp ,xxsel ,xxsldwi ,xvnmaddasp ,xscmpexpdp ,xscvuxddp ,xxspltib ,xsaddsp ,xsmaddadp ,xsrdpi ,xssubdp ,xsmsubmdp ,xscmpexpdp ,xscmpexpdp ,xvrspip ,xxinsertw ,xvcmpeqdp ,xvrsqrtedp ,xxlor ,xsnmaddadp ,xscvdpuxds ,xvnabssp ,xvnegsp ,xvcvsxddp ,xsnmsubqp ,daddq ,dcffixq ,dcmpoq ,dcmpuq ,dctfixq ,dctqpq ,ddedpdq ,denbcdq ,ddivq ,diexq ,dmulq ,dquaiq ,dquaq ,drdpq ,drintnq ,drintxq ,drrndq ,dscliq ,dscriq ,dsubq ,dtstdcq ,dtstdgq ,dtstexq ,dtstsfq ,dxexq ,fcpsgn ,fre ,frim ,frin ,frip ,friz ,fctidz ,xsxexpdp ,xsxsigdp ,xscvdphp ,xscvhphp ,xvxexpdp ,xvxsigdp ,xxbrh ,xvxexpsp ,xvxsigsp ,xxbrw ,xxbrd ,xvcvhpsp ,xvcvsphp ,xxbrq ,xsxexpdp ,xvxexpdp ,xscvqpsdz ,dtstsfiq ,xscpsgnqp ,xsdivqp ,xsrqpxp ,fmrgew ,fmrgow ,fcfidu, fctidu ,fctiduz ,fctiwu ,fctiwuz ,ftdiv ,ftsqrt ,mffs ,mffsce ,mffscdrn ,mffscdrn ,mffscdrni ,mffscrn ,mffsl ,xsabsqp ,xsxexpqp ,xsnegqp ,xsxsigqp ,xssqrtqp ,xsnabsqp ,xscvqpuwz ,xscvudqp ,xscvqpswz ,xscvsdqp ,xscvqpudz ,xscvqpdp ,xscvdpqp ,xscvqpsdz

Currently missing is operand decoding for the following operand types:

UIM(), BHRBE(), IH(), SP(), S(), TE(), DGM(), DCM(), CT(), RSP(), RTP(), EH(), PRS(), A(), R(), BC(), RC(), RIC(), SIM(), DCMX(), RO(), RMC(), EX(), SHB(), PS(), CY(), DRM(), SHW(), XC(), DM(), IMM8()

If an instruction with one of these operands is encounted, the operand will not be docoded and a warning message printed. Over time support for these operands will be added.

2 years agoMerge branch 'master' into ARMv8
Sasha @leela [Mon, 5 Nov 2018 22:06:44 +0000 (16:06 -0600)]
Merge branch 'master' into ARMv8

2 years agoMerge branch 'ARMv8' of https://github.com/dyninst/dyninst into ARMv8
Sasha @leela [Mon, 5 Nov 2018 21:50:35 +0000 (15:50 -0600)]
Merge branch 'ARMv8' of https://github.com/dyninst/dyninst into ARMv8

2 years agoVarious bug fixes
Xiaozhu Meng [Mon, 5 Nov 2018 20:38:54 +0000 (14:38 -0600)]
Various bug fixes

1. Jump table analysis
   1.1 do not slice backward along indirect edges, which will
   make jump table analysis depends on results of previous jump table analysis,
   and have cascading wrong analysis results.
   1.2 On x86, perform tentative instruction decoding at potential jump targets.
   If we find junk instructions at jump target, then we know the jump target is wrong
   1.3 Remove jump target checks that relies on the parsing function context.
   For jump tables shared by multiple functions, such checks can easily lead to
   non-determinisitic results.

2. Tail calls: on x86, if there is a pop to a callee saved register, it means
   the function is tearing down the stack frame. So, this jump should be a tail call

3. PLT stubs
   3.1 Improve analysis of PLT in .plt.got and fix related instrumentation problems
   3.2 Function should use the PLT name at the beginning of the parsing, not at the
   end of parsing. Otherwise, for PLT that is known to be non-returning, its caller
   may have the wrong retstatus

2 years agofix doNotOverflow for int64, picked from 2b21d59
LER0ever [Sun, 4 Nov 2018 20:49:50 +0000 (14:49 -0600)]
fix doNotOverflow for int64, picked from 2b21d59

2 years agoAdded 80 Power instructions missing from opcode 31
Benjamin Welton [Sat, 3 Nov 2018 05:19:41 +0000 (00:19 -0500)]
Added 80 Power instructions missing from opcode 31

Added the following new instructions to the power opcode tables (however they are not yet enabled):

slbiag, cmpeqb, cmprb, cnttz, cnttz, cp_abort, darn, extswsl, ldat, lwat, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, msgclr, msgclrp, msgsnd, msgsndp, mtvsrdd, mtvsrws, mtvsrd, mtvsrwa, mtvsrwz, mfvsrd, mfvsrwz, setb, slbieg, slbsync, stdat, stwat, clrbhrb, mfbhrbe, icbt, lqarx, stqcx, tabort, tabortdc, tabortdci, tabortwc, tabortwci, tbegin, tcheck, trechkpt, treclaim, tsr, addg6s, cbcdtd, cdtbcd, divde, divwe, lbarx, ldbrx, lharx, stbcx, stdbrx, sthcx, lbzcix, ldcix, lhzcix, lwzcix, stbcix, stdcix, sthcix, stwcix, lfdpx, stfdpx, prtyd, prtyw, slbfee, slbmfee, slbmfev, isel, tlbiel, subfz, slbmte, mtmsr, mtmsrd

2 years agoMinor fix to decoding extended opcode 30 on PPC
Benjamin Welton [Fri, 2 Nov 2018 20:45:29 +0000 (13:45 -0700)]
Minor fix to decoding extended opcode 30 on PPC

On PPC, the extended opcode of table 30 is decoded based on the following criterion:

If bit 27 = 1. Extended opcode is at range 27-30. Otherwise the extended opcode range is 27-29.

2 years agoMerge branch 'ARMv8' of https://code.rongyi.io/LER0ever/Dyninst into ARMv8
LER0ever [Tue, 30 Oct 2018 21:52:40 +0000 (16:52 -0500)]
Merge branch 'ARMv8' of https://code.rongyi.io/LER0ever/Dyninst into ARMv8

Conflict: binutils 2.31.1 instead

2 years agoaarch64: use sys/uio instead of bits/uio
LER0ever [Wed, 24 Oct 2018 22:46:39 +0000 (22:46 +0000)]
aarch64: use sys/uio instead of bits/uio
we should never include bits/uio directly, as stated in the bits/uio.h file:

18 #if !defined _SYS_UIO_H && !defined _FCNTL_H
19 # error "Never include <bits/uio.h> directly; use <sys/uio.h> instead."
20 #endif

2 years agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

2 years agoMerge branch 'master' into ARMv8
Sasha @leela [Tue, 30 Oct 2018 20:12:17 +0000 (15:12 -0500)]
Merge branch 'master' into ARMv8

2 years agoUpdate binutils version to download.
Sasha @leela [Tue, 30 Oct 2018 19:30:32 +0000 (14:30 -0500)]
Update binutils version to download.

2 years agoImplement doNotOverflow for ARMv8.
Sasha @leela [Tue, 30 Oct 2018 18:13:55 +0000 (13:13 -0500)]
Implement doNotOverflow for ARMv8.
Implement load relative.
Fix emit immediate for plus and minus.

2 years agoFix interface changes for ARM.
Sasha @leela [Tue, 30 Oct 2018 17:50:28 +0000 (12:50 -0500)]
Fix interface changes for ARM.

2 years ago1. Fix x86-64 codegen for binary operators with 64-bit imm values
Xiaozhu Meng [Fri, 26 Oct 2018 17:06:36 +0000 (12:06 -0500)]
1. Fix x86-64 codegen for binary operators with 64-bit imm values

2. When decoding floating point instructions on x86-64, the address size
override prefix means 64-bit address size rather than 16-bit

3. Fix a linking problem of examples

4. Do not use negative values when reading jump tables

2 years agoAdding USE_OpenMP to cmake files;
Sasha Nicolas [Thu, 25 Oct 2018 21:42:30 +0000 (16:42 -0500)]
Adding USE_OpenMP to cmake files;
Adding MD5 to verify downloaded file;
Removing compiler restriction.

2 years agoMerge pull request #488 from dyninst/new-parallel-parsing
Xiaozhu Meng [Thu, 25 Oct 2018 20:38:02 +0000 (15:38 -0500)]
Merge pull request #488 from dyninst/new-parallel-parsing

Merge parallel code parsing

2 years agoMerge branch 'master' into new-parallel-parsing 488/head
Xiaozhu Meng [Thu, 25 Oct 2018 20:35:09 +0000 (15:35 -0500)]
Merge branch 'master' into new-parallel-parsing

Rmove setting function ret status during finalizing

Conflicts:
cmake/packages.cmake
examples/CMakeLists.txt
instructionAPI/src/power_opcode_tables.C

2 years ago1. Fix inconsistent block splits
Xiaozhu Meng [Thu, 25 Oct 2018 14:06:21 +0000 (09:06 -0500)]
1. Fix inconsistent block splits

2. Fix non-returning function analysis for PLT stubs, where a PLT stub
   may first be set to RETURN and then set to NORETURN.

3. When parsing call fallthrough edge, the corresponding call edge may
   still point to sink (not handled yet), which causes the code to
   believe it is an indirect call. So, change the code to look up callee
   by using the callee entry address.

2 years agoaarch64: use sys/uio instead of bits/uio
LER0ever [Wed, 24 Oct 2018 22:46:39 +0000 (22:46 +0000)]
aarch64: use sys/uio instead of bits/uio
we should never include bits/uio directly, as stated in the bits/uio.h file:

18 #if !defined _SYS_UIO_H && !defined _FCNTL_H
19 # error "Never include <bits/uio.h> directly; use <sys/uio.h> instead."
20 #endif

2 years agoMerge pull request #496 from LER0ever/code.rongyi.io/LER0ever/Dyninst/build-fixes
Xiaozhu Meng [Wed, 24 Oct 2018 18:55:50 +0000 (13:55 -0500)]
Merge pull request #496 from LER0ever/code.rongyi.io/LER0ever/Dyninst/build-fixes

Build fixes for parallel building and xdr-related issues

2 years agoMerge pull request #498 from dyninst/power_vector
Xiaozhu Meng [Wed, 24 Oct 2018 15:08:11 +0000 (10:08 -0500)]
Merge pull request #498 from dyninst/power_vector

Vector instruction support on Power and recycled opcode

2 years agoFinish most of the Power 8 VSX instruction decoding 498/head
Xiaozhu Meng [Wed, 24 Oct 2018 12:55:26 +0000 (07:55 -0500)]
Finish most of the Power 8 VSX instruction decoding

2 years agoMerge branch 'ARMv8' of ssh://code.rongyi.io:233/LER0ever/Dyninst into ARMv8
LER0ever [Wed, 24 Oct 2018 05:14:26 +0000 (05:14 +0000)]
Merge branch 'ARMv8' of ssh://code.rongyi.io:233/LER0ever/Dyninst into ARMv8

2 years agoaarch64: add branchOp case
LER0ever [Tue, 23 Oct 2018 21:50:40 +0000 (16:50 -0500)]
aarch64: add branchOp case

2 years agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

2 years agoModifying cmake configuration to compile and install TBB.
Sasha Nicolas [Wed, 24 Oct 2018 01:36:57 +0000 (20:36 -0500)]
Modifying cmake configuration to compile and install TBB.

2 years agoaarch64: add branchOp case
LER0ever [Tue, 23 Oct 2018 21:50:40 +0000 (16:50 -0500)]
aarch64: add branchOp case

2 years ago10/23
Yuhan Xie [Tue, 23 Oct 2018 20:23:08 +0000 (15:23 -0500)]
10/23
Chapter 6

new:
    keyword CY, 21th bit
    keyword ST, 16th bit
    keyword SIX, 17-20
    keyword DRM, 18-20
    keyword RM, 19-20
    (ST and SIX always show up together)
    keyword PS, 22th bit

Summary of Changable fields:
UIM:
11-15:
   4-906 vctuxs,
   4-970 vctsxs,

  12-15:
     4-524 vspltb
     4-525 vextractub
     4-589 vextractuh
     4-653 vextractuw
     4-717 vextractd
     4-781 vinsertb
     4-845 vinserth
     4-909 vinsertw
     4-973 vinsertd

4-588 vsplth 13-15

4-652 vspltw 14-15

Rc bit:
  for opcode 4: always 21th bit

6-bit(26-31) ext opcode for opcode 4:
   32-47, 59-63

2 years agoImplementing indirect load.
Sasha @leela [Tue, 23 Oct 2018 00:01:54 +0000 (19:01 -0500)]
Implementing indirect load.
Now dereferencing, address-of and negative assignment works. test1_25 passes.
Fix multiplication of negative value only for int of 32 bits.

2 years agoMerge branch 'master' into new-parallel-parsing
Xiaozhu Meng [Sun, 21 Oct 2018 22:57:45 +0000 (17:57 -0500)]
Merge branch 'master' into new-parallel-parsing

2 years agoAdding multiple items for Power 8 instruction decoding
Xiaozhu Meng [Fri, 19 Oct 2018 16:21:40 +0000 (11:21 -0500)]
Adding multiple items for Power 8 instruction decoding

1. VSR registers
2. Decoding for several operand fields
3. Decoding for extended op 60

2 years agoRemove an edge check that caused significant slowdown
Xiaozhu Meng [Thu, 18 Oct 2018 21:55:26 +0000 (16:55 -0500)]
Remove an edge check that caused significant slowdown

2 years ago10/18 Opcode from Chapter 6
Yuhan Xie [Thu, 18 Oct 2018 20:43:46 +0000 (15:43 -0500)]
10/18 Opcode from Chapter 6

Summary of Changable fields:
  UIM:
  12-15:
4-524 vspltb
4-525 vextractub
4-589 vextractuh
4-653 vextractuw
4-717 vextractd
4-781 vinsertb
4-845 vinserth
4-909 vinsertw
4-973 vinsertd
13-15:
4-588 vsplth
    14-15:
4-652 vspltw

  Rc bit:
for opcode 4: always 21th bit

ext opcode for opcode 4:
    26-31: 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 59, 60, 61, 62, 63

new:
  Keyword SIM, 11-15 bits
    Keyword SHB, 22-25 bits
third-level opcode: 4-1538-x

2 years agoStart to integrate new power opcodes
Xiaozhu Meng [Thu, 18 Oct 2018 16:57:24 +0000 (11:57 -0500)]
Start to integrate new power opcodes

2 years agoFixing regression in some tests caused by misplaced directive.
Sasha Nicolas [Thu, 18 Oct 2018 01:21:39 +0000 (20:21 -0500)]
Fixing regression in some tests caused by misplaced directive.

2 years agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

2 years agocmake: fix msvc complaints about target dependency 496/head
LER0ever [Wed, 17 Oct 2018 23:34:20 +0000 (18:34 -0500)]
cmake: fix msvc complaints about target dependency

2 years agocmake: add conditional check for whether we are building boost
LER0ever [Wed, 17 Oct 2018 23:10:40 +0000 (18:10 -0500)]
cmake: add conditional check for whether we are building boost

2 years agocmake: add boost to all dyninst libraries and DyninstRT, fixes parallel building
LER0ever [Wed, 17 Oct 2018 22:54:10 +0000 (17:54 -0500)]
cmake: add boost to all dyninst libraries and DyninstRT, fixes parallel building

2 years agoUpdate ABI.C
melsabagh-kw [Tue, 9 Jan 2018 16:40:49 +0000 (11:40 -0500)]
Update ABI.C

ebx is callee-saved and should not be set in `callWritten_`.
(cherry picked from commit 6537dafa476375bbfbaa3b0149cc4d27b59b80f7)

2 years ago1. Fix typos in the Power instruction decoding table and add
Xiaozhu Meng [Wed, 17 Oct 2018 14:31:10 +0000 (09:31 -0500)]
1. Fix typos in the Power instruction decoding table and add
   instruction semantics for rldicl

2. When pushing new parse work elements into the work queue,
   we cannot get the source address of the edge from Block::last(),
   because we currently do not hold an accessor to the block end
   and the block can be split. So, before adding new work elements,
   first acquire an accessor to the block end

2 years agoA block can be split between it is just recorded in the block end
Xiaozhu Meng [Tue, 16 Oct 2018 20:23:53 +0000 (15:23 -0500)]
A block can be split between it is just recorded in the block end
map and adding out-going edge work elements. This means Block::end()
and Block::last() are not reliable when adding parsing work elements.
Change them to use IA_IAPI::getAddr(), which is a local object.

2 years ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:45:22 +0000 (14:45 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

2 years ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:44:20 +0000 (14:44 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

2 years agoThe power instruction decoding tables are declared as std::map.
Xiaozhu Meng [Tue, 16 Oct 2018 19:22:43 +0000 (14:22 -0500)]
The power instruction decoding tables are declared as std::map.
Currently, we use the [] operator to access entries in the table.
While the tables are mostly read-only, when we encounter instructions
that are not in the table. The [] operator may create new entries
and cause crashes. Therefore, change all accesses from [] operation
to use find() method.

2 years ago1. Use a new tbb::concurrent_hash_map to record block end.
Xiaozhu Meng [Tue, 16 Oct 2018 19:17:30 +0000 (14:17 -0500)]
1. Use a new tbb::concurrent_hash_map to record block end.
   In addition, when adding out-going edges to a block, we
   first query the block end hash map to get the accessor
   to the block. When splitting the block, we also first
   query the block end hash map to get the access to the block.
   tbb::concurrent_hash_map provides implicit read-write lock
   through the accessor. Therefore, we enforce that adding
   out-going edges are not going to be concurrent with block split.

2. Add a bunch of asserts that check edge consistency. This is
   for debug purpose and will be removed later

2 years agoRemoving function defition without declaration.
Sasha @poman [Tue, 16 Oct 2018 17:09:21 +0000 (12:09 -0500)]
Removing function defition without declaration.

2 years agocmake: use latest binutils, restrict libelf to >=0.173
LER0ever [Mon, 15 Oct 2018 02:55:26 +0000 (21:55 -0500)]
cmake: use latest binutils, restrict libelf to >=0.173
older binutils won't recognize Fedora 25 AArch64
older libelf does not have the "dwarf_next_line" function

2 years agoheaders: delete all xdr related code
LER0ever [Mon, 15 Oct 2018 02:54:27 +0000 (21:54 -0500)]
headers: delete all xdr related code

2 years agoNote for implementation added, XX3 formants in opcode 60 revised, new opcodes added
Yuhan Xie [Thu, 11 Oct 2018 23:08:46 +0000 (18:08 -0500)]
Note for implementation added, XX3 formants in opcode 60 revised, new opcodes added

Revised:
  - opcode with XX3 formats: extended opcode are expanded from 21-28 to 21-29,
with last bit treated as 0 and 1 respectively
  - The instructions with Rc bits, included Rc in the extended opcode,
treated the instructions with Rc=0 and Rc=1 as different opcodes.

new:
-xvtstdcdp (P760): DCMX field is chopped into 3 parts. May be a special case in implementation.
-**new Keyword: UIM:
   field 12-15 immediate field (xxextractuw,xxinsertw (P766))
   field 14-15 immediate field (xxspltw (P774))
  //I think UIM should be modified to a certain expression to show what exact bits are for UIM
-new Keyword: SHW:
   field 22-23 specify a shift amount in words
   skipped:
    -xxpermdi (P773), three arbitrary digits
    -xxsel (P773), XX4 form
    -xxsldwi (P774), three arbitrary digits

2 years agoAttempting to remove sink edges causes weird side effects on memory usages.
Xiaozhu Meng [Thu, 11 Oct 2018 14:16:37 +0000 (09:16 -0500)]
Attempting to remove sink edges causes weird side effects on memory usages.
Remove related code.

2 years agoFix typos in fix-point analysis for jump tables and remove sink edges when finding...
Xiaozhu Meng [Wed, 10 Oct 2018 18:54:05 +0000 (13:54 -0500)]
Fix typos in fix-point analysis for jump tables and remove sink edges when finding new edges

2 years agoA few fixes for non-returning function analysis
Xiaozhu Meng [Wed, 10 Oct 2018 15:27:11 +0000 (10:27 -0500)]
A few fixes for non-returning function analysis

1. We determine cycle by only checking the number delayed frames.
   Change it to check whether the set of delayed frames stays the same.
   This change may not be necessary, but it is safer

2. Enforce the correct order for checking function status when
   dealing with tail calls and shared code. The common code is moved
   to a new function Parser::update_function_ret_status.

   The return status starts with UNSET, and increases to RETURN, and maybe NORETURN
   Once it is RETURN or NORETURN, it will not go back to UNSET.

   Therefore, it is crucial for the following if statements to be the right order:
   First check the smaller values, and then check the larger values.

   Consider that if we reverse the order. So the code looks like
   1) if (other_func->retstatus() == RETURN) {
          ....
   2) }  else if (other_func->retstatus() == UNSET) {
          ....
      }

   In such code structure, at line 1), the other_func can be in UNSET, so the check fails.
   Concurrently, the other_func can be immediately set to RETURN, making the check at
   line 2) failing. So, the frame.func is neither delayed, nor updates its return status
   to RETURN, which can lead to wrong NORETURN status.

2 years ago1. Change the DYNINST_DEBUG_PARSING from a flag to a debug log name prefix.
Xiaozhu Meng [Tue, 9 Oct 2018 18:52:28 +0000 (13:52 -0500)]
1. Change the DYNINST_DEBUG_PARSING from a flag to a debug log name prefix.
   In parallel parsing, we need different threads to output to different files

2. Change the jump table analysis to eliminate non-determinisitic behaviors
2.1. Do not rely on the order of node in slice
2.2. Add a fix-point analysis to allow jump table analysis to redo analysis,
     discover new out-going edges due to new in-cominging edges, and continue
     parsing

2 years agoMerge branch 'master' into arm64/feature/relocation 367/head
Sasha Nicolas [Fri, 5 Oct 2018 22:40:31 +0000 (17:40 -0500)]
Merge branch 'master' into arm64/feature/relocation

2 years agoFixing update of defined registers after baseTramp is generated.
Sasha @leela [Fri, 5 Oct 2018 22:33:23 +0000 (17:33 -0500)]
Fixing update of defined registers after baseTramp is generated.

During generation of the baseTramp, registers are marked as defined
in the codeGen object, and after that we need to get this info in
order to verify whether we should perform optimizations or regenerate
the baseTramp.

2 years agobuild: move file copying to install phase
LER0ever [Fri, 5 Oct 2018 22:03:15 +0000 (17:03 -0500)]
build: move file copying to install phase

2 years agogitignore: add cmake shadow build directories
LER0ever [Fri, 5 Oct 2018 22:02:52 +0000 (17:02 -0500)]
gitignore: add cmake shadow build directories

2 years agoMinor fixes to FP Stack Unwinding through Inst Frames
Benjamin Welton [Thu, 4 Oct 2018 21:43:11 +0000 (16:43 -0500)]
Minor fixes to FP Stack Unwinding through Inst Frames

Minor fixes to stack unwinding through instrimentation (applies to First Party stackwalker only).

Added additional comments to the walker to detail how it functions more clearly and what it is looking for to
accept a stack frame.

2 years agoMerge branch 'master' of github.com:dyninst/dyninst
Benjamin Welton [Wed, 3 Oct 2018 22:38:38 +0000 (17:38 -0500)]
Merge branch 'master' of github.com:dyninst/dyninst

2 years agoModification to x86 emitter to support SW out of inst frames.
Benjamin Welton [Thu, 12 Apr 2018 17:32:31 +0000 (12:32 -0500)]
Modification to x86 emitter to support SW out of inst frames.

This patch contains changes to the emitter to support first party stackwalking out of inst's frames. For inst frames to be walkable, instrimentation frames must be enabled.

The following changes were made to support this:

- Insertion of the previous SP into the stack at a known location (2 slots above the FP).
- Insertion of a special word into the stack such that stackwalker can easily identify that this frame is an inst frame (and to select the correct walker). BEEFDEAD is located at +1 slot away from FP.
- The poping of these values from the stack at frame teardown.
- Fixes to the emitter to use scratch registers where hard coded ones were present before.

Total performance impact of this patch is an extra 5 instruction. 3 on frame creation, 2 on destruction.

2 years agoNew walker to walk out of Instrimentation Frames FP
Benjamin Welton [Thu, 12 Apr 2018 17:58:17 +0000 (12:58 -0500)]
New walker to walk out of Instrimentation Frames FP

This patch contains a new walker that can walk out of inst frames in first party stackwalking mode.

For this to work, the emitter fixes located in pull request #451 must be applied. The walker itself creates
a Stackwalker frame based on the information saved by the emitter.

2 years agoMerge pull request #452 from bwelton/sw_instFrameWalker
Benjamin Welton [Tue, 2 Oct 2018 21:43:38 +0000 (16:43 -0500)]
Merge pull request #452 from bwelton/sw_instFrameWalker

New walker to walk out of Instrumentation Frames first party. Build and test suite passes (x64, ubuntu)