dyninst.git
3 years agoNEED_NATIVE_ASSEMBLER is unused
Peter Foley [Wed, 23 Mar 2016 03:26:22 +0000 (23:26 -0400)]
NEED_NATIVE_ASSEMBLER is unused

NEED_NATIVE_ASSEMBLER is passed, but not used anywhere.
Remove it.

Signed-off-by: Peter Foley <pefoley2@pefoley.com>
3 years agoRespect make -j for DyninstRT
Peter Foley [Wed, 23 Mar 2016 03:26:20 +0000 (23:26 -0400)]
Respect make -j for DyninstRT

Use the proper variable for make so that cmake propagates the
jobserver flags properly.

Signed-off-by: Peter Foley <pefoley2@pefoley.com>
3 years agoMake getFunctionRef work
Peter Foley [Wed, 23 Mar 2016 03:26:19 +0000 (23:26 -0400)]
Make getFunctionRef work

getFunctionRef depended on undefined behavior and was otherwise
completely broken. Fix it.

Signed-off-by: Peter Foley <pefoley2@pefoley.com>
3 years agoSupport libcxx
Peter Foley [Wed, 23 Mar 2016 03:26:18 +0000 (23:26 -0400)]
Support libcxx

Allow compiling dyninst against http://libcxx.llvm.org/

Signed-off-by: Peter Foley <pefoley2@pefoley.com>
3 years agoLine info fixes to make older libdwarfs safe to use.
Bill Williams [Fri, 18 Mar 2016 20:20:53 +0000 (15:20 -0500)]
Line info fixes to make older libdwarfs safe to use.

3 years agoFixed bugs from emitElf refactoring; test suite is now clean.
Bill Williams [Thu, 17 Mar 2016 19:07:05 +0000 (14:07 -0500)]
Fixed bugs from emitElf refactoring; test suite is now clean.

3 years agoMoved Symtab parameter into emitElf class.
Bill Williams [Tue, 8 Mar 2016 20:02:46 +0000 (14:02 -0600)]
Moved Symtab parameter into emitElf class.

3 years agoPPC/little-endian build patch
Bill Williams [Tue, 8 Mar 2016 19:52:52 +0000 (13:52 -0600)]
PPC/little-endian build patch

3 years agoEmitElf refactoring, stage 1: created elfTypes traits classes. emitElf64 is now the...
Bill Williams [Thu, 18 Feb 2016 19:56:37 +0000 (13:56 -0600)]
EmitElf refactoring, stage 1: created elfTypes traits classes. emitElf64 is now the authoritative ELF emitter, and emitElf is deleted.

3 years agoMerge branch 'master' of ssh://git.dyninst.org/pub/dyninst
Sunny Shah [Mon, 14 Mar 2016 20:33:05 +0000 (15:33 -0500)]
Merge branch 'master' of ssh://git.dyninst.org/pub/dyninst

3 years agoMerge branch 'arm64'
Sunny Shah [Mon, 14 Mar 2016 20:32:14 +0000 (15:32 -0500)]
Merge branch 'arm64'

3 years agoInstructions in the load/store category with V (bit 26) set to 1 use SIMD registers...
Sunny Shah [Sun, 13 Mar 2016 06:18:31 +0000 (00:18 -0600)]
Instructions in the load/store category with V (bit 26) set to 1 use SIMD registers for Rd and Rn. Fixed now to handle this case.

3 years agoLoad/store instructions with 7-bit immediate now have the correct immediate valaue...
Sunny Shah [Fri, 11 Mar 2016 21:58:16 +0000 (15:58 -0600)]
Load/store instructions with 7-bit immediate now have the correct immediate valaue for both SIMD and non-SIMD instructions.

3 years agoCalculation of immediate operand in logical immediate instructions was done wrong...
Sunny Shah [Fri, 11 Mar 2016 18:27:53 +0000 (12:27 -0600)]
Calculation of immediate operand in logical immediate instructions was done wrong. Fixed now to calculate it according to the DecodeBitMasks function of the ARMv8 manual (page 5595) -- this is per the semantics of the instructions of the logical immediate category.

3 years agoFixed missing semi-colon, and removed un-needed macros from the header.
Sunny Shah [Tue, 8 Mar 2016 22:56:26 +0000 (16:56 -0600)]
Fixed missing semi-colon, and removed un-needed macros from the header.

3 years agoFormatting changes to about half of the file to make the formatting consistent throug...
Sunny Shah [Tue, 8 Mar 2016 22:51:10 +0000 (16:51 -0600)]
Formatting changes to about half of the file to make the formatting consistent throughout.

3 years agoAll immh:immb values are valid for SIMD (non-scalar) shift by immediate instructions...
Sunny Shah [Tue, 8 Mar 2016 22:30:29 +0000 (16:30 -0600)]
All immh:immb values are valid for SIMD (non-scalar) shift by immediate instructions. Updated the code to allow this.

3 years agoFix for correctly identifying all instructions in the SIMD modified immediate category.
Sunny Shah [Tue, 8 Mar 2016 07:12:38 +0000 (01:12 -0600)]
Fix for correctly identifying all instructions in the SIMD modified immediate category.

All instructions in the above mentioned category were getting detected as MOVI. This has now been fixed by adding a few manually encoded entries to the instruction table to correctly identify these instructions.

3 years agoFixed issue of all SIMD modified immediate and shift by immediate instructions flatte...
Sunny Shah [Mon, 7 Mar 2016 23:42:02 +0000 (17:42 -0600)]
Fixed issue of all SIMD modified immediate and shift by immediate instructions flattening to the same instruction (MOVI).

Due to pecularities of the instruction encodings of SIMD modified immediate and shift by immediate instructions, all instructions in both sets (except shift by immediate instructions with lowest bit of opcode equal to 1) were getting treated as movi. This has been fixed. Modified immediate instructions, however, still all flatten to MOVI - the fix for this will be made later.

Also cleaned up code in the ARM decoder.

3 years agoField opc with value 3 in case of load/store literal instructions is a valid PRFM...
Sunny Shah [Tue, 1 Mar 2016 19:03:26 +0000 (13:03 -0600)]
Field opc with value 3 in case of load/store literal instructions is a valid PRFM instruction, not an invalid instruction.

3 years agoFixes to correctly handle the PRFM instruction.
Sunny Shah [Mon, 29 Feb 2016 22:11:27 +0000 (16:11 -0600)]
Fixes to correctly handle the PRFM instruction.

3 years agoFixes to correctly handle SIMD load/store single structure post-indexed category
Sunny Shah [Mon, 29 Feb 2016 19:26:44 +0000 (13:26 -0600)]
Fixes to correctly handle SIMD load/store single structure post-indexed category

3 years agoFixes to correctly handle SIMD load/store single structure instructions
Sunny Shah [Mon, 29 Feb 2016 06:03:03 +0000 (00:03 -0600)]
Fixes to correctly handle SIMD load/store single structure instructions

3 years agoFixes based on testing SIMD vector x indexed, load/store multiple structures and...
Sunny Shah [Fri, 26 Feb 2016 21:49:32 +0000 (15:49 -0600)]
Fixes based on testing SIMD vector x indexed, load/store multiple structures and load/store multiple structures post-indexed categories.

Most fixes revolve around adding the correct registers (several cases had been left out in the load/store categories) and taking care of the read/write properties of the registers (again, most problems were in the load/store instructions).

4 years agoStopped bottoming target registers of add/sub in some situations.
Matt Morehouse [Mon, 22 Feb 2016 16:21:35 +0000 (10:21 -0600)]
Stopped bottoming target registers of add/sub in some situations.

When add/sub reads an argument from a topped memory location, we
now round the target register to top or bottom rather than always
setting it to bottom.

4 years agoImproved handling of sign/zero extends.
Matt Morehouse [Fri, 19 Feb 2016 18:08:51 +0000 (12:08 -0600)]
Improved handling of sign/zero extends.

Extended memory-tracking to include sign/zero extends, made sign/
zero extends from topped locations yield topped values, and
implemented better handling of CBW and CWDE instructions.

4 years agoStarted topping loads from undetermined (topped) locations.
Matt Morehouse [Tue, 16 Feb 2016 16:58:38 +0000 (10:58 -0600)]
Started topping loads from undetermined (topped) locations.

Also made modifications to StackMod so that storing stack pointers
to topped locations results in the function being uninstrumentable.

4 years agoMemory leak fixes and stopped tracking topped locations.
Matt Morehouse [Mon, 8 Feb 2016 19:47:29 +0000 (13:47 -0600)]
Memory leak fixes and stopped tracking topped locations.

Various data structures were being dynamically allocated and never
freed.  Some of these structures I was able to switch to stack
allocation and others I was able to free when they were no longer
needed.

Additionally, several std::map objects were maintaining entries for
locations that did not contain stack heights.  By eliminating these
entries, I was able to drastically reduce memory consumption while
speeding up the fixpoint analysis.

4 years agoImplemented naive stack slot tracking.
Matt Morehouse [Tue, 26 Jan 2016 15:02:07 +0000 (09:02 -0600)]
Implemented naive stack slot tracking.

This is done by performing a second fixpoint analysis after
register stack heights are determined in the first fixpoint
analysis.

4 years agoTightened up add/sub handling and added support for addsd/movsd.
Matt Morehouse [Tue, 19 Jan 2016 14:50:21 +0000 (08:50 -0600)]
Tightened up add/sub handling and added support for addsd/movsd.

4 years agoImproved LEA handling and added mul/div handling.
Matt Morehouse [Wed, 13 Jan 2016 20:09:32 +0000 (14:09 -0600)]
Improved LEA handling and added mul/div handling.

4 years agoImplemented basic memory tracking for stack analysis.
Matt Morehouse [Fri, 11 Dec 2015 15:10:23 +0000 (09:10 -0600)]
Implemented basic memory tracking for stack analysis.

Addresses that can be statically determined (e.g. global variables)
are now tracked in the same manner as registers. Currently only the
MOV instruction is handled for memory loads and stores. There are
plans to add sign/zero extends in the near future.

4 years agoMade several improvements to our stack analysis code.
Matt Morehouse [Tue, 17 Nov 2015 16:55:11 +0000 (10:55 -0600)]
Made several improvements to our stack analysis code.

1. Added handler for XOR zeroing.
2. Set caller-save registers to topBottom after a function call
   rather than bottom (as before).
3. Set registers containing memory-loaded values to bottom rather
   than topBottom (as before).

4 years agoFixed issue with tail call recognition
Matt Morehouse [Mon, 12 Oct 2015 14:46:18 +0000 (09:46 -0500)]
Fixed issue with tail call recognition

We now use the exitBlocks() method instead of callEdges() due to
changes in ParseAPI.

4 years agoFixed segfault on instantiation of non-seeded Randomize objects
Matt Morehouse [Mon, 21 Sep 2015 19:05:36 +0000 (14:05 -0500)]
Fixed segfault on instantiation of non-seeded Randomize objects

4 years agoFixed bug related to falsely recognizing memory accesses
Matt Morehouse [Mon, 21 Sep 2015 19:02:35 +0000 (14:02 -0500)]
Fixed bug related to falsely recognizing memory accesses

Some instructions were being incorrectly identified as accessing memory.

4 years agoBuild compatibility with Visual Studio 2015.
Allison Morris [Tue, 23 Feb 2016 18:53:08 +0000 (12:53 -0600)]
Build compatibility with Visual Studio 2015.

+C99 Support:
Older versions of Microsoft's compiler lack support for some C99
functions, such as snprintf. This commit removes Windows-only macros
on VS 2015 builds that were used to provide snprintf. These macros
are still intact for builds using older versions of MSVC.

+Initializer List Support:
Some of DataflowAPI used Boost libraries in Windows builds to make up
for MSVC's lack of initializer list support. Our initializer list code
is now used on VS 2015+ builds, while the Boost code continues to be
used in older MSVC builds.

4 years agoFixed source register addition for the SIMD table lookup category.
Sunny Shah [Mon, 22 Feb 2016 17:42:31 +0000 (11:42 -0600)]
Fixed source register addition for the SIMD table lookup category.

An extra second source register was getting added for the SIMD table lookup instructions. This has now been fixed.

4 years agoReplaced most asserts with a flag marking the instruction as invalid.
Sunny Shah [Mon, 22 Feb 2016 01:22:54 +0000 (19:22 -0600)]
Replaced most asserts with a flag marking the instruction as invalid.

Except for the cases where the assert didn't depend on the value of a field in the instruction, all of them have been replaced as described above.

4 years agoFixed detection of correct second source register for SIMD scalar X indexed instructi...
Sunny Shah [Fri, 19 Feb 2016 22:46:03 +0000 (16:46 -0600)]
Fixed detection of correct second source register for SIMD scalar X indexed instruction category.

The lower nibble of the opcode needs to be checked, and not the higher nibble.
Also set destination register read for some instructions in the SIMD modified immediate category.

4 years agoAdded support for SIMD scalar 3 same instruction category.
Sunny Shah [Thu, 18 Feb 2016 19:26:39 +0000 (13:26 -0600)]
Added support for SIMD scalar 3 same instruction category.

4 years agoAdded logic to detect invalid instructions in the SIMD scalar shift by immediate...
Sunny Shah [Tue, 16 Feb 2016 22:21:20 +0000 (16:21 -0600)]
Added logic to detect invalid instructions in the SIMD scalar shift by immediate category

4 years agoBug fixes from issues found by Nathan during fuzz testing
Sunny Shah [Tue, 16 Feb 2016 21:37:47 +0000 (15:37 -0600)]
Bug fixes from issues found by Nathan during fuzz testing

* All instructions that point to the INVALID entry of the instruction table have isValid marked as false, to prevent any form of operand post-processing on them. Such post processing was happening before this fix and was an incorrect implementation.
* The code for parsing immediates for scalar shift by immediate SIMD category is same as that for the non-scalar(variant) variant, but wasn;t gettubg executed for the scalar variant. A check has now been added to execute it for the scalar variant as well.

4 years agoBug fixes for SIMD instruction support.
Sunny Shah [Fri, 12 Feb 2016 18:24:44 +0000 (12:24 -0600)]
Bug fixes for SIMD instruction support.

Registers for the scalar pairwise category weren't being set correctly for the Rn field, and not at all for the Rd field. This has now been fixed.

4 years agoARM64 non-register branch and return instructions now have their correct category...
Sunny Shah [Fri, 12 Feb 2016 17:17:25 +0000 (11:17 -0600)]
ARM64 non-register branch and return instructions now have their correct category set.

This is used by ParseAPI to determine the type of an instruction when building basic blocks.

4 years agoBug fixes and optimizations after more testing
Sunny Shah [Thu, 11 Feb 2016 20:15:53 +0000 (14:15 -0600)]
Bug fixes and optimizations after more testing

* Optimized creation of 64-bit immediate from the a,b,c,d,e,f,g and h operands
* Fixes to correctly handle shift amounts for the SIMD modified immediate category

4 years agoFixed bugs found during testing (using the aarch64_simd test).
Sunny Shah [Tue, 9 Feb 2016 22:03:24 +0000 (16:03 -0600)]
Fixed bugs found during testing (using the aarch64_simd test).

* The register alias H_REG is renamed to HQ_REG to improve readability. It also has a size associated with it now (dyn_regs.C).
* Several assignments of isValid were true instead of false, this has been fixed.
* Changed macro definition for non-SIMD load/store instructions to not also include SIMD instructions

4 years agoParseAPI with support for direcct control flow on ARM64.
Sunny Shah [Fri, 5 Feb 2016 23:34:39 +0000 (17:34 -0600)]
ParseAPI with support for direcct control flow on ARM64.

ParseAPI now supports direct control flow on ARM64. I'd made a commit of all the changes earlier, but looks like it didn't go through.
This commit contains all the changes: all functions required to support direct control flow are implemented. IA_aarch64.h is deleted as it no longer required at this stage.

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Tue, 2 Feb 2016 21:34:41 +0000 (15:34 -0600)]
Added support for following SIMD instruction categories:

* Scalar shift by immediate
* Scalar 2 register miscellaneous

Also added utility functions for finding the number of the highest and lowest set bits in a 32-bit integer.

4 years agoAdded support for the following SIMD instruction categories:
Sunny Shah [Thu, 28 Jan 2016 21:08:05 +0000 (15:08 -0600)]
Added support for the following SIMD instruction categories:

* Scalar pairwise
* Scalar 3 different
* Scaalr 3 same
* Scalar X indexed

Also implemented OPRsize function to record the value of the "size" field. Re-used the _szField variable for this.

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Mon, 25 Jan 2016 20:06:12 +0000 (14:06 -0600)]
Added support for following SIMD instruction categories:

* Vector X indexed element
* Scalar copy

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Fri, 22 Jan 2016 21:44:12 +0000 (15:44 -0600)]
Added support for following SIMD instruction categories:

* 3 different
* 3 same
* 2 register miscellaneous

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Wed, 20 Jan 2016 22:34:39 +0000 (16:34 -0600)]
Added support for following SIMD instruction categories:

* Permute
* Shift by immediate
* Table lookup

4 years agoAdded support for the following SIMD instruction categories:
Sunny Shah [Tue, 19 Jan 2016 02:32:00 +0000 (20:32 -0600)]
Added support for the following SIMD instruction categories:
* Across lanes
* Copy
* Extract
* Modified Immediate

The first of the above two had been implemented by Steve but several cases had been left out; those have been handled now.

4 years agoError propagation and trusted code in defensive mode.
Allison Morris [Tue, 12 Jan 2016 03:37:27 +0000 (21:37 -0600)]
Error propagation and trusted code in defensive mode.

+Error checking and propagation:
Defensive mode parses all modules at start-up and instruments most
functions. This commit checks for errors and propagates them to the
upper layer. If any instrumentation fails, an error message is printed
and the process is aborted.

+Trusted code:
Defensive mode now uses a whitelist to mark certain system libraries as
safe. These are not parsed or instrumented at start-up. A new mechanism
exists for switching safe modules to defensive at runtime.

4 years agoVarious DataflowAPI, DyninstAPI, PatchAPI, and runtime fixes.
Allison Morris [Tue, 12 Jan 2016 03:33:25 +0000 (21:33 -0600)]
Various DataflowAPI, DyninstAPI, PatchAPI, and runtime fixes.

+Stack analysis:
Minor changes to our definitions of transfer functions to produce more
consistent results when calculating stack heights.

+Dynamic target expressions:
This expression works again on Windows and Linux.

+Springboard generation:
Fixes a null pointer bug that occurs when a trap is used instead of a jump
to reach relocated code.

+Windows traps:
Using traps for instrumentation is now enabled on Windows builds.

+Error propagation:
Errors applying instrumentation in PatchAPI now propagate to the
DyninstAPI layer.

+Runtime variables:
Restores a missing runtime variable.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Sun, 3 Jan 2016 21:25:06 +0000 (15:25 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years ago fixed some compiling errors. noted what have been implemented.
SteveXiSong [Sun, 3 Jan 2016 21:18:10 +0000 (15:18 -0600)]
 fixed some compiling errors. noted what have been implemented.

4 years agoadded symbols for more mem access width
SteveXiSong [Fri, 1 Jan 2016 20:31:19 +0000 (14:31 -0600)]
added symbols for more mem access width

4 years agoadd more logic for SIMD instructions
SteveXiSong [Wed, 30 Dec 2015 21:53:48 +0000 (15:53 -0600)]
add more logic for SIMD instructions

4 years agoUpdated test files to have same logic as in ARM's instruction API file.
Sunny Shah [Wed, 16 Dec 2015 21:52:22 +0000 (15:52 -0600)]
Updated test files to have same logic as in ARM's instruction API file.

4 years agoMerge branch 'v9.1.x' of ssh://follis/p/paradyn/development/bill/head/dyninst into... v9.1.0
Paradyn [Wed, 16 Dec 2015 17:09:59 +0000 (11:09 -0600)]
Merge branch 'v9.1.x' of ssh://follis/p/paradyn/development/bill/head/dyninst into v9.1.x

4 years ago9.1 Word-based doc updates
Paradyn [Wed, 16 Dec 2015 17:09:04 +0000 (11:09 -0600)]
9.1 Word-based doc updates

4 years agoReverting opcode decoding logic to what we used earlier.
Sunny Shah [Tue, 15 Dec 2015 18:47:45 +0000 (12:47 -0600)]
Reverting opcode decoding logic to what we used earlier.

The decoder table no longer has a list of indices into the instruction table (which was done to support strict solution to aliasing) but just one index which corresponds to the most general instruction.
Modifying the opcode decoding logic to conform to this form of aliasing.

4 years agoConsistency fix
Bill Williams [Tue, 15 Dec 2015 18:22:14 +0000 (12:22 -0600)]
Consistency fix

4 years agoAdd explicit include for BPatch_object.h
Bill Williams [Tue, 15 Dec 2015 18:20:28 +0000 (12:20 -0600)]
Add explicit include for BPatch_object.h

4 years agoFinal bits of cleanup (warnings and version numbers).
Bill Williams [Fri, 11 Dec 2015 20:46:05 +0000 (14:46 -0600)]
Final bits of cleanup (warnings and version numbers).

4 years agoBPatch_object::findFunction should no longer spam BPatch errors for each of its modul...
Bill Williams [Thu, 10 Dec 2015 19:48:24 +0000 (13:48 -0600)]
BPatch_object::findFunction should no longer spam BPatch errors for each of its modules that don't contain the function requested.

4 years agoBPatch library callbacks now return a BPatch_object, in line with change from module...
Bill Williams [Thu, 10 Dec 2015 19:47:37 +0000 (13:47 -0600)]
BPatch library callbacks now return a BPatch_object, in line with change from module->object for representing libraries.

4 years agoUpdated READMEs
Bill Williams [Wed, 9 Dec 2015 22:24:33 +0000 (16:24 -0600)]
Updated READMEs

4 years agofixed a few bugs after rolling backing to weak solution to aliases
SteveXiSong [Tue, 8 Dec 2015 19:38:11 +0000 (13:38 -0600)]
fixed a few bugs after rolling backing to weak solution to aliases

4 years agoupaded instructionAPI to roll back to weak solution to instruction aliases
SteveXiSong [Tue, 8 Dec 2015 18:40:45 +0000 (12:40 -0600)]
upaded instructionAPI to roll back to weak solution to instruction aliases

4 years agoDon't try to follow indirect catch blocks; they probably are not statically resolvabl...
Bill Williams [Mon, 7 Dec 2015 20:20:44 +0000 (14:20 -0600)]
Don't try to follow indirect catch blocks; they probably are not statically resolvable (and may segfault if we try).

4 years agoException block parsing fixes to match glibc internals:
Bill Williams [Mon, 7 Dec 2015 17:26:47 +0000 (11:26 -0600)]
Exception block parsing fixes to match glibc internals:

* DW_EH_PE_aligned refers to alignment within the .eh_frame section, not alignment of the target
* DW_EH_PE_indirect accounts for the "mysterious" bit at 0x80 in the type field, and should be respected.
* Zero values do not get the base added, but are ignored.
* Read the landing pad base if it's present, and use it; default to low_pc as before.
* Table end is always encoded as ULEB128, apparently.

4 years agoSlicing: ignore catch edges.
Bill Williams [Mon, 7 Dec 2015 17:23:12 +0000 (11:23 -0600)]
Slicing: ignore catch edges.

4 years agoFix string corruption in use of symtab names.
Bill Williams [Thu, 3 Dec 2015 17:17:36 +0000 (11:17 -0600)]
Fix string corruption in use of symtab names.

4 years agoFix bad handling of high_pc errors and bad default libdwarf error handler.
Bill Williams [Wed, 25 Nov 2015 22:17:23 +0000 (16:17 -0600)]
Fix bad handling of high_pc errors and bad default libdwarf error handler.

4 years agoFix dwarf_attr leak, which could get quite large with repeated line info queries.
Bill Williams [Fri, 20 Nov 2015 21:01:36 +0000 (15:01 -0600)]
Fix dwarf_attr leak, which could get quite large with repeated line info queries.

4 years agoFix bad decodes (per testsuite, which is actually correct on this one).
Bill Williams [Fri, 20 Nov 2015 21:01:11 +0000 (15:01 -0600)]
Fix bad decodes (per testsuite, which is actually correct on this one).

4 years agoupdated decoder-aarch64.C & .h to support LDST SIMD single structure instructions.
SteveXiSong [Tue, 8 Dec 2015 05:22:13 +0000 (23:22 -0600)]
updated decoder-aarch64.C & .h to support LDST SIMD single structure instructions.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 8 Dec 2015 02:12:12 +0000 (20:12 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoupdated decoder-aarch64 for LDST SIMD
SteveXiSong [Tue, 8 Dec 2015 02:12:05 +0000 (20:12 -0600)]
updated decoder-aarch64 for LDST SIMD

4 years agoModified byte-ordering used for instruction decoding for ARM64.
Sunny Shah [Mon, 7 Dec 2015 16:18:42 +0000 (10:18 -0600)]
Modified byte-ordering used for instruction decoding for ARM64.

The code was assuming ARM to be big endian while it is not. Modified the decode method to get instruction bytes according to litle-endian order.

4 years agoFixed endian-ness of ARM.
Sunny Shah [Mon, 7 Dec 2015 03:00:39 +0000 (21:00 -0600)]
Fixed endian-ness of ARM.

The code was assuming ARM to be big endian while it is not. Modified the decode method to get instructions bytes according to litle-endian order.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 1 Dec 2015 20:22:26 +0000 (14:22 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoupdated makeReg functions to support SIMD
SteveXiSong [Tue, 1 Dec 2015 20:22:14 +0000 (14:22 -0600)]
updated makeReg functions to support SIMD

4 years agoFix bad handling of high_pc errors and bad default libdwarf error handler.
Bill Williams [Wed, 25 Nov 2015 22:17:23 +0000 (16:17 -0600)]
Fix bad handling of high_pc errors and bad default libdwarf error handler.

4 years agoUsage of the struct fields to check the instruction's mask with the mask bits was...
Sunny Shah [Wed, 25 Nov 2015 21:24:35 +0000 (15:24 -0600)]
Usage of the struct fields to check the instruction's mask with the mask bits was incorrect. Fixed to use the correct fields.

4 years agoModified decoder and instruction table walking logic to support last change related...
Sunny Shah [Wed, 25 Nov 2015 20:55:45 +0000 (14:55 -0600)]
Modified decoder and instruction table walking logic to support last change related to aliasing to the tables.

* A list of instruction table indices is stored with each decoder table entry.
* If the above list is of size 1, simply use that index to get the instruction.
* If the list is not of size 1, walk through each instruction table entry and check if the masked value of the current instruction matches the masked value stored in the entry.
* If the mask matches, return that entry as the instruction. Else, move on to the next entry.

4 years agoupdated the script with strict solution to aliasing
SteveXiSong [Tue, 24 Nov 2015 04:41:09 +0000 (22:41 -0600)]
updated the script with strict solution to aliasing

4 years agoMerge branch 'v9.1.x' of ssh://git.dyninst.org/pub/dyninst into v9.1.x
Bill Williams [Fri, 20 Nov 2015 23:00:27 +0000 (17:00 -0600)]
Merge branch 'v9.1.x' of ssh://git.dyninst.org/pub/dyninst into v9.1.x

4 years agoupdated the method to handle compiler bug when template functions appears first
SteveXiSong [Fri, 20 Nov 2015 22:40:37 +0000 (16:40 -0600)]
updated the method to handle compiler bug when template functions appears first

4 years agofixed the compiler bug when OPRimm appears at the first place of boost::list_of
SteveXiSong [Fri, 20 Nov 2015 21:37:27 +0000 (15:37 -0600)]
fixed the compiler bug when OPRimm appears at the first place of boost::list_of

4 years agoFix dwarf_attr leak, which could get quite large with repeated line info queries.
Bill Williams [Fri, 20 Nov 2015 21:01:36 +0000 (15:01 -0600)]
Fix dwarf_attr leak, which could get quite large with repeated line info queries.

4 years agoFix bad decodes (per testsuite, which is actually correct on this one).
Bill Williams [Fri, 20 Nov 2015 21:01:11 +0000 (15:01 -0600)]
Fix bad decodes (per testsuite, which is actually correct on this one).

4 years agoupdated decoder generator with class structure
SteveXiSong [Thu, 19 Nov 2015 00:08:49 +0000 (18:08 -0600)]
updated decoder generator with class structure

4 years agofixed insn_print merge conflicts
SteveXiSong [Wed, 18 Nov 2015 21:55:24 +0000 (15:55 -0600)]
fixed insn_print merge conflicts

4 years agofixed insn_printf
SteveXiSong [Wed, 18 Nov 2015 02:14:17 +0000 (20:14 -0600)]
fixed insn_printf

4 years agofixed insn_print bugs
SteveXiSong [Tue, 17 Nov 2015 18:55:12 +0000 (12:55 -0600)]
fixed insn_print bugs

4 years agoMerge branch 'v9.1.x' into arm64
SteveXiSong [Mon, 16 Nov 2015 23:06:06 +0000 (17:06 -0600)]
Merge branch 'v9.1.x' into arm64