dyninst.git
2 years ago10/23
Yuhan Xie [Tue, 23 Oct 2018 20:23:08 +0000 (15:23 -0500)]
10/23
Chapter 6

new:
    keyword CY, 21th bit
    keyword ST, 16th bit
    keyword SIX, 17-20
    keyword DRM, 18-20
    keyword RM, 19-20
    (ST and SIX always show up together)
    keyword PS, 22th bit

Summary of Changable fields:
UIM:
11-15:
   4-906 vctuxs,
   4-970 vctsxs,

  12-15:
     4-524 vspltb
     4-525 vextractub
     4-589 vextractuh
     4-653 vextractuw
     4-717 vextractd
     4-781 vinsertb
     4-845 vinserth
     4-909 vinsertw
     4-973 vinsertd

4-588 vsplth 13-15

4-652 vspltw 14-15

Rc bit:
  for opcode 4: always 21th bit

6-bit(26-31) ext opcode for opcode 4:
   32-47, 59-63

2 years agoAdding multiple items for Power 8 instruction decoding
Xiaozhu Meng [Fri, 19 Oct 2018 16:21:40 +0000 (11:21 -0500)]
Adding multiple items for Power 8 instruction decoding

1. VSR registers
2. Decoding for several operand fields
3. Decoding for extended op 60

2 years ago10/18 Opcode from Chapter 6
Yuhan Xie [Thu, 18 Oct 2018 20:43:46 +0000 (15:43 -0500)]
10/18 Opcode from Chapter 6

Summary of Changable fields:
  UIM:
  12-15:
4-524 vspltb
4-525 vextractub
4-589 vextractuh
4-653 vextractuw
4-717 vextractd
4-781 vinsertb
4-845 vinserth
4-909 vinsertw
4-973 vinsertd
13-15:
4-588 vsplth
    14-15:
4-652 vspltw

  Rc bit:
for opcode 4: always 21th bit

ext opcode for opcode 4:
    26-31: 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 59, 60, 61, 62, 63

new:
  Keyword SIM, 11-15 bits
    Keyword SHB, 22-25 bits
third-level opcode: 4-1538-x

2 years agoStart to integrate new power opcodes
Xiaozhu Meng [Thu, 18 Oct 2018 16:57:24 +0000 (11:57 -0500)]
Start to integrate new power opcodes

2 years ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:45:22 +0000 (14:45 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

2 years ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:44:20 +0000 (14:44 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

2 years agoNote for implementation added, XX3 formants in opcode 60 revised, new opcodes added
Yuhan Xie [Thu, 11 Oct 2018 23:08:46 +0000 (18:08 -0500)]
Note for implementation added, XX3 formants in opcode 60 revised, new opcodes added

Revised:
  - opcode with XX3 formats: extended opcode are expanded from 21-28 to 21-29,
with last bit treated as 0 and 1 respectively
  - The instructions with Rc bits, included Rc in the extended opcode,
treated the instructions with Rc=0 and Rc=1 as different opcodes.

new:
-xvtstdcdp (P760): DCMX field is chopped into 3 parts. May be a special case in implementation.
-**new Keyword: UIM:
   field 12-15 immediate field (xxextractuw,xxinsertw (P766))
   field 14-15 immediate field (xxspltw (P774))
  //I think UIM should be modified to a certain expression to show what exact bits are for UIM
-new Keyword: SHW:
   field 22-23 specify a shift amount in words
   skipped:
    -xxpermdi (P773), three arbitrary digits
    -xxsel (P773), XX4 form
    -xxsldwi (P774), three arbitrary digits

2 years agoOpcode conflict detected, new opcodes added
Yuhan Xie [Tue, 2 Oct 2018 21:26:08 +0000 (16:26 -0500)]
Opcode conflict detected, new opcodes added

p576-690(include but skipped)

skipped:

  -xsrqpi & xsrqpix, P634, two instructions sharing the same opcode, differentiated by EX bit
  -xssqrtsp, P644, xssqrtsp has the exact same opcode with xscmpgtdp (P526)
  -xvcmpgtdp, P668, has exact the same opcode with xsrdpic(P628)
  -xvcmpgtsp, P670, has exact the same opcode with xssqrtdp(P641)
  -xvcvspsxws, P686, has exact the same opcode with xsminjdp(P589)
  -xvcvspuxws, P690, has exact the same opcode with xsmincdp(P587)

new keywords included:
  -P653, included DCMX
  -P636, included RMC, two bit from 21th, always companied with an R bit in the 15th bit.
  -new third level opcode 60-475

2 years ago09/27/2018 New opcodes added
Yuhan Xie [Thu, 27 Sep 2018 21:11:31 +0000 (16:11 -0500)]
09/27/2018 New opcodes added

p523-576(not including p576)

skipped:
nothing

new:
  -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25
  -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log.
  -new keyword included: VRS
  -lxvx: page 492, two entries for this instruction(a slash inside the extened opcode).31-268 & 31-300

2 years ago09/27/2018 New opcodes added
Yuhan Xie [Thu, 27 Sep 2018 21:02:58 +0000 (16:02 -0500)]
09/27/2018 New opcodes added

p523-576(not including p576)

skipped:
nothing

new:
  -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25
  -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log.
  -new keyword included: VRS
  -lxvx: page 492, a slash inside the extened opcode.two entries in the opcode table are included: 31-268 & 31-300

2 years ago09/25
Yuhan Xie [Tue, 25 Sep 2018 22:05:48 +0000 (17:05 -0500)]
09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
         lxvx (P492, a slash in the memory map and two numbers are included)
 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
 stxssp (P501, VRS)
 stxv (P507, new keyword DQ)
 xsabsqp (P512, 0 in it)

new keywords included:

-included new keywords "XS", it should be the storing version of "XT")
-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)

2 years agoMerge branch 'power_vector' of github.com:dyninst/dyninst into power_vector
Yuhan Xie [Tue, 25 Sep 2018 22:03:53 +0000 (17:03 -0500)]
Merge branch 'power_vector' of github.com:dyninst/dyninst into power_vector

2 years ago09/25
Yuhan Xie [Tue, 25 Sep 2018 19:56:35 +0000 (14:56 -0500)]
09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
         lxvx (P492, a slash in the memory map and two numbers are included)
 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
 stxssp (P501, VRS)
 stxv (P507, new keyword DQ)
 xsabsqp (P512, 0 in it)

new keywords included:

-included new keywords "XS", it should be the storing version of "XT")
-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)

2 years agoP492-523
Yuhan Xie [Tue, 25 Sep 2018 19:56:35 +0000 (14:56 -0500)]
P492-523

2 years agoadded power operations, stopped on pg491 of the manual page, lxvll
Yuhan Xie [Thu, 20 Sep 2018 21:31:31 +0000 (16:31 -0500)]
added power operations, stopped on pg491 of the manual page, lxvll

2 years agoTemplate for adding instructions
Benjamin Welton [Thu, 20 Sep 2018 19:54:53 +0000 (14:54 -0500)]
Template for adding instructions

2 years agoadded arithExpr xor
van Hauser [Sat, 24 Mar 2018 12:46:06 +0000 (13:46 +0100)]
added arithExpr xor
(cherry picked from commit eee4b0740bb24e07581af453392220808ac0524c)

2 years agoMerge pull request #485 from dyninst/power8_instrumentation_fix
Xiaozhu Meng [Fri, 7 Sep 2018 16:26:45 +0000 (11:26 -0500)]
Merge pull request #485 from dyninst/power8_instrumentation_fix

Power8 instrumentation fix

2 years agoRemove debugging printf statement 485/head
Xiaozhu Meng [Fri, 7 Sep 2018 16:03:51 +0000 (11:03 -0500)]
Remove debugging printf statement

2 years agoThe fixes for power preamble should not be enabled on other platforms
Xiaozhu Meng [Fri, 7 Sep 2018 15:57:49 +0000 (10:57 -0500)]
The fixes for power preamble should not be enabled on other platforms
and suppress unncessary warning output

2 years agoSetting the default value of pointers encoding
Sasha Nicolas [Thu, 6 Sep 2018 22:14:20 +0000 (17:14 -0500)]
Setting the default value of pointers encoding
in a Frame Description Entry (FDE) to be DW_EH_PE_absptr.

2 years agoFix power rewriter mode
Xiaozhu Meng [Thu, 6 Sep 2018 18:55:58 +0000 (13:55 -0500)]
Fix power rewriter mode

1. there is no longer .opd section in Power 8 binaries. We used to derived TOC for each
   function based on .opd section. Such code is outdated.
2. Fix genearting calls to PLT on power. If the caller and the callee are not in the
   same object, we need a PLT call.
3. Fix getting the same scratch registers

2 years agoFix for test1_30:
Sasha Nicolas [Wed, 5 Sep 2018 17:51:41 +0000 (12:51 -0500)]
Fix for test1_30:
this test would show PASSED but in reality the return value of the
functions getAddressRanges either in BPatch_image or BPatch_module was
false, meaning the ranges weren't being found correctly.
It turns out that the comparison between filenames was wrong.
For this fix, StringTableEntry needed to be changed in other to store the filename
without the path, and thus allow StringTable boost::multi_index_container
to be indexed by "filename" and not only by "/path/filename".

2 years agoTwo more fixes for instrumentation on power. Now all tests in create and attach modes...
Xiaozhu Meng [Wed, 5 Sep 2018 17:49:52 +0000 (12:49 -0500)]
Two more fixes for instrumentation on power. Now all tests in create and attach modes are passing.

1. call site instrumentation point should return the real function rather than the targ function
2. loop tree node should not include targ functions as callee

2 years agoMore fixes for power instrumentation
Xiaozhu Meng [Wed, 5 Sep 2018 13:24:37 +0000 (08:24 -0500)]
More fixes for power instrumentation

1. Do not relocate the power preamble by skipping the first two instructions,
   instead of comparing addresses
2. RelocGraph indexes RelocBlock by block starting address rather than
   block_instance pointers
3. Function entry springboard is now using OffLimits springboard priority,
   as it should have a higher priority than block entry springboard.

2 years ago1. Copy Ben's fix for code gen on power
Xiaozhu Meng [Mon, 3 Sep 2018 17:09:45 +0000 (12:09 -0500)]
1. Copy Ben's fix for code gen on power
2. Make sure we skip the function preamble when genearting springboard
3. Reloc block now can be empty, so should not assert

2 years agoStart to make instrumentation on Power8 work.
Xiaozhu Meng [Thu, 30 Aug 2018 18:42:26 +0000 (13:42 -0500)]
Start to make instrumentation on Power8 work.

The first issue is about the new power ABI, where each function has two entries.
The inter-procedural entry has the function name and the intra-procedural entry
does not, and so is named as targXXXX. We do two things here:
1. We should not relocate targXXXX as it is essentially the same function as the inter-procedural one.
2. The inter-procedural entry contains two preamble to set up the value of r2 (TOC). We should
   not relocate these two instructions. So, when creating a RelocBlock for such entry, we skip
   the first two instructions.

The second issue is about generating long branches. This is related to springboard
and generating function call instrumentation (as function call on power is branch).
For calls, Ben introduces the uses of TAR register to store the target address. The
power manual says TAR register is reserved for system software. We will need to
revisit the use of TAR register. For long springboard, right now we cannot create an
instPoint to do liveness. So, long springboards are now done by traps.

2 years agoPower8 does not necessary have the .opd section
Xiaozhu Meng [Tue, 28 Aug 2018 14:50:15 +0000 (09:50 -0500)]
Power8 does not necessary have the .opd section

2 years agoThe instruction semantics code for push should consider different
Xiaozhu Meng [Mon, 27 Aug 2018 15:29:57 +0000 (10:29 -0500)]
The instruction semantics code for push should consider different
register sizes

2 years agoShould prefer CU level line info parsing over object level line info
Xiaozhu Meng [Fri, 24 Aug 2018 20:31:45 +0000 (15:31 -0500)]
Should prefer CU level line info parsing over object level line info
parsing when there is a seperate debug info file

2 years agoWhen the ".debug_info" section is not present, we do object level line
Xiaozhu Meng [Fri, 24 Aug 2018 16:45:22 +0000 (11:45 -0500)]
When the ".debug_info" section is not present, we do object level line
infomation parsing. However, when we iterate every module in the object,
we will re-parse the line information for the whole object. We should
just parse once and share the parsing results in different modules.

2 years agoFix wrong register operands in x86-64 instruction decoding
Xiaozhu Meng [Thu, 23 Aug 2018 15:51:29 +0000 (10:51 -0500)]
Fix wrong register operands in x86-64 instruction decoding

2 years agoMerge pull request #463 from dyninst/vector_categories
Xiaozhu Meng [Wed, 22 Aug 2018 14:24:34 +0000 (09:24 -0500)]
Merge pull request #463 from dyninst/vector_categories

Vector categories merge into master

2 years ago1. The FULL register size must have value 0 due to the way we calculate 463/head
Xiaozhu Meng [Wed, 22 Aug 2018 00:59:44 +0000 (19:59 -0500)]
1. The FULL register size must have value 0 due to the way we calculate
base registers.
2. Update liveness for the value changes

2 years agoadd debugging support to LineInformation
John Mellor-Crummey [Tue, 17 Oct 2017 17:22:44 +0000 (12:22 -0500)]
add debugging support to LineInformation

2 years agoadd debugging support to Symtab interface
John Mellor-Crummey [Tue, 17 Oct 2017 17:19:37 +0000 (12:19 -0500)]
add debugging support to Symtab interface

use new IBSTree dumping functionality to dump function and
module ranges.

2 years agoadd debugging support to IBSTree.h
John Mellor-Crummey [Tue, 17 Oct 2017 16:48:10 +0000 (11:48 -0500)]
add debugging support to IBSTree.h

2 years agocorrect dwarf debug printing
John Mellor-Crummey [Wed, 18 Oct 2017 15:48:34 +0000 (10:48 -0500)]
correct dwarf debug printing

in dwarfWalker::setFuncFromLowest, set the current function
before calling dwarf_printf so that curFunc() in the
dwarf_printf sees the function just found

(cherry picked from commit a786739e5369b79ff6823cf742042c9f2d874765)

2 years agoupdate line map reader based on dwarf_next_lines
John Mellor-Crummey [Sat, 30 Jun 2018 17:58:19 +0000 (12:58 -0500)]
update line map reader based on dwarf_next_lines

integrate changes in master's parseLineMapInfoForCU that
avoid missing line map entries into new line map parser
based on elfutils 0.173 that uses dwarf_next_lines for
binaries that lack a .debug_info section

2 years agoremove old line map parsing code
John Mellor-Crummey [Sat, 30 Jun 2018 16:41:53 +0000 (11:41 -0500)]
remove old line map parsing code

2 years agofix line map parsing to avoid omissions
John Mellor-Crummey [Sat, 30 Jun 2018 16:39:42 +0000 (11:39 -0500)]
fix line map parsing to avoid omissions

2 years agouse dwarf_next_lines to read .debug_line without .debug_info
John Mellor-Crummey [Fri, 29 Jun 2018 19:33:08 +0000 (14:33 -0500)]
use dwarf_next_lines to read .debug_line without .debug_info

2 years agohandle empty DebugSectionMap
John Mellor-Crummey [Sat, 2 Jun 2018 18:06:11 +0000 (13:06 -0500)]
handle empty DebugSectionMap

2 years agoavoid infinite loop on bad DWARF CFI record
John Mellor-Crummey [Fri, 1 Jun 2018 23:35:54 +0000 (18:35 -0500)]
avoid infinite loop on bad DWARF CFI record

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Tue, 10 Jul 2018 17:52:12 +0000 (12:52 -0500)]
Merge branch 'master' of https://github.com/dyninst/dyninst

2 years agoChanging URL of Elfutils to always download the lastest released version.
Sasha Nicolas [Tue, 10 Jul 2018 17:46:04 +0000 (12:46 -0500)]
Changing URL of Elfutils to always download the lastest released version.

2 years agoMerge pull request #469 from rafzi/upstream
Sasha NĂ­colas [Fri, 29 Jun 2018 23:41:55 +0000 (18:41 -0500)]
Merge pull request #469 from rafzi/upstream

symtab: fix memory error in Statement::getFile

2 years agosymtab: fix memory error in Statement::getFile 469/head
Rafael Stahl [Tue, 19 Jun 2018 15:24:19 +0000 (17:24 +0200)]
symtab: fix memory error in Statement::getFile

2 years agoFix register sizes in InstructionAPI
Xiaozhu Meng [Wed, 6 Jun 2018 20:37:40 +0000 (15:37 -0500)]
Fix register sizes in InstructionAPI

2 years agoMerge branch 'github_master' into vector_categories
Xiaozhu Meng [Wed, 6 Jun 2018 19:40:26 +0000 (14:40 -0500)]
Merge branch 'github_master' into vector_categories

2 years agoFix bit-size for YMM and ZMM registers
Xiaozhu Meng [Wed, 6 Jun 2018 19:39:16 +0000 (14:39 -0500)]
Fix bit-size for YMM and ZMM registers

2 years agoFixing parsing of try/catch blocks.
Sasha Nicolas [Wed, 30 May 2018 01:33:15 +0000 (20:33 -0500)]
Fixing parsing of try/catch blocks.
The FDEs were not necessarily following the CIE, as the format says.
https://refspecs.linuxfoundation.org/LSB_3.0.0/LSB-PDA/LSB-PDA/ehframechpt.html
In the ARM binary, because there were FDEs with different CIEs mixed together
we were ignoring FDEs whose CIE had past or whose CIE's reference had changed.

2 years agoFix: parsing .eh_frame on binaries without .debug_frame.
Sasha Nicolas [Thu, 24 May 2018 01:30:27 +0000 (20:30 -0500)]
Fix: parsing .eh_frame on binaries without .debug_frame.

2 years agoFixing the calculation of offset for FDE augmentation data.
Sasha Nicolas [Fri, 13 Oct 2017 21:16:34 +0000 (16:16 -0500)]
Fixing the calculation of offset for FDE augmentation data.

(cherry picked from commit 0780fb7bd7371acea691110826718f810c1f3dd4)

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Wed, 23 May 2018 17:46:04 +0000 (12:46 -0500)]
Merge branch 'master' of https://github.com/dyninst/dyninst

2 years agoMerge pull request #430 from jmellorcrummey/master
Xiaozhu Meng [Tue, 17 Apr 2018 20:05:03 +0000 (15:05 -0500)]
Merge pull request #430 from jmellorcrummey/master

add missing initialization for flags when Elf_X is a memory image

2 years agoMerge pull request #445 from stanfordcox/irelative
Xiaozhu Meng [Tue, 17 Apr 2018 19:34:08 +0000 (14:34 -0500)]
Merge pull request #445 from stanfordcox/irelative

Remove unused rpc/xdr references.

2 years agoCorrecting declaration of variable for the value of DW_AT_comp_dir of Modules.
Sasha Nicolas [Wed, 4 Apr 2018 22:58:11 +0000 (17:58 -0500)]
Correcting declaration of variable for the value of DW_AT_comp_dir of Modules.

2 years agoMerge branch 'sasha/dwarf-absolute-filenames'
Sasha Nicolas [Sat, 31 Mar 2018 00:42:15 +0000 (19:42 -0500)]
Merge branch 'sasha/dwarf-absolute-filenames'

2 years agoAdding getCompDir method to Module.
Sasha Nicolas [Sat, 31 Mar 2018 00:37:56 +0000 (19:37 -0500)]
Adding getCompDir method to Module.
This method returns the DW_AT_comp_dir of Compilation Units.

2 years agoMerge pull request #446 from mxz297/powerpc_and_loop
Xiaozhu Meng [Thu, 29 Mar 2018 21:28:36 +0000 (16:28 -0500)]
Merge pull request #446 from mxz297/powerpc_and_loop

Fixes for testsuite failures on powerv7 and block boundary aligning for overlapping instructions

2 years agoWhen checking whether an address is consistent with instructionsin a 446/head
Xiaozhu Meng [Thu, 29 Mar 2018 20:55:56 +0000 (15:55 -0500)]
When checking whether an address is consistent with instructionsin a
block, first check whether the address is within the block

2 years agoShould continue to check other CIEs when we cannot find FDE in one of the CIE
Xiaozhu Meng [Thu, 29 Mar 2018 15:11:04 +0000 (10:11 -0500)]
Should continue to check other CIEs when we cannot find FDE in one of the CIE

2 years agoppc32 and ppc64 should use the same formatter
Xiaozhu Meng [Wed, 28 Mar 2018 21:36:00 +0000 (16:36 -0500)]
ppc32 and ppc64 should use the same formatter

2 years agoNeed to flush trap mapping table into the mutatee after instrumentation for registeri...
Xiaozhu Meng [Mon, 26 Mar 2018 21:31:36 +0000 (16:31 -0500)]
Need to flush trap mapping table into the mutatee after instrumentation for registering callbacks

2 years agoWhen dealing with overlapping instructions, we should align block as
Xiaozhu Meng [Thu, 22 Mar 2018 17:14:15 +0000 (12:14 -0500)]
When dealing with overlapping instructions, we should align block as
soon as possible, correctly split blocks, anc create new fall-through
edges

2 years agoAdd instruction semantics for extsw on powerpc
Xiaozhu Meng [Mon, 19 Mar 2018 16:56:34 +0000 (11:56 -0500)]
Add instruction semantics for extsw on powerpc

2 years agoRemove unused rpc/xdr references. 445/head
Stan Cox [Wed, 28 Mar 2018 18:06:32 +0000 (14:06 -0400)]
Remove unused rpc/xdr references.

2 years agoMerge remote-tracking branch 'upstream/master' into irelative
Stan Cox [Wed, 28 Mar 2018 18:04:24 +0000 (14:04 -0400)]
Merge remote-tracking branch 'upstream/master' into irelative

2 years agoFixing problem of relative paths from libdw.
Sasha Nicolas [Tue, 27 Mar 2018 21:12:12 +0000 (16:12 -0500)]
Fixing problem of relative paths from libdw.
Now all paths coming from libdw dwarf_filesrc() and dwarf_linesrc() are
being checked and converted to be absolute.

2 years agoPrevious commits broke the build. This is to fix the compiling, but the changes done...
Sasha Nicolas [Wed, 21 Mar 2018 22:34:18 +0000 (17:34 -0500)]
Previous commits broke the build. This is to fix the compiling, but the changes done in the commits should be examined.

2 years agoMerge pull request #441 from thomasdullien/master
Bill Williams [Tue, 20 Mar 2018 19:50:43 +0000 (14:50 -0500)]
Merge pull request #441 from thomasdullien/master

Very minor clean-up a particualrly ugly piece of code.

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Tue, 20 Mar 2018 16:43:32 +0000 (11:43 -0500)]
Merge branch 'master' of https://github.com/dyninst/dyninst

2 years agoFix segfault due to missing arguments in call to parse_printf 441/head
Thomas Dullien [Tue, 20 Mar 2018 15:09:57 +0000 (16:09 +0100)]
Fix segfault due to missing arguments in call to parse_printf

2 years agoMerge remote-tracking branch 'upstream/master'
Thomas Dullien [Tue, 20 Mar 2018 09:28:07 +0000 (10:28 +0100)]
Merge remote-tracking branch 'upstream/master'

2 years agoMerge pull request #437 from mxz297/ret_crossarch
Xiaozhu Meng [Mon, 19 Mar 2018 16:12:34 +0000 (11:12 -0500)]
Merge pull request #437 from mxz297/ret_crossarch

Fixes for non-returning functions, endianness for cross architecture parsing, and powerpc instruction decoding. In addition, fix failures in testsuite on x86/64

2 years agoFix DWARF parsing for arraies 437/head
Xiaozhu Meng [Mon, 19 Mar 2018 16:09:01 +0000 (11:09 -0500)]
Fix DWARF parsing for arraies

2 years agoVery minor clean-up a particualrly ugly piece of code.
Thomas Dullien [Mon, 19 Mar 2018 11:37:55 +0000 (12:37 +0100)]
Very minor clean-up a particualrly ugly piece of code.

2 years agoIn loop anaylsis, visit blocks according to the starting addresses to
Xiaozhu Meng [Fri, 16 Mar 2018 14:10:52 +0000 (09:10 -0500)]
In loop anaylsis, visit blocks according to the starting addresses to
ensure deterministic results. And ignore catch edges in loop analysis

2 years agoHandle wait instruction on powerpc and add vrsave SPR
Xiaozhu Meng [Thu, 8 Mar 2018 20:11:24 +0000 (14:11 -0600)]
Handle wait instruction on powerpc and add vrsave SPR

2 years ago~0 --> ~0u to avoid warnings about left shift of signed value 430/head
John Mellor-Crummey [Thu, 8 Mar 2018 19:50:35 +0000 (13:50 -0600)]
~0 --> ~0u to avoid warnings about left shift of signed value

2 years agocorrect misleading indentation to avoid compiler warnings
John Mellor-Crummey [Thu, 8 Mar 2018 19:49:51 +0000 (13:49 -0600)]
correct misleading indentation to avoid compiler warnings

2 years agoFix a few powerpc instruction decoding problems and the endianness issue
Xiaozhu Meng [Thu, 8 Mar 2018 19:15:50 +0000 (13:15 -0600)]
Fix a few powerpc instruction decoding problems and the endianness issue
of code sections that are not named ".text"

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
John Mellor-Crummey [Thu, 8 Mar 2018 17:09:22 +0000 (11:09 -0600)]
Merge branch 'master' of https://github.com/dyninst/dyninst

bringing my jmellorcrummey fork up to date with wisconsin.

2 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Tue, 6 Mar 2018 20:02:50 +0000 (14:02 -0600)]
Merge branch 'master' of https://github.com/dyninst/dyninst

2 years agoDelete deprecated #ifdef in liveness analysis
Xiaozhu Meng [Thu, 1 Mar 2018 19:41:10 +0000 (13:41 -0600)]
Delete deprecated #ifdef in liveness analysis

2 years agoShould ignore setting function return status when the function is known
Xiaozhu Meng [Sun, 18 Feb 2018 16:56:06 +0000 (10:56 -0600)]
Should ignore setting function return status when the function is known
as non-returning.

2 years agoHandle data endianness in parsing try/catch blocks, so it can be
Xiaozhu Meng [Sun, 18 Feb 2018 16:18:40 +0000 (10:18 -0600)]
Handle data endianness in parsing try/catch blocks, so it can be
cross-architecture

2 years agoShould delay parsing tail call edges when the return status of the tail
Xiaozhu Meng [Fri, 16 Feb 2018 16:40:11 +0000 (10:40 -0600)]
Should delay parsing tail call edges when the return status of the tail
callee is still UNSET

2 years agoFor known non-returning functions, we should ignore possible conflicting
Xiaozhu Meng [Fri, 16 Feb 2018 16:22:46 +0000 (10:22 -0600)]
For known non-returning functions, we should ignore possible conflicting
non-returning analysis results and still treat them as non-returning.

2 years agoadd missing initialization for flags when Elf_X is a memory image
John Mellor-Crummey [Sun, 11 Feb 2018 04:39:31 +0000 (22:39 -0600)]
add missing initialization for flags when Elf_X is a memory image

2 years agoMerge pull request #410 from jmellorcrummey/cuda-machine
Bill Williams [Fri, 26 Jan 2018 20:04:10 +0000 (14:04 -0600)]
Merge pull request #410 from jmellorcrummey/cuda-machine

Add basic support for EM_CUDA binary type

2 years agoMerge pull request #427 from nedwill/master
Bill Williams [Mon, 22 Jan 2018 16:55:04 +0000 (10:55 -0600)]
Merge pull request #427 from nedwill/master

Fix sh_info for VERNEED section

2 years agoShould only check for thunk call when it is a call instruction
Xiaozhu Meng [Fri, 12 Jan 2018 21:54:30 +0000 (15:54 -0600)]
Should only check for thunk call when it is a call instruction

2 years agoFixing verdef and vernum section headers info. Alignment and number of items.
Sasha Nicolas [Fri, 12 Jan 2018 18:54:44 +0000 (12:54 -0600)]
Fixing verdef and vernum section headers info. Alignment and number of items.

2 years agoFix sh_info for VERNEED section 427/head
Ned Williamson [Fri, 12 Jan 2018 01:41:20 +0000 (17:41 -0800)]
Fix sh_info for VERNEED section

This field used to contain verneednum, but now is hardcoded to 2.
This changes restores the original correct behavior.

2 years agoParseAPI should treat IFUNC type symbols as code
Xiaozhu Meng [Thu, 11 Jan 2018 22:19:13 +0000 (16:19 -0600)]
ParseAPI should treat IFUNC type symbols as code

2 years agoCompare against the proper operand field (addressing mode, not type).
Bill Williams [Wed, 10 Jan 2018 17:44:40 +0000 (11:44 -0600)]
Compare against the proper operand field (addressing mode, not type).

2 years agoClean unwanted files
Xiaozhu Meng [Fri, 29 Dec 2017 16:33:33 +0000 (10:33 -0600)]
Clean unwanted files

2 years agoAdd unstrip and codeCoverage to the example dir. Will build and install
Xiaozhu Meng [Fri, 29 Dec 2017 16:26:49 +0000 (10:26 -0600)]
Add unstrip and codeCoverage to the example dir. Will build and install
them with Dyninst