20 months agoMerge pull request #528 from dyninst/ppc_pc_fix
Xiaozhu Meng [Tue, 15 Jan 2019 20:29:09 +0000 (14:29 -0600)]
Merge pull request #528 from dyninst/ppc_pc_fix

Ppc pc fix

20 months agoMerge pull request #518 from stanfordcox/scox/includes
Xiaozhu Meng [Tue, 15 Jan 2019 19:13:42 +0000 (13:13 -0600)]
Merge pull request #518 from stanfordcox/scox/includes

Don't use system header <> syntax for dyninst includes

20 months agoRemove asserts that cause test failures 528/head
Xiaozhu Meng [Tue, 15 Jan 2019 16:43:26 +0000 (10:43 -0600)]
Remove asserts that cause test failures

20 months agoFix a non-deterministic hang in test_thread_5
Xiaozhu Meng [Sat, 12 Jan 2019 20:05:12 +0000 (14:05 -0600)]
Fix a non-deterministic hang in test_thread_5

When the mutator stops the mutatee, the mutator will wait for
all the threads in the mutatee to stop by counting the number
of STOP events. If one of the thread exited, there will be no
STOP comeing back.

When a pre-exit event is handled, if the thread has pending stop
to be waited, we should no longer wait for this thread.

20 months agoFix on x86-64 the mov instruction for register of 16-bit size.
Sasha Nicolas [Fri, 4 Jan 2019 00:22:50 +0000 (18:22 -0600)]
Fix on x86-64 the mov instruction for register of 16-bit size.
The opcode 89h is for both 32-bit and 16-bit but to use
the 16-bit version it's necessary to add an operand-size prefix
byte of value 66h.
Test snip_ref_shlib_var now passing on x86-64 linux.

21 months agoDeal with relocation type R_PPC64_IRELATIVE
Xiaozhu Meng [Thu, 20 Dec 2018 21:48:39 +0000 (15:48 -0600)]
Deal with relocation type R_PPC64_IRELATIVE

21 months agoMerge pull request #519 from dyninst/power_abi_v2_fixes
Xiaozhu Meng [Wed, 19 Dec 2018 19:33:34 +0000 (13:33 -0600)]
Merge pull request #519 from dyninst/power_abi_v2_fixes

Power abi v2 fixes

21 months agoFix code gen for PLT call/jump in dynamic instrumentation on Power 519/head
Xiaozhu Meng [Wed, 19 Dec 2018 17:15:28 +0000 (11:15 -0600)]
Fix code gen for PLT call/jump in dynamic instrumentation on Power

21 months agoThe red zone in Power ABI v2 contains 288 bytes for user code and
Xiaozhu Meng [Wed, 19 Dec 2018 15:43:30 +0000 (09:43 -0600)]
The red zone in Power ABI v2 contains 288 bytes for user code and
224 more bytes for system code. To be safe, we move down stack pointer
512 bytes to avoid overwriting any useful data.

21 months agoSeveral bug fixes on binary rewriting on Power
Xiaozhu Meng [Wed, 19 Dec 2018 15:02:26 +0000 (09:02 -0600)]
Several bug fixes on binary rewriting on Power

1. Fix TOC address calculation
2. Fix PLT call/jump
3. Adjust GLINK entry in .dynamic section, which points to the PLT resolver
4. Adjust R_PPC64_RELATIVE relocation entries

21 months agoDon't use system header <> syntax for dyninst includes 518/head
Stan Cox [Mon, 10 Dec 2018 22:48:46 +0000 (17:48 -0500)]
Don't use system header <> syntax for dyninst includes

21 months agoMerge pull request #510 from dyninst/fix/whileExpr
Xiaozhu Meng [Fri, 7 Dec 2018 23:18:19 +0000 (17:18 -0600)]
Merge pull request #510 from dyninst/fix/whileExpr

Fix whileExpr not generating the correct code and causing abort

21 months agoMerge pull request #513 from jmellorcrummey/fix-openmp-link
Xiaozhu Meng [Fri, 7 Dec 2018 16:42:48 +0000 (10:42 -0600)]
Merge pull request #513 from jmellorcrummey/fix-openmp-link

as needed, add -fopenmp flag when linking executables

21 months agoMerge pull request #507 from stanfordcox/scox/examples
Xiaozhu Meng [Fri, 7 Dec 2018 16:38:19 +0000 (10:38 -0600)]
Merge pull request #507 from stanfordcox/scox/examples

Add .dir suffix to examples/{codeCoverage,unstrip}

21 months agoMerge pull request #506 from stanfordcox/scox/doc
Xiaozhu Meng [Fri, 7 Dec 2018 16:32:29 +0000 (10:32 -0600)]
Merge pull request #506 from stanfordcox/scox/doc

Install docs into target doc dirs

21 months agoMerge pull request #509 from dyninst/fix_sign_unsigned
Xiaozhu Meng [Fri, 7 Dec 2018 16:26:00 +0000 (10:26 -0600)]
Merge pull request #509 from dyninst/fix_sign_unsigned

Fixes signed/unsigned operations for comparison, multiplication,

21 months agoThe right shift implementation on power is wrong. Do not use it for division. 509/head
Xiaozhu Meng [Fri, 7 Dec 2018 16:20:27 +0000 (10:20 -0600)]
The right shift implementation on power is wrong. Do not use it for division.

21 months agoFix 64-bit sign/unsigned comparison, multi, and division on ARM
Xiaozhu Meng [Fri, 7 Dec 2018 15:13:45 +0000 (09:13 -0600)]
Fix 64-bit sign/unsigned comparison, multi, and division on ARM

21 months agoas needed, add -fopenmp flag when linking executables 513/head
John Mellor-Crummey [Fri, 7 Dec 2018 04:24:20 +0000 (22:24 -0600)]
as needed, add -fopenmp flag when linking executables

21 months agoFix 64-bit sign/unsigned comparison, multi, and division on power
Xiaozhu Meng [Thu, 6 Dec 2018 20:03:49 +0000 (14:03 -0600)]
Fix 64-bit sign/unsigned comparison, multi, and division on power

21 months agoast: fix whileOp 510/head
LER0ever [Thu, 6 Dec 2018 05:56:49 +0000 (23:56 -0600)]
ast: fix whileOp

the current whileOp code is mostly from ifOp since they share mostly the
same high level logic.
We should update whileOp code whenever we make a future change to ifOp

21 months agocmake: export CompilerCommands for IDE jump-to-def support
LER0ever [Thu, 6 Dec 2018 05:56:22 +0000 (23:56 -0600)]
cmake: export CompilerCommands for IDE jump-to-def support

21 months agoStart to fix signed/unsigned operations for comparison, multiplication,
Xiaozhu Meng [Wed, 5 Dec 2018 22:07:42 +0000 (16:07 -0600)]
Start to fix signed/unsigned operations for comparison, multiplication,
and division.

This commit contains platform independent changes and platform dependent
changes for x86-64

21 months agoEmit 64-bit integer multiplication and division on power
Xiaozhu Meng [Mon, 3 Dec 2018 17:21:10 +0000 (11:21 -0600)]
Emit 64-bit integer multiplication and division on power

21 months agoAdd .dir suffix to examples/{codeCoverage,unstrip} 507/head
Stan Cox [Fri, 30 Nov 2018 17:20:14 +0000 (12:20 -0500)]
Add .dir suffix to examples/{codeCoverage,unstrip}

21 months agoUpdate the stack locations to find for parameters, as there is an ABI change since...
Xiaozhu Meng [Fri, 30 Nov 2018 17:05:19 +0000 (11:05 -0600)]
Update the stack locations to find for parameters, as there is an ABI change since power 8

21 months agoInstall docs into target doc dirs 506/head
Stan Cox [Fri, 30 Nov 2018 03:08:29 +0000 (22:08 -0500)]
Install docs into target doc dirs

21 months agoFix wrong handling for PTRACE_EVENT_EXIT in proccontrol. Currently, each time we...
Xiaozhu Meng [Wed, 28 Nov 2018 21:56:15 +0000 (15:56 -0600)]
Fix wrong handling for PTRACE_EVENT_EXIT in proccontrol. Currently, each time we see PTRACE_EVENT_EXIT, we assume the mutatee exited normally. However, this is a wrong assumption. Based on the man page of PTRACE:

PTRACE_EVENT_EXIT will happen before actual death,  This applies to exits via
exit(2), exit_group(2), and signal deaths

PTRACE_EVENT_EXIT will also be delivered to proccontrol when the mutatee
died of crashes/signals. So, we need to check whether the waitpid status
represents a normal exit or a signal exit

22 months agoUpdate README.md
Xiaozhu Meng [Mon, 19 Nov 2018 17:02:42 +0000 (11:02 -0600)]
Update README.md

22 months agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sasha Nicolas [Fri, 9 Nov 2018 17:41:29 +0000 (11:41 -0600)]
Merge branch 'master' of https://github.com/dyninst/dyninst

22 months agoMerge branch 'master' into ARMv8
Sasha @leela [Fri, 9 Nov 2018 17:01:06 +0000 (11:01 -0600)]
Merge branch 'master' into ARMv8

22 months agoUpdate latex based manuals v10.0.0
Xiaozhu Meng [Fri, 9 Nov 2018 16:48:08 +0000 (10:48 -0600)]
Update latex based manuals

22 months agoMerge branch 'master' into ARMv8
Sasha @leela [Fri, 9 Nov 2018 16:28:31 +0000 (10:28 -0600)]
Merge branch 'master' into ARMv8

22 months agoMore updates to README and docx based manuals
Xiaozhu Meng [Fri, 9 Nov 2018 16:17:46 +0000 (10:17 -0600)]
More updates to README and docx based manuals

22 months agoFix generateLongBranch to make Replace Function work.
Sasha @leela [Fri, 9 Nov 2018 00:50:47 +0000 (18:50 -0600)]
Fix generateLongBranch to make Replace Function work.
test1_22 passes.

22 months agoClear debugging output
Xiaozhu Meng [Thu, 8 Nov 2018 21:57:08 +0000 (15:57 -0600)]
Clear debugging output

22 months agoUpdate README.md
Sasha NĂ­colas [Thu, 8 Nov 2018 21:40:02 +0000 (15:40 -0600)]
Update README.md

22 months agoCorrect LDR/STR instructions for SIMD&FP
Sasha @leela [Thu, 8 Nov 2018 21:22:27 +0000 (15:22 -0600)]
Correct LDR/STR instructions for SIMD&FP
Saving all FP registers in BaseTramp
Remove #if for DYNINST_snippetBreakpoint

22 months agoBump the version number to 10.0.0
Xiaozhu Meng [Thu, 8 Nov 2018 18:27:47 +0000 (12:27 -0600)]
Bump the version number to 10.0.0

22 months agoUpdate Spack information
Xiaozhu Meng [Thu, 8 Nov 2018 17:54:07 +0000 (11:54 -0600)]
Update Spack information

22 months agoUpdate README.md to rewrite install documentation
Xiaozhu Meng [Thu, 8 Nov 2018 16:52:28 +0000 (10:52 -0600)]
Update README.md to rewrite install documentation

22 months agoUpdate cmake setup explanation in README.md
Xiaozhu Meng [Wed, 7 Nov 2018 22:47:15 +0000 (16:47 -0600)]
Update cmake setup explanation in README.md

22 months agoRemove old files and start to update README.md
Xiaozhu Meng [Wed, 7 Nov 2018 21:10:03 +0000 (15:10 -0600)]
Remove old files and start to update README.md

22 months agoImplementing DynFrameHelper::allocatesFrame
Sasha @leela [Wed, 7 Nov 2018 19:18:45 +0000 (13:18 -0600)]
Implementing DynFrameHelper::allocatesFrame
Implementing StackwalkInstrumentationHelper::isInstrumentation
Implementing writeFunctionPtr
Removing #if for DYNINST_instForkEntry
test_thread_*, test_fork_* passing.

22 months agoClean up change log
Xiaozhu Meng [Wed, 7 Nov 2018 17:27:05 +0000 (11:27 -0600)]
Clean up change log

22 months agoUpdate change log since v9.3.2 for v10.0.0
Xiaozhu Meng [Wed, 7 Nov 2018 16:03:19 +0000 (10:03 -0600)]
Update change log since v9.3.2 for v10.0.0

22 months agoAdded/updated support for 271 new power instructions
Benjamin Welton [Tue, 6 Nov 2018 06:07:15 +0000 (22:07 -0800)]
Added/updated support for 271 new power instructions

Added full/partial support for the following instructions:

vsldoi ,maddhd ,maddhdu ,maddld ,vbpermq ,extended ,bcdctsq ,bcdcfsq ,bcdctz ,bcdctn ,bcdcfz ,bcdcfn ,bcdsetsgn ,vclzlsbb ,vctzlsbb ,vnegw ,vnegd ,vprtybw ,vprtybd ,vprtybq ,vextsb2w ,vextsh2w ,vextsb2d ,vextsh2d ,vextsw2d ,vctzb ,vctzh ,vctzw ,vctzd ,dcbst ,wait ,td ,lxsiwax ,stfpdux ,slbiag ,cmpeqb ,cmprb ,cnttzw ,cnttzd ,cp_abort ,darn ,extswsl ,ldat ,lwat ,mcrxrx ,mfvsrld ,modsd ,modud ,modsw ,moduw ,msgsnd ,msgclr ,msgsndp ,msgclrp ,msgsync ,mtvsrdd ,mfvsrwz ,mtvsrd ,mtvsrwa ,mtvsrwz ,mtvsrws ,setb ,slbieg ,slbsync ,stdat ,stwat ,clrbhrb ,mfbhrbe ,icbt ,lqarx ,stqcx ,tbegin ,tend ,tabort ,tabortwc ,tabortwci ,tabortdc ,tabortdci ,tsr ,tcheck ,treclaim ,trechkpt ,addg6s ,cdtbcd ,cbcdtd ,divde ,divdeu ,modsd ,lbarx ,lharx ,ldbrx ,stbcx ,stdbrx ,sthcx ,lbzcix ,lwzcix ,ldcix ,stbcix ,sthcix ,stwcix ,stdcix ,lfdpx ,stfdpx ,prtyd ,prtyw ,slbfee ,slbfee ,slbmfee ,slbmfev ,mfocrf ,isel ,tlbiel ,slbmte ,subfze ,mtmsrd ,mtmsr ,copy ,paste ,extswsli ,stxvb16x ,wait ,lxsiwax ,mfvsrd ,bpermd ,divwe ,divweu ,lfiwzx ,cmpb ,lfiwax ,lhzcix ,slbia ,slbie ,dtstsfi ,dcffix ,fcfids ,fcfidus ,dadd ,dcmpo ,dcmpu ,dctdp ,dctfix ,ddedpd ,ddiv ,denbcd ,diex ,dmul ,dquai ,dqua ,drintn ,drintx ,drrnd ,drsp ,dscli ,dscri ,dsub ,dtstdc ,dtstdg ,dtstex ,dtstsf ,frsqrtes ,dxex ,xxpermdi ,xvtdivsp ,xxsel ,xxsldwi ,xvnmaddasp ,xscmpexpdp ,xscvuxddp ,xxspltib ,xsaddsp ,xsmaddadp ,xsrdpi ,xssubdp ,xsmsubmdp ,xscmpexpdp ,xscmpexpdp ,xvrspip ,xxinsertw ,xvcmpeqdp ,xvrsqrtedp ,xxlor ,xsnmaddadp ,xscvdpuxds ,xvnabssp ,xvnegsp ,xvcvsxddp ,xsnmsubqp ,daddq ,dcffixq ,dcmpoq ,dcmpuq ,dctfixq ,dctqpq ,ddedpdq ,denbcdq ,ddivq ,diexq ,dmulq ,dquaiq ,dquaq ,drdpq ,drintnq ,drintxq ,drrndq ,dscliq ,dscriq ,dsubq ,dtstdcq ,dtstdgq ,dtstexq ,dtstsfq ,dxexq ,fcpsgn ,fre ,frim ,frin ,frip ,friz ,fctidz ,xsxexpdp ,xsxsigdp ,xscvdphp ,xscvhphp ,xvxexpdp ,xvxsigdp ,xxbrh ,xvxexpsp ,xvxsigsp ,xxbrw ,xxbrd ,xvcvhpsp ,xvcvsphp ,xxbrq ,xsxexpdp ,xvxexpdp ,xscvqpsdz ,dtstsfiq ,xscpsgnqp ,xsdivqp ,xsrqpxp ,fmrgew ,fmrgow ,fcfidu, fctidu ,fctiduz ,fctiwu ,fctiwuz ,ftdiv ,ftsqrt ,mffs ,mffsce ,mffscdrn ,mffscdrn ,mffscdrni ,mffscrn ,mffsl ,xsabsqp ,xsxexpqp ,xsnegqp ,xsxsigqp ,xssqrtqp ,xsnabsqp ,xscvqpuwz ,xscvudqp ,xscvqpswz ,xscvsdqp ,xscvqpudz ,xscvqpdp ,xscvdpqp ,xscvqpsdz

Currently missing is operand decoding for the following operand types:

UIM(), BHRBE(), IH(), SP(), S(), TE(), DGM(), DCM(), CT(), RSP(), RTP(), EH(), PRS(), A(), R(), BC(), RC(), RIC(), SIM(), DCMX(), RO(), RMC(), EX(), SHB(), PS(), CY(), DRM(), SHW(), XC(), DM(), IMM8()

If an instruction with one of these operands is encounted, the operand will not be docoded and a warning message printed. Over time support for these operands will be added.

22 months agoMerge branch 'master' into ARMv8
Sasha @leela [Mon, 5 Nov 2018 22:06:44 +0000 (16:06 -0600)]
Merge branch 'master' into ARMv8

22 months agoMerge branch 'ARMv8' of https://github.com/dyninst/dyninst into ARMv8
Sasha @leela [Mon, 5 Nov 2018 21:50:35 +0000 (15:50 -0600)]
Merge branch 'ARMv8' of https://github.com/dyninst/dyninst into ARMv8

22 months agoVarious bug fixes
Xiaozhu Meng [Mon, 5 Nov 2018 20:38:54 +0000 (14:38 -0600)]
Various bug fixes

1. Jump table analysis
   1.1 do not slice backward along indirect edges, which will
   make jump table analysis depends on results of previous jump table analysis,
   and have cascading wrong analysis results.
   1.2 On x86, perform tentative instruction decoding at potential jump targets.
   If we find junk instructions at jump target, then we know the jump target is wrong
   1.3 Remove jump target checks that relies on the parsing function context.
   For jump tables shared by multiple functions, such checks can easily lead to
   non-determinisitic results.

2. Tail calls: on x86, if there is a pop to a callee saved register, it means
   the function is tearing down the stack frame. So, this jump should be a tail call

3. PLT stubs
   3.1 Improve analysis of PLT in .plt.got and fix related instrumentation problems
   3.2 Function should use the PLT name at the beginning of the parsing, not at the
   end of parsing. Otherwise, for PLT that is known to be non-returning, its caller
   may have the wrong retstatus

22 months agofix doNotOverflow for int64, picked from 2b21d59
LER0ever [Sun, 4 Nov 2018 20:49:50 +0000 (14:49 -0600)]
fix doNotOverflow for int64, picked from 2b21d59

22 months agoAdded 80 Power instructions missing from opcode 31
Benjamin Welton [Sat, 3 Nov 2018 05:19:41 +0000 (00:19 -0500)]
Added 80 Power instructions missing from opcode 31

Added the following new instructions to the power opcode tables (however they are not yet enabled):

slbiag, cmpeqb, cmprb, cnttz, cnttz, cp_abort, darn, extswsl, ldat, lwat, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, msgclr, msgclrp, msgsnd, msgsndp, mtvsrdd, mtvsrws, mtvsrd, mtvsrwa, mtvsrwz, mfvsrd, mfvsrwz, setb, slbieg, slbsync, stdat, stwat, clrbhrb, mfbhrbe, icbt, lqarx, stqcx, tabort, tabortdc, tabortdci, tabortwc, tabortwci, tbegin, tcheck, trechkpt, treclaim, tsr, addg6s, cbcdtd, cdtbcd, divde, divwe, lbarx, ldbrx, lharx, stbcx, stdbrx, sthcx, lbzcix, ldcix, lhzcix, lwzcix, stbcix, stdcix, sthcix, stwcix, lfdpx, stfdpx, prtyd, prtyw, slbfee, slbmfee, slbmfev, isel, tlbiel, subfz, slbmte, mtmsr, mtmsrd

22 months agoMinor fix to decoding extended opcode 30 on PPC
Benjamin Welton [Fri, 2 Nov 2018 20:45:29 +0000 (13:45 -0700)]
Minor fix to decoding extended opcode 30 on PPC

On PPC, the extended opcode of table 30 is decoded based on the following criterion:

If bit 27 = 1. Extended opcode is at range 27-30. Otherwise the extended opcode range is 27-29.

22 months agoMerge branch 'ARMv8' of https://code.rongyi.io/LER0ever/Dyninst into ARMv8
LER0ever [Tue, 30 Oct 2018 21:52:40 +0000 (16:52 -0500)]
Merge branch 'ARMv8' of https://code.rongyi.io/LER0ever/Dyninst into ARMv8

Conflict: binutils 2.31.1 instead

22 months agoaarch64: use sys/uio instead of bits/uio
LER0ever [Wed, 24 Oct 2018 22:46:39 +0000 (22:46 +0000)]
aarch64: use sys/uio instead of bits/uio
we should never include bits/uio directly, as stated in the bits/uio.h file:

18 #if !defined _SYS_UIO_H && !defined _FCNTL_H
19 # error "Never include <bits/uio.h> directly; use <sys/uio.h> instead."
20 #endif

22 months agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

22 months agoMerge branch 'master' into ARMv8
Sasha @leela [Tue, 30 Oct 2018 20:12:17 +0000 (15:12 -0500)]
Merge branch 'master' into ARMv8

22 months agoUpdate binutils version to download.
Sasha @leela [Tue, 30 Oct 2018 19:30:32 +0000 (14:30 -0500)]
Update binutils version to download.

22 months agoImplement doNotOverflow for ARMv8.
Sasha @leela [Tue, 30 Oct 2018 18:13:55 +0000 (13:13 -0500)]
Implement doNotOverflow for ARMv8.
Implement load relative.
Fix emit immediate for plus and minus.

22 months agoFix interface changes for ARM.
Sasha @leela [Tue, 30 Oct 2018 17:50:28 +0000 (12:50 -0500)]
Fix interface changes for ARM.

23 months ago1. Fix x86-64 codegen for binary operators with 64-bit imm values
Xiaozhu Meng [Fri, 26 Oct 2018 17:06:36 +0000 (12:06 -0500)]
1. Fix x86-64 codegen for binary operators with 64-bit imm values

2. When decoding floating point instructions on x86-64, the address size
override prefix means 64-bit address size rather than 16-bit

3. Fix a linking problem of examples

4. Do not use negative values when reading jump tables

23 months agoAdding USE_OpenMP to cmake files;
Sasha Nicolas [Thu, 25 Oct 2018 21:42:30 +0000 (16:42 -0500)]
Adding USE_OpenMP to cmake files;
Adding MD5 to verify downloaded file;
Removing compiler restriction.

23 months agoMerge pull request #488 from dyninst/new-parallel-parsing
Xiaozhu Meng [Thu, 25 Oct 2018 20:38:02 +0000 (15:38 -0500)]
Merge pull request #488 from dyninst/new-parallel-parsing

Merge parallel code parsing

23 months agoMerge branch 'master' into new-parallel-parsing 488/head
Xiaozhu Meng [Thu, 25 Oct 2018 20:35:09 +0000 (15:35 -0500)]
Merge branch 'master' into new-parallel-parsing

Rmove setting function ret status during finalizing


23 months ago1. Fix inconsistent block splits
Xiaozhu Meng [Thu, 25 Oct 2018 14:06:21 +0000 (09:06 -0500)]
1. Fix inconsistent block splits

2. Fix non-returning function analysis for PLT stubs, where a PLT stub
   may first be set to RETURN and then set to NORETURN.

3. When parsing call fallthrough edge, the corresponding call edge may
   still point to sink (not handled yet), which causes the code to
   believe it is an indirect call. So, change the code to look up callee
   by using the callee entry address.

23 months agoaarch64: use sys/uio instead of bits/uio
LER0ever [Wed, 24 Oct 2018 22:46:39 +0000 (22:46 +0000)]
aarch64: use sys/uio instead of bits/uio
we should never include bits/uio directly, as stated in the bits/uio.h file:

18 #if !defined _SYS_UIO_H && !defined _FCNTL_H
19 # error "Never include <bits/uio.h> directly; use <sys/uio.h> instead."
20 #endif

23 months agoMerge pull request #496 from LER0ever/code.rongyi.io/LER0ever/Dyninst/build-fixes
Xiaozhu Meng [Wed, 24 Oct 2018 18:55:50 +0000 (13:55 -0500)]
Merge pull request #496 from LER0ever/code.rongyi.io/LER0ever/Dyninst/build-fixes

Build fixes for parallel building and xdr-related issues

23 months agoMerge pull request #498 from dyninst/power_vector
Xiaozhu Meng [Wed, 24 Oct 2018 15:08:11 +0000 (10:08 -0500)]
Merge pull request #498 from dyninst/power_vector

Vector instruction support on Power and recycled opcode

23 months agoFinish most of the Power 8 VSX instruction decoding 498/head
Xiaozhu Meng [Wed, 24 Oct 2018 12:55:26 +0000 (07:55 -0500)]
Finish most of the Power 8 VSX instruction decoding

23 months agoMerge branch 'ARMv8' of ssh://code.rongyi.io:233/LER0ever/Dyninst into ARMv8
LER0ever [Wed, 24 Oct 2018 05:14:26 +0000 (05:14 +0000)]
Merge branch 'ARMv8' of ssh://code.rongyi.io:233/LER0ever/Dyninst into ARMv8

23 months agoaarch64: add branchOp case
LER0ever [Tue, 23 Oct 2018 21:50:40 +0000 (16:50 -0500)]
aarch64: add branchOp case

23 months agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

23 months agoModifying cmake configuration to compile and install TBB.
Sasha Nicolas [Wed, 24 Oct 2018 01:36:57 +0000 (20:36 -0500)]
Modifying cmake configuration to compile and install TBB.

23 months agoaarch64: add branchOp case
LER0ever [Tue, 23 Oct 2018 21:50:40 +0000 (16:50 -0500)]
aarch64: add branchOp case

23 months ago10/23
Yuhan Xie [Tue, 23 Oct 2018 20:23:08 +0000 (15:23 -0500)]
Chapter 6

    keyword CY, 21th bit
    keyword ST, 16th bit
    keyword SIX, 17-20
    keyword DRM, 18-20
    keyword RM, 19-20
    (ST and SIX always show up together)
    keyword PS, 22th bit

Summary of Changable fields:
   4-906 vctuxs,
   4-970 vctsxs,

     4-524 vspltb
     4-525 vextractub
     4-589 vextractuh
     4-653 vextractuw
     4-717 vextractd
     4-781 vinsertb
     4-845 vinserth
     4-909 vinsertw
     4-973 vinsertd

4-588 vsplth 13-15

4-652 vspltw 14-15

Rc bit:
  for opcode 4: always 21th bit

6-bit(26-31) ext opcode for opcode 4:
   32-47, 59-63

23 months agoImplementing indirect load.
Sasha @leela [Tue, 23 Oct 2018 00:01:54 +0000 (19:01 -0500)]
Implementing indirect load.
Now dereferencing, address-of and negative assignment works. test1_25 passes.
Fix multiplication of negative value only for int of 32 bits.

23 months agoMerge branch 'master' into new-parallel-parsing
Xiaozhu Meng [Sun, 21 Oct 2018 22:57:45 +0000 (17:57 -0500)]
Merge branch 'master' into new-parallel-parsing

23 months agoAdding multiple items for Power 8 instruction decoding
Xiaozhu Meng [Fri, 19 Oct 2018 16:21:40 +0000 (11:21 -0500)]
Adding multiple items for Power 8 instruction decoding

1. VSR registers
2. Decoding for several operand fields
3. Decoding for extended op 60

23 months agoRemove an edge check that caused significant slowdown
Xiaozhu Meng [Thu, 18 Oct 2018 21:55:26 +0000 (16:55 -0500)]
Remove an edge check that caused significant slowdown

23 months ago10/18 Opcode from Chapter 6
Yuhan Xie [Thu, 18 Oct 2018 20:43:46 +0000 (15:43 -0500)]
10/18 Opcode from Chapter 6

Summary of Changable fields:
4-524 vspltb
4-525 vextractub
4-589 vextractuh
4-653 vextractuw
4-717 vextractd
4-781 vinsertb
4-845 vinserth
4-909 vinsertw
4-973 vinsertd
4-588 vsplth
4-652 vspltw

  Rc bit:
for opcode 4: always 21th bit

ext opcode for opcode 4:
    26-31: 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 59, 60, 61, 62, 63

  Keyword SIM, 11-15 bits
    Keyword SHB, 22-25 bits
third-level opcode: 4-1538-x

23 months agoStart to integrate new power opcodes
Xiaozhu Meng [Thu, 18 Oct 2018 16:57:24 +0000 (11:57 -0500)]
Start to integrate new power opcodes

23 months agoFixing regression in some tests caused by misplaced directive.
Sasha Nicolas [Thu, 18 Oct 2018 01:21:39 +0000 (20:21 -0500)]
Fixing regression in some tests caused by misplaced directive.

23 months agobuild: add pr 496 patch
LER0ever [Thu, 18 Oct 2018 00:19:14 +0000 (19:19 -0500)]
build: add pr 496 patch

23 months agocmake: fix msvc complaints about target dependency 496/head
LER0ever [Wed, 17 Oct 2018 23:34:20 +0000 (18:34 -0500)]
cmake: fix msvc complaints about target dependency

23 months agocmake: add conditional check for whether we are building boost
LER0ever [Wed, 17 Oct 2018 23:10:40 +0000 (18:10 -0500)]
cmake: add conditional check for whether we are building boost

23 months agocmake: add boost to all dyninst libraries and DyninstRT, fixes parallel building
LER0ever [Wed, 17 Oct 2018 22:54:10 +0000 (17:54 -0500)]
cmake: add boost to all dyninst libraries and DyninstRT, fixes parallel building

23 months agoUpdate ABI.C
melsabagh-kw [Tue, 9 Jan 2018 16:40:49 +0000 (11:40 -0500)]
Update ABI.C

ebx is callee-saved and should not be set in `callWritten_`.
(cherry picked from commit 6537dafa476375bbfbaa3b0149cc4d27b59b80f7)

23 months ago1. Fix typos in the Power instruction decoding table and add
Xiaozhu Meng [Wed, 17 Oct 2018 14:31:10 +0000 (09:31 -0500)]
1. Fix typos in the Power instruction decoding table and add
   instruction semantics for rldicl

2. When pushing new parse work elements into the work queue,
   we cannot get the source address of the edge from Block::last(),
   because we currently do not hold an accessor to the block end
   and the block can be split. So, before adding new work elements,
   first acquire an accessor to the block end

23 months agoA block can be split between it is just recorded in the block end
Xiaozhu Meng [Tue, 16 Oct 2018 20:23:53 +0000 (15:23 -0500)]
A block can be split between it is just recorded in the block end
map and adding out-going edge work elements. This means Block::end()
and Block::last() are not reliable when adding parsing work elements.
Change them to use IA_IAPI::getAddr(), which is a local object.

23 months ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:45:22 +0000 (14:45 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

23 months ago10/16 Revision of instructions in Chapter 7
Yuhan Xie [Tue, 16 Oct 2018 19:44:20 +0000 (14:44 -0500)]
10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.

23 months agoThe power instruction decoding tables are declared as std::map.
Xiaozhu Meng [Tue, 16 Oct 2018 19:22:43 +0000 (14:22 -0500)]
The power instruction decoding tables are declared as std::map.
Currently, we use the [] operator to access entries in the table.
While the tables are mostly read-only, when we encounter instructions
that are not in the table. The [] operator may create new entries
and cause crashes. Therefore, change all accesses from [] operation
to use find() method.

23 months ago1. Use a new tbb::concurrent_hash_map to record block end.
Xiaozhu Meng [Tue, 16 Oct 2018 19:17:30 +0000 (14:17 -0500)]
1. Use a new tbb::concurrent_hash_map to record block end.
   In addition, when adding out-going edges to a block, we
   first query the block end hash map to get the accessor
   to the block. When splitting the block, we also first
   query the block end hash map to get the access to the block.
   tbb::concurrent_hash_map provides implicit read-write lock
   through the accessor. Therefore, we enforce that adding
   out-going edges are not going to be concurrent with block split.

2. Add a bunch of asserts that check edge consistency. This is
   for debug purpose and will be removed later

23 months agoRemoving function defition without declaration.
Sasha @poman [Tue, 16 Oct 2018 17:09:21 +0000 (12:09 -0500)]
Removing function defition without declaration.

23 months agocmake: use latest binutils, restrict libelf to >=0.173
LER0ever [Mon, 15 Oct 2018 02:55:26 +0000 (21:55 -0500)]
cmake: use latest binutils, restrict libelf to >=0.173
older binutils won't recognize Fedora 25 AArch64
older libelf does not have the "dwarf_next_line" function

23 months agoheaders: delete all xdr related code
LER0ever [Mon, 15 Oct 2018 02:54:27 +0000 (21:54 -0500)]
headers: delete all xdr related code

23 months agoNote for implementation added, XX3 formants in opcode 60 revised, new opcodes added
Yuhan Xie [Thu, 11 Oct 2018 23:08:46 +0000 (18:08 -0500)]
Note for implementation added, XX3 formants in opcode 60 revised, new opcodes added

  - opcode with XX3 formats: extended opcode are expanded from 21-28 to 21-29,
with last bit treated as 0 and 1 respectively
  - The instructions with Rc bits, included Rc in the extended opcode,
treated the instructions with Rc=0 and Rc=1 as different opcodes.

-xvtstdcdp (P760): DCMX field is chopped into 3 parts. May be a special case in implementation.
-**new Keyword: UIM:
   field 12-15 immediate field (xxextractuw,xxinsertw (P766))
   field 14-15 immediate field (xxspltw (P774))
  //I think UIM should be modified to a certain expression to show what exact bits are for UIM
-new Keyword: SHW:
   field 22-23 specify a shift amount in words
    -xxpermdi (P773), three arbitrary digits
    -xxsel (P773), XX4 form
    -xxsldwi (P774), three arbitrary digits

23 months agoAttempting to remove sink edges causes weird side effects on memory usages.
Xiaozhu Meng [Thu, 11 Oct 2018 14:16:37 +0000 (09:16 -0500)]
Attempting to remove sink edges causes weird side effects on memory usages.
Remove related code.

23 months agoFix typos in fix-point analysis for jump tables and remove sink edges when finding...
Xiaozhu Meng [Wed, 10 Oct 2018 18:54:05 +0000 (13:54 -0500)]
Fix typos in fix-point analysis for jump tables and remove sink edges when finding new edges

23 months agoA few fixes for non-returning function analysis
Xiaozhu Meng [Wed, 10 Oct 2018 15:27:11 +0000 (10:27 -0500)]
A few fixes for non-returning function analysis

1. We determine cycle by only checking the number delayed frames.
   Change it to check whether the set of delayed frames stays the same.
   This change may not be necessary, but it is safer

2. Enforce the correct order for checking function status when
   dealing with tail calls and shared code. The common code is moved
   to a new function Parser::update_function_ret_status.

   The return status starts with UNSET, and increases to RETURN, and maybe NORETURN
   Once it is RETURN or NORETURN, it will not go back to UNSET.

   Therefore, it is crucial for the following if statements to be the right order:
   First check the smaller values, and then check the larger values.

   Consider that if we reverse the order. So the code looks like
   1) if (other_func->retstatus() == RETURN) {
   2) }  else if (other_func->retstatus() == UNSET) {

   In such code structure, at line 1), the other_func can be in UNSET, so the check fails.
   Concurrently, the other_func can be immediately set to RETURN, making the check at
   line 2) failing. So, the frame.func is neither delayed, nor updates its return status
   to RETURN, which can lead to wrong NORETURN status.