dyninst.git
23 months agoAdding Equal Operation case for emitImm.
Sasha Nicolas (arm1) [Thu, 26 Apr 2018 18:34:34 +0000 (13:34 -0500)]
Adding Equal Operation case for emitImm.
Correcting instruction encoding for ADD and SUB to modify flags register.
Minor fixes.

23 months agoImplementing functions to generate relational instructions,
Sasha Nicolas (arm1) [Tue, 17 Apr 2018 01:18:25 +0000 (20:18 -0500)]
Implementing functions to generate relational instructions,
mainly related to emitRelOp in the arm emitter, conditional branch in instruction class,
and emitV free function.

23 months agoImplementing more instruction generators for div and sub.
Sasha Nicolas (arm1) [Sat, 14 Apr 2018 03:43:26 +0000 (22:43 -0500)]
Implementing more instruction generators for div and sub.
Adding emit-aarch64.C to put aarch64 Emitters implementations.

23 months agoImplementing functions in EmitterAARCH64 class such as emitIf, emitLoadConst,
Sasha Nicolas (arm1) [Wed, 11 Apr 2018 18:19:18 +0000 (13:19 -0500)]
Implementing functions in EmitterAARCH64 class such as emitIf, emitLoadConst,
    emitLoad, emitLoadConst, emitStore, and emitCall.
Making corrections in insnCodeGen::generateLongBranch.
Implementing free functions such as emitVload, emitVstore, and doNotOverflow.

2 years agoCorrect use of abs.
Sasha @leela [Wed, 7 Mar 2018 19:56:03 +0000 (13:56 -0600)]
Correct use of abs.

2 years agoImplementing enconding function for registerSpace.
Sasha @leela [Wed, 7 Mar 2018 18:45:46 +0000 (12:45 -0600)]
Implementing enconding function for registerSpace.
Implementing calcUsedRegisters for parse_func.
Making sure to test for Call Instruction under modifyJump.
Preparing functions emitCall, emitA, and emitIf.
Fixing some compiling warnings.

2 years agoShould only check for thunk call when it is a call instruction
Xiaozhu Meng [Fri, 12 Jan 2018 21:54:30 +0000 (15:54 -0600)]
Should only check for thunk call when it is a call instruction

(cherry picked from commit 0dbfa36c9cc535f4dd25e657f0e1d2b54df29710)

2 years agoUse of page size was hard coded.
Sasha @leela [Fri, 16 Feb 2018 20:33:27 +0000 (14:33 -0600)]
Use of page size was hard coded.
There was a hard coded 4KB page size during the process of finding space for the new loadable sections. Since leela configuration for page size is 64KB, the smaller page size would cause to generate an assignment of virtual address that would lead to juxtaposition of two LOAD segments.

2 years agoFixing thunk call instruction generation. This makes libc work after relocation of...
Sasha @leela [Fri, 12 Jan 2018 03:36:45 +0000 (21:36 -0600)]
Fixing thunk call instruction generation. This makes libc work after relocation of all funtions.

2 years agoCorrectly modifying conditional branches.
Sasha @leela [Thu, 11 Jan 2018 02:53:12 +0000 (20:53 -0600)]
Correctly modifying conditional branches.
TBZ AND TBNZ instructions were not being properly generated after relocation.

2 years agoAdding code for function "_fini" for arch_aarch64.
Sasha @leela [Fri, 5 Jan 2018 05:01:03 +0000 (23:01 -0600)]
Adding code for function "_fini" for arch_aarch64.
This was already done for x86, x86_64 and power.

2 years ago.gnu.version_d section info and data fixed.
Sasha @leela [Thu, 4 Jan 2018 03:27:49 +0000 (21:27 -0600)]
.gnu.version_d section info and data fixed.

2 years agoMaking .gnu.version_d be renamed .onu.version_d
Sasha @leela [Thu, 28 Dec 2017 01:59:46 +0000 (19:59 -0600)]
Making .gnu.version_d be renamed .onu.version_d

2 years agoChange instruction when offset is greater than 1 MB.
Sasha @leela [Thu, 28 Dec 2017 01:57:17 +0000 (19:57 -0600)]
Change instruction when offset is greater than 1 MB.

2 years agoSorting symbols by address
Sasha @leela [Mon, 20 Nov 2017 17:34:15 +0000 (11:34 -0600)]
Sorting symbols by address

2 years ago1. Fix codegen for ADR instructions
Xiaozhu Meng [Fri, 3 Nov 2017 03:21:05 +0000 (22:21 -0500)]
1. Fix codegen for ADR instructions
2. On ARM, PC relative calculation should use pre-instruction PC values

2 years agoUpdate instruction semantics for adr and adrp. An earlier commit change these two...
Xiaozhu Meng [Tue, 31 Oct 2017 20:48:57 +0000 (15:48 -0500)]
Update instruction semantics for adr and adrp. An earlier commit change these two instructions to have only two operands rather than three operands.

2 years agoMerge branch 'master' into arm64/feature/relocation
Sasha @leela [Mon, 30 Oct 2017 23:46:54 +0000 (18:46 -0500)]
Merge branch 'master' into arm64/feature/relocation

2 years agoFixing some relocation issues: object-elf relocation type of sections and AARCH64...
Sasha @leela [Mon, 30 Oct 2017 21:48:50 +0000 (16:48 -0500)]
Fixing some relocation issues: object-elf relocation type of sections and AARCH64 relocation entry category.

2 years ago1. Should return from detaching the mutatee, when the mutatee cannot be stopped. 408/head
Xiaozhu Meng [Thu, 12 Oct 2017 20:05:44 +0000 (15:05 -0500)]
1. Should return from  detaching the mutatee, when the mutatee cannot be stopped.
2. Pick Bill's strrchr usage fix

2 years agoTake the fix for the memory issue in dwarf parsing from the new-parallel-parsing...
Xiaozhu Meng [Thu, 12 Oct 2017 19:52:03 +0000 (14:52 -0500)]
Take the fix for the memory issue in dwarf parsing from the new-parallel-parsing branch

2 years agoMerge pull request #403 from dyninst/sasha/fix-dwarf-symbol-frame
Sasha Nícolas [Fri, 8 Sep 2017 20:24:55 +0000 (15:24 -0500)]
Merge pull request #403 from dyninst/sasha/fix-dwarf-symbol-frame

fix dwarf symbol frame

2 years agotemporary patch to dwarfWalker 403/head
John Mellor-Crummey [Wed, 6 Sep 2017 01:21:23 +0000 (20:21 -0500)]
temporary patch to dwarfWalker
returning false for getFrameBase prevented processing
of multiple levels of inlined functions in CUBINs

(cherry picked from commit e91fb8670dc5884db902a678a00f48466b126ced)

2 years agoimprove fix to dwarf line reading.
John Mellor-Crummey [Fri, 1 Sep 2017 22:41:01 +0000 (17:41 -0500)]
improve fix to dwarf line reading.

(cherry picked from commit f5f04afc71e8318f9295b209e8ee60600d156ae6)

2 years agodon't skip the first line in all but first range.
John Mellor-Crummey [Fri, 1 Sep 2017 16:26:10 +0000 (11:26 -0500)]
don't skip the first line in all but first range.

(cherry picked from commit 5b8cf9fd1aaf877feeed2971fc9d2f952d06fa7e)

2 years agoUpdated comment for modifyJcc
Sunny Shah [Tue, 9 May 2017 17:20:34 +0000 (12:20 -0500)]
Updated comment for modifyJcc

2 years agoCall the right region_* methods for ARM.
Sunny Shah [Wed, 26 Apr 2017 16:59:07 +0000 (11:59 -0500)]
Call the right region_* methods for ARM.

2 years agoSet register space in RelDataPatch
Sunny Shah [Mon, 24 Apr 2017 22:12:49 +0000 (17:12 -0500)]
Set register space in RelDataPatch

The register space for the codeGen object used in RelDataPatch needs to be set before it is passed to insnCodeGen, since the latter uses it when getting a scratch register.

If the codeGen point in RelDataPatch is null, a new point needs to be generated referencing the previous instruction. This requires pointers to the function and block instances. To store these pointe
ers from RelDataWidget, two new fields (and their setters) are added to RelDataPatch.

2 years agoImplemented IP patch application for ARM.
Sunny Shah [Wed, 19 Apr 2017 21:58:28 +0000 (16:58 -0500)]
Implemented IP patch application for ARM.

Updated IPPatch::apply for ARM. Most of the complexity required on Power is avoided here since we have an instruction available (ADR) to get the current PC.
Also updated moveValueToReg in insnCodeGen to accept a vector of registers to be excluded when getting a scratch register.

2 years agoFixed ABI array intialization for ARM
Sunny Shah [Mon, 17 Apr 2017 23:12:26 +0000 (18:12 -0500)]
Fixed ABI array intialization for ARM

2 years agoImplemented ABI initialization for ARM
Sunny Shah [Mon, 17 Apr 2017 22:39:42 +0000 (17:39 -0500)]
Implemented ABI initialization for ARM

intialize32 for ARM returns directly without doing anything. intialize64
contains the actual logic.

2 years agoFixes for runtime errors
Sunny Shah [Thu, 13 Apr 2017 17:31:42 +0000 (12:31 -0500)]
Fixes for runtime errors

Inlcudes fixes for two seg faults observed while testing relocation:
* createRegisterSpace needs to be called in initialize64.
* modifyData should also handle the literal variant of LDR in the SIMd set.

2 years agoFixed conditional branch instruction generation for short displacements
Sunny Shah [Mon, 10 Apr 2017 21:05:26 +0000 (16:05 -0500)]
Fixed conditional branch instruction generation for short displacements

For displacements that are in range in the modifyJCC function, only bits
5-23  of the instruction need to be modified to set the new
displacement. That way, all conditional instructions (B.cond, CBZ, CBNZ,
TBZ, TBNZ) are taken into account.

2 years agoFixed offset calculation in modifyData for the ADRP instruction.
Sunny Shah [Mon, 10 Apr 2017 20:46:59 +0000 (15:46 -0500)]
Fixed offset calculation in modifyData for the ADRP instruction.

2 years agoFixed modifyData logic for offset values beyond +/- 1 MB.
Sunny Shah [Fri, 7 Apr 2017 19:44:43 +0000 (14:44 -0500)]
Fixed modifyData logic for offset values beyond +/- 1 MB.

When the offset is <-1MB/>+1MB, the appropriate sequence of instructions
needs to be generated to keep the PC-relative data access intact. The
previous logic was using the incorrect values for loading into the
temporary registers before using those registers as indirect pointers
(in the LDR/LDRSW case). This is now fixed.

2 years agoDifferentiate modifyData() processing for ADR/ADRP variants and LDR/LDRSW variants.
Sunny Shah [Fri, 7 Apr 2017 18:40:56 +0000 (13:40 -0500)]
Differentiate modifyData() processing for ADR/ADRP variants and LDR/LDRSW variants.

2 years agoAdded implementation for modifyData() in codegen.
Sunny Shah [Tue, 4 Apr 2017 17:36:58 +0000 (12:36 -0500)]
Added implementation for modifyData() in codegen.

modifyData for ARM deals with ADR/ADRP instructions which need to be
patched to a modified ADR/ADRP or to a bunch of move instructions.

2 years agoImplemented or and and operations in emitImm for ARM64.
Sunny Shah [Mon, 3 Apr 2017 20:23:37 +0000 (15:23 -0500)]
Implemented or and and operations in emitImm for ARM64.

This commit implements the orOp and andOp cases for emitImm. Also
introduced a new function in codegen - generateBitwiseOpShifted - for
generating code for the shifted variants of the bitwise instructions AND, ORR and EOR.

2 years agoImplemented plus, minus and times operation in emitImm for ARM64.
Sunny Shah [Mon, 3 Apr 2017 20:01:35 +0000 (15:01 -0500)]
Implemented plus, minus and times operation in emitImm for ARM64.

The plusOp, minusOp and timesOp cases for emitImm are implemented with
this commit. This also introduces three new methods in the codegen file:
* generateAddSubShifted - ADD/SUB (shifted variant)
* generateAddSubImmediate - ADD/SUB (immediate variant)
* generateMul - MUL

2 years agoCodegen functions for ADD variants
Sunny Shah [Fri, 31 Mar 2017 21:23:20 +0000 (16:23 -0500)]
Codegen functions for ADD variants

Added two new codegen functions for the ADD (immediate) and ADD (shifted
register) variants of the ADD instruction for ARM64.

2 years agoImplemented clobberAllFuncCall for ARM64.
Sunny Shah [Fri, 31 Mar 2017 15:36:25 +0000 (10:36 -0500)]
Implemented clobberAllFuncCall for ARM64.

The implementation follows the general pattern for other architectures: mark only definitely used registers as used if leaf function, else mark all as used.

2 years agoUse abs() instead of ABS macro
Itaru Kitayama [Fri, 31 Mar 2017 14:43:45 +0000 (09:43 -0500)]
Use abs() instead of ABS macro

2 years agoAdded line to relocation log to indicate a failed application of rel
Sunny Shah [Fri, 31 Mar 2017 13:55:05 +0000 (08:55 -0500)]
Added line to relocation log to indicate a failed application of rel
data patch.

2 years agoIn ARMv8.2 or later extensions, address space can be configured
Itaru Kitayama [Thu, 23 Mar 2017 22:54:43 +0000 (17:54 -0500)]
In ARMv8.2 or later extensions, address space can be configured
up to 52 bits. Add new defines, MAX_IMM52 and MIN_IMM52.

2 years agoFix run-time error
Itaru Kitayama [Mon, 20 Mar 2017 12:26:43 +0000 (07:26 -0500)]
Fix run-time error

2 years agoRemove !arch_aarch64 guard in init function
Itaru Kitayama [Fri, 17 Mar 2017 23:02:17 +0000 (18:02 -0500)]
Remove !arch_aarch64 guard in init function

2 years agoInit bit array before it gets used
Itaru Kitayama [Wed, 15 Mar 2017 00:56:39 +0000 (19:56 -0500)]
Init bit array before it gets used

2 years agoImplemented restoreRegister() and restoreFPRegister() in
Sunny Shah [Tue, 14 Mar 2017 19:18:44 +0000 (14:18 -0500)]
Implemented restoreRegister() and restoreFPRegister() in
EmitterAARCH64SaveRegs.

2 years agoMore build fixes.
Sunny Shah [Tue, 14 Mar 2017 18:04:53 +0000 (13:04 -0500)]
More build fixes.

This commit fixes all pending, miscellaneous build errors on ARM.

2 years agoFixed build errors.
Sunny Shah [Tue, 14 Mar 2017 16:59:38 +0000 (11:59 -0500)]
Fixed build errors.

2 years agoAdd a macro MSROp
Itaru Kitayama [Tue, 14 Mar 2017 10:43:17 +0000 (05:43 -0500)]
Add a macro MSROp

2 years agoAdded implementation for saveRegister() ans saveFPRegister() in
Sunny Shah [Mon, 13 Mar 2017 23:22:29 +0000 (18:22 -0500)]
Added implementation for saveRegister() ans saveFPRegister() in
EmitterAARCH64SaveRegs.

This commit also adds a new method in codegen for ARM64 -
generateMemAccessFP() to store/load FP registers.

2 years agoImplemented saveGPRegister(), saveFPRegisters() and saveFPRegisters() in
Sunny Shah [Mon, 13 Mar 2017 23:03:28 +0000 (18:03 -0500)]
Implemented saveGPRegister(), saveFPRegisters() and saveFPRegisters() in
EmitterAARCH64SaveRegs.

2 years agoImplemented stack frame creation and tear down functions.
Sunny Shah [Thu, 9 Mar 2017 00:34:19 +0000 (18:34 -0600)]
Implemented stack frame creation and tear down functions.

This commit implements EmitterAARCH64SaveRegs::createFrame and
EmitterAARCH64RestoreRegs::tearFrame, mimicking the stack frame creation
and tear down functionality followed by ARM64 binaries. The check for
the link register in saveSPR/restoreSPR is also removed since the link
register will no longer be handled as a SPR.

2 years agoAdded method to generate an instruction to move a register to/from the
Sunny Shah [Thu, 9 Mar 2017 00:00:19 +0000 (18:00 -0600)]
Added method to generate an instruction to move a register to/from the
stack pointer.

This method uses the MOV(to/from SP) variant of the move instruction.

2 years agoImplemented baseTramp::generateSaves and baseTramp::generateRestores().
Sunny Shah [Wed, 8 Mar 2017 18:32:46 +0000 (12:32 -0600)]
Implemented baseTramp::generateSaves and baseTramp::generateRestores().

The logic for these methods is derived from our current logic on both
x86 and Power. Both of the above call the appropriate methods in
EmitterAARCH64SaveRegs/EmitterAARCH64RestoreRegs.

2 years agoUse enums added in codegen to specify type of memory operation
Sunny Shah [Mon, 6 Mar 2017 23:07:08 +0000 (17:07 -0600)]
Use enums added in codegen to specify type of memory operation
(load/store).

2 years agoPerform only post-indexed memory operations in
Sunny Shah [Fri, 3 Mar 2017 21:49:47 +0000 (15:49 -0600)]
Perform only post-indexed memory operations in
insnCodeGen::generateMemAccess32or64.

2 years agoMoved all register saving/restoring functions to one of two new classes
Sunny Shah [Wed, 1 Mar 2017 22:46:52 +0000 (16:46 -0600)]
Moved all register saving/restoring functions to one of two new classes
and removed the definitions from the inst-aarch64 header.

This commit moves all functions that handle register saving/restoring
for the base tramp to one of two new classes: EmitterAARCH64SaveRegs and
EmitterAARCH64RestoreRegs. The class definitions go in the emit-aarch64
file with their implementation in the inst-aarch64 file.

baseTramp::generateSaves/generateRestores will have an instance of one
of these classes as appropriate and call only the public methods of the
class. None of the methods for saving/restoring individual regs are now
public: the only public methods are those that save/restore ALL
GPRs/FPRs/SPRs.

2 years agoRemoved unneeded/redundant code for saving/restoring registers.
Sunny Shah [Wed, 1 Mar 2017 18:10:03 +0000 (12:10 -0600)]
Removed unneeded/redundant code for saving/restoring registers.

2 years agoImplemented saveSPR() ans restoreSPR() for ARM and updated
Sunny Shah [Wed, 1 Mar 2017 17:54:34 +0000 (11:54 -0600)]
Implemented saveSPR() ans restoreSPR() for ARM and updated
special-purpose register stack-offset macros.

2 years agoAdd check for opcode of LDR-immediate (unsigned offset) variant in
Sunny Shah [Wed, 1 Mar 2017 17:52:31 +0000 (11:52 -0600)]
Add check for opcode of LDR-immediate (unsigned offset) variant in
insnCodeGen::generateMemAccess32or64().

2 years agoThe last commit, for whatever reason, did not add one header even though
Sunny Shah [Fri, 24 Feb 2017 23:20:07 +0000 (17:20 -0600)]
The last commit, for whatever reason, did not add one header even though
it was given as an argument to git add. Adding it now.

2 years agoImplemented 32/64 bit memory access (store) instruction generation.
Sunny Shah [Fri, 24 Feb 2017 23:16:00 +0000 (17:16 -0600)]
Implemented 32/64 bit memory access (store) instruction generation.

insnCodeGen::generateMemAccess32or64() for ARM generates a STR
instruction for storing/loading a single 32- or 64-bit value.

This function will also eventually generate the equivalent load (LDR)
    instruction.

2 years agoFix build warning
Itaru Kitayama [Fri, 24 Feb 2017 00:18:57 +0000 (18:18 -0600)]
Fix build warning

2 years agoUpdate instrumentation/emitter macro definitions for ARM.
Sunny Shah [Thu, 23 Feb 2017 22:51:47 +0000 (16:51 -0600)]
Update instrumentation/emitter macro definitions for ARM.

2 years agoImplemented initialization of register space for ARM64.
Sunny Shah [Wed, 22 Feb 2017 21:50:17 +0000 (15:50 -0600)]
Implemented initialization of register space for ARM64.

Initializes the GPRs, SPRs and FPRs, marking the appropriate ones as
off-limits.

2 years agoImplemented generation of long branches for ARM64.
Sunny Shah [Tue, 21 Feb 2017 18:13:03 +0000 (12:13 -0600)]
Implemented generation of long branches for ARM64.

Long branch generation relies on loading an immediate into a 64-bit
register. This loading is peformed by a newly added function
insnCodeGen::generateMove() which generates one of the 3 move
instructions - MOVZ, MOVK and MOVN - based on the input arguments.

This commit also provides an implementation of the getEmitter() function
for ARM64, although the implementation of emitter methods for both the stat
and dyn versions of the emitter remains pending.

2 years agoAdding back functions removed in last commit
Sunny Shah [Fri, 17 Feb 2017 19:59:54 +0000 (13:59 -0600)]
Adding back functions removed in last commit

The removal of the functions in the last commit caused several build
failures that will need the functions to be present. Keeping them in the
file while I resolve any dependencies and implement the required ones as
necessary.

2 years agoCompleted implementation of modify*() functions for ARM codegen and
Sunny Shah [Fri, 17 Feb 2017 18:45:53 +0000 (12:45 -0600)]
Completed implementation of modify*() functions for ARM codegen and
removed functions not currently required for the platform.

2 years agoCodegen function changes to support the ARM CF Widget. These changes
Sunny Shah [Wed, 8 Feb 2017 23:17:17 +0000 (17:17 -0600)]
Codegen function changes to support the ARM CF Widget. These changes
involve the insnCodeGen::modify* calls.

Also added FIXME notes to the PPC CF widget for potential code areas
that may be deprecated and thus could be considered for update/removal.

2 years agoRemoved definitions and declarations of
Sunny Shah [Tue, 7 Feb 2017 20:19:43 +0000 (14:19 -0600)]
Removed definitions and declarations of
insnCodeGen::generateInterFunctionBranch for all architectures.

Reason: dead code.

2 years agoImplemented generateBranch, generateCall and generateBranchViaTrap.
Sunny Shah [Mon, 6 Feb 2017 23:00:02 +0000 (17:00 -0600)]
Implemented generateBranch, generateCall and generateBranchViaTrap.
Also added stub for generateAddReg.

2 years agoAdd basic relocation functionality
Sunny Shah [Fri, 3 Feb 2017 22:22:25 +0000 (16:22 -0600)]
Add basic relocation functionality

The control flow widget for ARM64 contains a generic implementation to support
relocation: the implementation mostly mimics that for Power, differing
at the places where the "call" bit for a branch instruction needs to be
set/unset. The createStackwalkerSteppers() implementation in the stackwalking code
also mimics than on Power.

This commit does not touch all changes required to support relocation
but only a subset.

2 years agoMerge pull request #401 from mxz297/jumptable_merge
Xiaozhu Meng [Tue, 29 Aug 2017 22:18:37 +0000 (15:18 -0700)]
Merge pull request #401 from mxz297/jumptable_merge

Merging my jump table improvements, att_syntax, arm semantics, v9.3.x, and libdw

2 years agoOnly do endianess translation for powerpc binaries 401/head
Xiaozhu Meng [Tue, 29 Aug 2017 22:13:51 +0000 (17:13 -0500)]
Only do endianess translation for powerpc binaries

2 years agoDisplacements should be signed integers
Xiaozhu Meng [Tue, 29 Aug 2017 20:41:36 +0000 (15:41 -0500)]
Displacements should be signed integers

2 years agoWe should only set proccontrol level process's data to NULL when the Dyninst level...
Xiaozhu Meng [Tue, 29 Aug 2017 17:18:26 +0000 (12:18 -0500)]
We should only set proccontrol level process's data to NULL when the Dyninst level process is the only owner of the proccontrol level process

2 years agoFix uninitialized return value in line info
Xiaozhu Meng [Tue, 29 Aug 2017 14:22:58 +0000 (09:22 -0500)]
Fix uninitialized return value in line info

2 years agoFix symplifying concat operations in jump table analysis
Xiaozhu Meng [Thu, 24 Aug 2017 20:39:09 +0000 (15:39 -0500)]
Fix symplifying concat operations in jump table analysis

2 years agoMerge branch 'libdw' into jumptable_rebase
Xiaozhu Meng [Thu, 24 Aug 2017 17:12:23 +0000 (12:12 -0500)]
Merge branch 'libdw' into jumptable_rebase

2 years ago1. When we find potential indexing variable with table stride being 1, we need to...
Xiaozhu Meng [Wed, 23 Aug 2017 19:21:36 +0000 (14:21 -0500)]
1. When we find potential indexing variable with table stride being 1, we need to make sure that we have already found the table base to declare this variable as the table index.
2. Add constants multiplication in AST simplification

2 years agoFixing small things after the merge.
Sasha Nicolas [Wed, 23 Aug 2017 19:54:43 +0000 (14:54 -0500)]
Fixing small things after the merge.

2 years agoMerge branch 'sasha/libdw_deploy' into v9.3.x
Sasha Nicolas [Wed, 23 Aug 2017 17:41:34 +0000 (12:41 -0500)]
Merge branch 'sasha/libdw_deploy' into v9.3.x

2 years agoMerge branch 'github_master' into jumptable_rebase
Xiaozhu Meng [Tue, 22 Aug 2017 14:59:06 +0000 (09:59 -0500)]
Merge branch 'github_master' into jumptable_rebase

2 years ago1. Fix ARM semantics for instructions that use conditional code
Xiaozhu Meng [Tue, 22 Aug 2017 14:44:46 +0000 (09:44 -0500)]
1. Fix ARM semantics for instructions that use conditional code
2. Make sure to keep multiplication by one and shifting left by zero through visitors and expansion cache

2 years agoAdded high-level of diagram of ROSE semantics
Sunny Shah [Fri, 12 May 2017 19:22:47 +0000 (14:22 -0500)]
Added high-level of diagram of ROSE semantics

2 years agoAdded pseudocode extractor extract and instruction pseudocode files
Sunny Shah [Thu, 11 May 2017 15:49:37 +0000 (10:49 -0500)]
Added pseudocode extractor extract and instruction pseudocode files

ISA_ps contains one file for each instruction in the XML specification,
with each file containing the pseudocode for that instruction
extracted from the specification by the script.

2 years agoAdded comments for the declaration of several methods in the DispatcherARM64 class and
Sunny Shah [Tue, 31 Jan 2017 22:58:20 +0000 (16:58 -0600)]
Added comments for the declaration of several methods in the DispatcherARM64 class and
relevant comments in their implementation.

2 years agoSemantics for UDIV and SDIV
Sunny Shah [Tue, 31 Jan 2017 18:42:28 +0000 (12:42 -0600)]
Semantics for UDIV and SDIV

2 years agoSemantics for load/store acquire/release instructions (non-SIMD)
Sunny Shah [Tue, 17 Jan 2017 18:47:44 +0000 (12:47 -0600)]
Semantics for load/store acquire/release instructions (non-SIMD)

Includes semantics for the following instructions:
* LDAR
* LDARH
* LDARB
* STLR
* STLRB
* STLRH

2 years agoSemantics for data processing (3-source) instructions and their aliases (non-SIMD)
Sunny Shah [Tue, 17 Jan 2017 18:23:52 +0000 (12:23 -0600)]
Semantics for data processing (3-source) instructions and their aliases (non-SIMD)

Includes semantics for the following instructions:
MADD, MSUB, MNEG, MUL, SMADDL, SMSUBL, SMNEGL, SMULH, SMULL, UMADDL,
UMSEBL, UMNEGL, UMULH, UMULL

2 years agoSemantics for CLS and CLZ
Sunny Shah [Thu, 5 Jan 2017 20:41:15 +0000 (14:41 -0600)]
Semantics for CLS and CLZ

Introduced new enum CountOp that indicates type of count operation for
these instructions, as well as the utility functions -
CountLeadingZeroBits and CountLeadingSignBits - that implement the
counting logic.

2 years agoSemantics for CSEL
Sunny Shah [Thu, 5 Jan 2017 19:17:17 +0000 (13:17 -0600)]
Semantics for CSEL

Also added a method to return the condition code value from the raw
isntruction based on the instruction category.

2 years agoSemantics for more arithmetic instructions
Sunny Shah [Fri, 23 Dec 2016 19:53:26 +0000 (13:53 -0600)]
Semantics for more arithmetic instructions

Includes semantics for the following instructions:
* TST (immediate)
* TST (shifted)
* SBC
* SBCS
* NGC
* NGCS
* NEG
* NEGS
* MVN
* MOV (to/from SP)

2 years agoSemantics for shift instruction.
Sunny Shah [Tue, 20 Dec 2016 19:24:33 +0000 (13:24 -0600)]
Semantics for shift instruction.

Includes semantics for the following instructions:
* LSL (register)
* LSLV
* LSR (register)
* LSRV
* ASR (register)
* ASRV
* ROR (register)
* RORV

Introduced method DispatcherARM64::ShiftReg that is utilized by the
semantics of all the above instructions and calls the appropriate shift
function under BaseSemantics::RiscOperators based on the shift type.

Introduced method DispatcherARM64::getShiftType that is again used by
the semantics code to determine the type of shift.

2 years agoSemantics for load/store-unscaled instructions
Sunny Shah [Mon, 12 Dec 2016 17:15:28 +0000 (11:15 -0600)]
Semantics for load/store-unscaled instructions

Includes semantics for the following instructions:
* LDUR
* LDURB
* LDURH
* LDURSB
* LDURSH
* LDURSW
* STUR
* STURB
* STURH

2 years agoSemantics for load/store (unprivileged instructions)
Sunny Shah [Mon, 12 Dec 2016 17:02:56 +0000 (11:02 -0600)]
Semantics for load/store (unprivileged instructions)

Includes semantics for the following instructions:
* LDTR
* LDTRB
* LDTRH
* LDTRSB
* LDTRSH
* STTR
* STTRB
* STTRH

2 years agoSemantics for load/store pair instructions
Sunny Shah [Mon, 5 Dec 2016 18:48:52 +0000 (12:48 -0600)]
Semantics for load/store pair instructions

Variants of following instructions now supported:
* LDP
* STP
* LDPSW
* LDNP
* STNP

2 years agoWhen symplifying AST in jump table analysis, we need to remove multiplying by one...
Xiaozhu Meng [Mon, 21 Aug 2017 20:14:38 +0000 (15:14 -0500)]
When symplifying AST in jump table analysis, we need to remove multiplying by one and shifting left by zero from the AST when doing jump table indexing slice, to improve aliasing tracking;
on the other hand, we should keep these multilcation by one or shifting left by zero when doing jump table format slice, to identify the index variable for one byte long tables