dyninst.git
4 years agoFixes based on testing SIMD vector x indexed, load/store multiple structures and...
Sunny Shah [Fri, 26 Feb 2016 21:49:32 +0000 (15:49 -0600)]
Fixes based on testing SIMD vector x indexed, load/store multiple structures and load/store multiple structures post-indexed categories.

Most fixes revolve around adding the correct registers (several cases had been left out in the load/store categories) and taking care of the read/write properties of the registers (again, most problems were in the load/store instructions).

4 years agoFixed source register addition for the SIMD table lookup category.
Sunny Shah [Mon, 22 Feb 2016 17:42:31 +0000 (11:42 -0600)]
Fixed source register addition for the SIMD table lookup category.

An extra second source register was getting added for the SIMD table lookup instructions. This has now been fixed.

4 years agoReplaced most asserts with a flag marking the instruction as invalid.
Sunny Shah [Mon, 22 Feb 2016 01:22:54 +0000 (19:22 -0600)]
Replaced most asserts with a flag marking the instruction as invalid.

Except for the cases where the assert didn't depend on the value of a field in the instruction, all of them have been replaced as described above.

4 years agoFixed detection of correct second source register for SIMD scalar X indexed instructi...
Sunny Shah [Fri, 19 Feb 2016 22:46:03 +0000 (16:46 -0600)]
Fixed detection of correct second source register for SIMD scalar X indexed instruction category.

The lower nibble of the opcode needs to be checked, and not the higher nibble.
Also set destination register read for some instructions in the SIMD modified immediate category.

4 years agoAdded support for SIMD scalar 3 same instruction category.
Sunny Shah [Thu, 18 Feb 2016 19:26:39 +0000 (13:26 -0600)]
Added support for SIMD scalar 3 same instruction category.

4 years agoAdded logic to detect invalid instructions in the SIMD scalar shift by immediate...
Sunny Shah [Tue, 16 Feb 2016 22:21:20 +0000 (16:21 -0600)]
Added logic to detect invalid instructions in the SIMD scalar shift by immediate category

4 years agoBug fixes from issues found by Nathan during fuzz testing
Sunny Shah [Tue, 16 Feb 2016 21:37:47 +0000 (15:37 -0600)]
Bug fixes from issues found by Nathan during fuzz testing

* All instructions that point to the INVALID entry of the instruction table have isValid marked as false, to prevent any form of operand post-processing on them. Such post processing was happening before this fix and was an incorrect implementation.
* The code for parsing immediates for scalar shift by immediate SIMD category is same as that for the non-scalar(variant) variant, but wasn;t gettubg executed for the scalar variant. A check has now been added to execute it for the scalar variant as well.

4 years agoBug fixes for SIMD instruction support.
Sunny Shah [Fri, 12 Feb 2016 18:24:44 +0000 (12:24 -0600)]
Bug fixes for SIMD instruction support.

Registers for the scalar pairwise category weren't being set correctly for the Rn field, and not at all for the Rd field. This has now been fixed.

4 years agoARM64 non-register branch and return instructions now have their correct category...
Sunny Shah [Fri, 12 Feb 2016 17:17:25 +0000 (11:17 -0600)]
ARM64 non-register branch and return instructions now have their correct category set.

This is used by ParseAPI to determine the type of an instruction when building basic blocks.

4 years agoBug fixes and optimizations after more testing
Sunny Shah [Thu, 11 Feb 2016 20:15:53 +0000 (14:15 -0600)]
Bug fixes and optimizations after more testing

* Optimized creation of 64-bit immediate from the a,b,c,d,e,f,g and h operands
* Fixes to correctly handle shift amounts for the SIMD modified immediate category

4 years agoFixed bugs found during testing (using the aarch64_simd test).
Sunny Shah [Tue, 9 Feb 2016 22:03:24 +0000 (16:03 -0600)]
Fixed bugs found during testing (using the aarch64_simd test).

* The register alias H_REG is renamed to HQ_REG to improve readability. It also has a size associated with it now (dyn_regs.C).
* Several assignments of isValid were true instead of false, this has been fixed.
* Changed macro definition for non-SIMD load/store instructions to not also include SIMD instructions

4 years agoParseAPI with support for direcct control flow on ARM64.
Sunny Shah [Fri, 5 Feb 2016 23:34:39 +0000 (17:34 -0600)]
ParseAPI with support for direcct control flow on ARM64.

ParseAPI now supports direct control flow on ARM64. I'd made a commit of all the changes earlier, but looks like it didn't go through.
This commit contains all the changes: all functions required to support direct control flow are implemented. IA_aarch64.h is deleted as it no longer required at this stage.

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Tue, 2 Feb 2016 21:34:41 +0000 (15:34 -0600)]
Added support for following SIMD instruction categories:

* Scalar shift by immediate
* Scalar 2 register miscellaneous

Also added utility functions for finding the number of the highest and lowest set bits in a 32-bit integer.

4 years agoAdded support for the following SIMD instruction categories:
Sunny Shah [Thu, 28 Jan 2016 21:08:05 +0000 (15:08 -0600)]
Added support for the following SIMD instruction categories:

* Scalar pairwise
* Scalar 3 different
* Scaalr 3 same
* Scalar X indexed

Also implemented OPRsize function to record the value of the "size" field. Re-used the _szField variable for this.

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Mon, 25 Jan 2016 20:06:12 +0000 (14:06 -0600)]
Added support for following SIMD instruction categories:

* Vector X indexed element
* Scalar copy

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Fri, 22 Jan 2016 21:44:12 +0000 (15:44 -0600)]
Added support for following SIMD instruction categories:

* 3 different
* 3 same
* 2 register miscellaneous

4 years agoAdded support for following SIMD instruction categories:
Sunny Shah [Wed, 20 Jan 2016 22:34:39 +0000 (16:34 -0600)]
Added support for following SIMD instruction categories:

* Permute
* Shift by immediate
* Table lookup

4 years agoAdded support for the following SIMD instruction categories:
Sunny Shah [Tue, 19 Jan 2016 02:32:00 +0000 (20:32 -0600)]
Added support for the following SIMD instruction categories:
* Across lanes
* Copy
* Extract
* Modified Immediate

The first of the above two had been implemented by Steve but several cases had been left out; those have been handled now.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Sun, 3 Jan 2016 21:25:06 +0000 (15:25 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years ago fixed some compiling errors. noted what have been implemented.
SteveXiSong [Sun, 3 Jan 2016 21:18:10 +0000 (15:18 -0600)]
 fixed some compiling errors. noted what have been implemented.

4 years agoadded symbols for more mem access width
SteveXiSong [Fri, 1 Jan 2016 20:31:19 +0000 (14:31 -0600)]
added symbols for more mem access width

4 years agoadd more logic for SIMD instructions
SteveXiSong [Wed, 30 Dec 2015 21:53:48 +0000 (15:53 -0600)]
add more logic for SIMD instructions

4 years agoUpdated test files to have same logic as in ARM's instruction API file.
Sunny Shah [Wed, 16 Dec 2015 21:52:22 +0000 (15:52 -0600)]
Updated test files to have same logic as in ARM's instruction API file.

4 years agoReverting opcode decoding logic to what we used earlier.
Sunny Shah [Tue, 15 Dec 2015 18:47:45 +0000 (12:47 -0600)]
Reverting opcode decoding logic to what we used earlier.

The decoder table no longer has a list of indices into the instruction table (which was done to support strict solution to aliasing) but just one index which corresponds to the most general instruction.
Modifying the opcode decoding logic to conform to this form of aliasing.

4 years agofixed a few bugs after rolling backing to weak solution to aliases
SteveXiSong [Tue, 8 Dec 2015 19:38:11 +0000 (13:38 -0600)]
fixed a few bugs after rolling backing to weak solution to aliases

4 years agoupaded instructionAPI to roll back to weak solution to instruction aliases
SteveXiSong [Tue, 8 Dec 2015 18:40:45 +0000 (12:40 -0600)]
upaded instructionAPI to roll back to weak solution to instruction aliases

4 years agoupdated decoder-aarch64.C & .h to support LDST SIMD single structure instructions.
SteveXiSong [Tue, 8 Dec 2015 05:22:13 +0000 (23:22 -0600)]
updated decoder-aarch64.C & .h to support LDST SIMD single structure instructions.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 8 Dec 2015 02:12:12 +0000 (20:12 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoupdated decoder-aarch64 for LDST SIMD
SteveXiSong [Tue, 8 Dec 2015 02:12:05 +0000 (20:12 -0600)]
updated decoder-aarch64 for LDST SIMD

4 years agoFixed endian-ness of ARM.
Sunny Shah [Mon, 7 Dec 2015 03:00:39 +0000 (21:00 -0600)]
Fixed endian-ness of ARM.

The code was assuming ARM to be big endian while it is not. Modified the decode method to get instructions bytes according to litle-endian order.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 1 Dec 2015 20:22:26 +0000 (14:22 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoupdated makeReg functions to support SIMD
SteveXiSong [Tue, 1 Dec 2015 20:22:14 +0000 (14:22 -0600)]
updated makeReg functions to support SIMD

4 years agoUsage of the struct fields to check the instruction's mask with the mask bits was...
Sunny Shah [Wed, 25 Nov 2015 21:24:35 +0000 (15:24 -0600)]
Usage of the struct fields to check the instruction's mask with the mask bits was incorrect. Fixed to use the correct fields.

4 years agoModified decoder and instruction table walking logic to support last change related...
Sunny Shah [Wed, 25 Nov 2015 20:55:45 +0000 (14:55 -0600)]
Modified decoder and instruction table walking logic to support last change related to aliasing to the tables.

* A list of instruction table indices is stored with each decoder table entry.
* If the above list is of size 1, simply use that index to get the instruction.
* If the list is not of size 1, walk through each instruction table entry and check if the masked value of the current instruction matches the masked value stored in the entry.
* If the mask matches, return that entry as the instruction. Else, move on to the next entry.

4 years agoupdated the script with strict solution to aliasing
SteveXiSong [Tue, 24 Nov 2015 04:41:09 +0000 (22:41 -0600)]
updated the script with strict solution to aliasing

4 years agoupdated the method to handle compiler bug when template functions appears first
SteveXiSong [Fri, 20 Nov 2015 22:40:37 +0000 (16:40 -0600)]
updated the method to handle compiler bug when template functions appears first

4 years agofixed the compiler bug when OPRimm appears at the first place of boost::list_of
SteveXiSong [Fri, 20 Nov 2015 21:37:27 +0000 (15:37 -0600)]
fixed the compiler bug when OPRimm appears at the first place of boost::list_of

4 years agoupdated decoder generator with class structure
SteveXiSong [Thu, 19 Nov 2015 00:08:49 +0000 (18:08 -0600)]
updated decoder generator with class structure

4 years agofixed insn_print merge conflicts
SteveXiSong [Wed, 18 Nov 2015 21:55:24 +0000 (15:55 -0600)]
fixed insn_print merge conflicts

4 years agofixed insn_printf
SteveXiSong [Wed, 18 Nov 2015 02:14:17 +0000 (20:14 -0600)]
fixed insn_printf

4 years agofixed insn_print bugs
SteveXiSong [Tue, 17 Nov 2015 18:55:12 +0000 (12:55 -0600)]
fixed insn_print bugs

4 years agoMerge branch 'v9.1.x' into arm64
SteveXiSong [Mon, 16 Nov 2015 23:06:06 +0000 (17:06 -0600)]
Merge branch 'v9.1.x' into arm64

4 years agoUpdated to 9.1
Bill Williams [Mon, 16 Nov 2015 16:13:54 +0000 (10:13 -0600)]
Updated to 9.1

4 years agoMerge branch 'v9.0.x' into v9.1.x
Bill Williams [Mon, 16 Nov 2015 15:46:52 +0000 (09:46 -0600)]
Merge branch 'v9.0.x' into v9.1.x

4 years agoMerge branch 'arm64' into v9.1.x
Sunny Shah [Sat, 14 Nov 2015 16:04:36 +0000 (10:04 -0600)]
Merge branch 'arm64' into v9.1.x

4 years agoMerge branch 'master' into arm64
SteveXiSong [Sat, 14 Nov 2015 01:22:22 +0000 (19:22 -0600)]
Merge branch 'master' into arm64

4 years agofixed merger conflicts
SteveXiSong [Fri, 13 Nov 2015 23:14:25 +0000 (17:14 -0600)]
fixed merger conflicts

4 years agouncommented reorder cases for ldst and fixed a bug in macro function for ldst_ex_pair...
SteveXiSong [Fri, 13 Nov 2015 23:04:10 +0000 (17:04 -0600)]
uncommented reorder cases for ldst and fixed a bug in macro function for ldst_ex_pair. Ready to be released.

4 years agoStack of IAPI fixes based on fuzz testing.
Bill Williams [Fri, 13 Nov 2015 22:47:26 +0000 (16:47 -0600)]
Stack of IAPI fixes based on fuzz testing.

4 years agoChanged names of right rotate, logical and arithmetic right shift functions displayed...
Sunny Shah [Fri, 13 Nov 2015 22:28:22 +0000 (16:28 -0600)]
Changed names of right rotate, logical and arithmetic right shift functions displayed when pretty printing the instruction

4 years agoModified handling of test-and-branch instructions to support our current operand...
Sunny Shah [Fri, 13 Nov 2015 22:14:52 +0000 (16:14 -0600)]
Modified handling of test-and-branch instructions to support our current operand re-ordering logic. (This will be reverted to the old code once we have ageneric ordering logic)

4 years agoA merge conflict was un-resolved in the previous commit. Resolving the same.
Sunny Shah [Fri, 13 Nov 2015 21:08:17 +0000 (15:08 -0600)]
A merge conflict was un-resolved in the previous commit. Resolving the same.

4 years agoFixed merge conflicts after merging with changes by Steve.wq
Sunny Shah [Fri, 13 Nov 2015 20:20:16 +0000 (14:20 -0600)]
Fixed merge conflicts after merging with changes by Steve.wq

4 years agoAdded logic to re-order the operands after delayed decoding.
Sunny Shah [Fri, 13 Nov 2015 20:13:32 +0000 (14:13 -0600)]
Added logic to re-order the operands after delayed decoding.

This is a temporary solution - will be replaced by a more generic solution in the coming weeks. For now, except for some instructions, the operand list is reversed after all operands are parsed. For the instructions that do not fit into this model, an operand swapping and rotating logic is used (at most there will be 1 swap and 2 rotates) to get the correct order.

4 years agoUpdated instruction table with output from the script with latest changes. This adds...
Sunny Shah [Fri, 13 Nov 2015 20:11:55 +0000 (14:11 -0600)]
Updated instruction table with output from the script with latest changes. This adds the setFlags method for instructions that need to set PSTATE.

4 years agocommented a line of debugging code
SteveXiSong [Fri, 13 Nov 2015 19:50:53 +0000 (13:50 -0600)]
commented a line of debugging code

4 years agoreversed the operand order and handled cases for ldst exceptions
SteveXiSong [Fri, 13 Nov 2015 19:44:28 +0000 (13:44 -0600)]
reversed the operand order and handled cases for ldst exceptions

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
Sunny Shah [Fri, 13 Nov 2015 13:10:52 +0000 (07:10 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoAdded operand re-ordering function skeleton.
Sunny Shah [Fri, 13 Nov 2015 13:09:06 +0000 (07:09 -0600)]
Added operand re-ordering function skeleton.

4 years agofixed some ls/st imm values bugs
SteveXiSong [Fri, 13 Nov 2015 04:49:30 +0000 (22:49 -0600)]
fixed some ls/st imm values bugs

4 years agoupdated the functions to generate setFlags
SteveXiSong [Fri, 13 Nov 2015 03:29:39 +0000 (21:29 -0600)]
updated the functions to generate setFlags

4 years agomodified the aarch64_opc_table and added coresponding function in header file
SteveXiSong [Thu, 12 Nov 2015 20:32:33 +0000 (14:32 -0600)]
modified the aarch64_opc_table and added coresponding function in header file

4 years agoadded setflags field function
SteveXiSong [Thu, 12 Nov 2015 20:24:18 +0000 (14:24 -0600)]
added setflags field function

4 years agoSupport for system registers.
Sunny Shah [Thu, 12 Nov 2015 17:48:23 +0000 (11:48 -0600)]
Support for system registers.

* Added all EL0 accessible system registers to dyn_regs.
* MSR and MRS (register) now add the system register (if EL0 accessible) and the source/destination register to the AST.
* Added a map from system register encodings to thier names. A function - buildSysRegMap - builds this map.

4 years agoModified logic for constructing an AST for a branch instruction.
Sunny Shah [Wed, 11 Nov 2015 20:14:48 +0000 (14:14 -0600)]
Modified logic for constructing an AST for a branch instruction.

Branches that are calls (BL and BLR) will add PC+4 as fallthrough instead of LR.

4 years agoFurther decoding fixes.
Bill Williams [Wed, 11 Nov 2015 20:10:36 +0000 (14:10 -0600)]
Further decoding fixes.

4 years agoresoleved conflicts
SteveXiSong [Tue, 10 Nov 2015 19:37:30 +0000 (13:37 -0600)]
resoleved conflicts

4 years agocommited weak solution to aliasing
SteveXiSong [Tue, 10 Nov 2015 19:34:42 +0000 (13:34 -0600)]
commited weak solution to aliasing

4 years agoFixed marking of an instruction as invalid by setting opcode to invalid and clearing...
Sunny Shah [Tue, 10 Nov 2015 17:41:45 +0000 (11:41 -0600)]
Fixed marking of an instruction as invalid by setting opcode to invalid and clearing the operands.
Modified read and write status of PSTATE for system instructions, as well as other changes to system instructions to handle operands correctly.

4 years agofixed bad switch cases
SteveXiSong [Tue, 10 Nov 2015 00:07:09 +0000 (18:07 -0600)]
fixed bad switch cases

4 years agoFixed detection of flaoting point compare instruction.
Sunny Shah [Mon, 9 Nov 2015 22:59:21 +0000 (16:59 -0600)]
Fixed detection of flaoting point compare instruction.

4 years agoFixed build issues relating to creating an immediate operand.
Sunny Shah [Mon, 9 Nov 2015 22:35:46 +0000 (16:35 -0600)]
Fixed build issues relating to creating an immediate operand.

4 years agoFixed build issues.
Sunny Shah [Mon, 9 Nov 2015 22:30:05 +0000 (16:30 -0600)]
Fixed build issues.

4 years agoFixed a minor bug in the instruction table.
Sunny Shah [Fri, 6 Nov 2015 21:48:21 +0000 (15:48 -0600)]
Fixed a minor bug in the instruction table.

No list_of() should be used when assigning an empty vector.

4 years agoChanged initialization of condStringMap to use the assign method which is passed...
Sunny Shah [Fri, 6 Nov 2015 20:49:16 +0000 (14:49 -0600)]
Changed initialization of condStringMap to use the assign method which is passed in an array.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
Sunny Shah [Fri, 6 Nov 2015 15:29:02 +0000 (09:29 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

Conflicts:
instructionAPI/src/InstructionDecoder-aarch64.C

4 years agoFixed handling of option field to match decode semantics in the manual as opposed...
Sunny Shah [Fri, 6 Nov 2015 15:26:14 +0000 (09:26 -0600)]
Fixed handling of option field to match decode semantics in the manual as opposed to the textual description of the field.

4 years agoadd field calls for '!=' fields
SteveXiSong [Fri, 6 Nov 2015 00:07:03 +0000 (18:07 -0600)]
add field calls for '!=' fields

4 years agoresolved conflicts
SteveXiSong [Thu, 5 Nov 2015 21:35:39 +0000 (15:35 -0600)]
resolved conflicts

4 years agofixed some minor bugs for ld/st
SteveXiSong [Thu, 5 Nov 2015 21:30:35 +0000 (15:30 -0600)]
fixed some minor bugs for ld/st

4 years agoFixes as part of validation.
Sunny Shah [Thu, 5 Nov 2015 17:31:39 +0000 (11:31 -0600)]
Fixes as part of validation.

* Added InstructionDecoder-aarch64 as a friend class of Operation so that mnemonics can be modified for conditional branches. Added a map of condition code to its string representation - the mnemonic is modified accordingly.
* Updated decoder and instruction table with output of most recent script.
* Added support for add/sub extended register instructions.
* Few other fixes for floating point instructions.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Wed, 4 Nov 2015 21:10:55 +0000 (15:10 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agovalidated ld class.
SteveXiSong [Wed, 4 Nov 2015 21:10:47 +0000 (15:10 -0600)]
validated ld class.

4 years agoModified register names for floating point registers.
Sunny Shah [Wed, 4 Nov 2015 16:16:07 +0000 (10:16 -0600)]
Modified register names for floating point registers.

Register names for FP registers were using incorrect values from dyn_regs.h for half/single/double precision. Fixed these to use names according to the manual.
Added support for zero-variants of some FP isntructions.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 3 Nov 2015 03:40:07 +0000 (21:40 -0600)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years ago1.re-ordered the alias instructions as a weak solution. 2.fixed some ld/st bugs....
SteveXiSong [Tue, 3 Nov 2015 03:39:37 +0000 (21:39 -0600)]
1.re-ordered the alias instructions as a weak solution. 2.fixed some ld/st bugs. 3.fixed a bug in unsign_extend64

4 years agoFixed ARM64 register sizes. Floating point register sizes were specified in accordanc...
Sunny Shah [Fri, 30 Oct 2015 21:05:21 +0000 (16:05 -0500)]
Fixed ARM64 register sizes. Floating point register sizes were specified in accordance with the nomenclature in the ARM manual, which differ from their actual sizes.

4 years agoupdate generator: type field is generated with using template
SteveXiSong [Thu, 29 Oct 2015 21:59:11 +0000 (16:59 -0500)]
update generator: type field is generated with using template

4 years agorestore the operand calling order
SteveXiSong [Thu, 29 Oct 2015 02:43:27 +0000 (21:43 -0500)]
restore the operand calling order

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Wed, 28 Oct 2015 19:57:02 +0000 (14:57 -0500)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agomark TODO functions
SteveXiSong [Wed, 28 Oct 2015 19:56:54 +0000 (14:56 -0500)]
mark TODO functions

4 years agoInstructionAPI decoding fixes.
Bill Williams [Wed, 28 Oct 2015 19:29:38 +0000 (14:29 -0500)]
InstructionAPI decoding fixes.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
Sunny Shah [Tue, 27 Oct 2015 22:16:04 +0000 (17:16 -0500)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoAdded complete instruction and decoder table generated from the python script.
Sunny Shah [Tue, 27 Oct 2015 22:14:48 +0000 (17:14 -0500)]
Added complete instruction and decoder table generated from the python script.

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 27 Oct 2015 22:04:01 +0000 (17:04 -0500)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agochange unallocated to IVALID
SteveXiSong [Tue, 27 Oct 2015 22:03:25 +0000 (17:03 -0500)]
change unallocated to IVALID

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
Sunny Shah [Tue, 27 Oct 2015 22:00:01 +0000 (17:00 -0500)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64

4 years agoChanged order of start and end bit names in oeprand templates and added updated ARM64...
Sunny Shah [Tue, 27 Oct 2015 21:59:38 +0000 (16:59 -0500)]
Changed order of start and end bit names in oeprand templates and added updated ARM64 opcode entry IDs to the entry ID enum.

4 years agoreplace ',' with COMMA
SteveXiSong [Tue, 27 Oct 2015 21:59:36 +0000 (16:59 -0500)]
replace ',' with COMMA

4 years agoMerge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64
SteveXiSong [Tue, 27 Oct 2015 21:42:28 +0000 (16:42 -0500)]
Merge branch 'arm64' of ssh://git.dyninst.org/pub/dyninst into arm64