dyninst.git
3 years agoWhen we encounter instructions without instruction semantics, we should stop jump...
Xiaozhu Meng [Fri, 11 Nov 2016 16:17:20 +0000 (10:17 -0600)]
When we encounter instructions without instruction semantics, we should stop jump table analyis.
In such case, if the missing instruction is key to the jump table analysis, we will not be able to
resolve it. If the missing instruction is not relevant to the jump table analysis, the slicing
is including unnecessary instruction. In either case, we should fix things.

3 years agoOn ARM, many jump table reads are one-byte memory reads. Assuming one-byte read yield...
Xiaozhu Meng [Fri, 11 Nov 2016 15:54:00 +0000 (09:54 -0600)]
On ARM, many jump table reads are one-byte memory reads. Assuming one-byte read yields a value in [0,255] would cause too many bogus edges. Disable this heuristics on ARM

3 years agoFix checking of zero flag for table index
Xiaozhu Meng [Fri, 11 Nov 2016 15:49:56 +0000 (09:49 -0600)]
Fix checking of zero flag for table index

3 years agoMerge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into...
Xiaozhu Meng [Thu, 10 Nov 2016 21:48:23 +0000 (15:48 -0600)]
Merge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into upstream/arm64/feature/semantics

3 years ago1. Add timing statistics for parsing
Xiaozhu Meng [Thu, 10 Nov 2016 21:47:13 +0000 (15:47 -0600)]
1. Add timing statistics for parsing
2. Fix tail call heuristics for ARM
3. Eliminate redundant indirect edges

3 years agoMerge branch 'arm64/feature/semantics' of bigking.cs.wisc.edu:/u/s/s/ssunny/dev-home...
Sunny Shah [Thu, 10 Nov 2016 19:16:03 +0000 (13:16 -0600)]
Merge branch 'arm64/feature/semantics' of bigking.cs.wisc.edu:/u/s/s/ssunny/dev-home/dyninst/dyninst-code into arm64/feature/semantics

3 years agoSemantics for immediate variants of LSL, LSR and ASR
Sunny Shah [Thu, 10 Nov 2016 18:24:21 +0000 (12:24 -0600)]
Semantics for immediate variants of LSL, LSR and ASR

3 years agoMerge branch 'upstream/arm64/feature/semantics' of coriander.cs.wisc.edu:/p/paradyn...
Xiaozhu Meng [Mon, 7 Nov 2016 17:37:19 +0000 (11:37 -0600)]
Merge branch 'upstream/arm64/feature/semantics' of coriander.cs.wisc.edu:/p/paradyn/development/xmeng/dyninstapi/dyninst_development/dyninst into upstream/arm64/feature/semantics

3 years agoSemantics for EOR variants and EON
Sunny Shah [Mon, 7 Nov 2016 16:48:58 +0000 (10:48 -0600)]
Semantics for EOR variants and EON

3 years agoSemantics for ORR variants (including two MOV instructions), ORN and AND/ANDS variants
Sunny Shah [Mon, 7 Nov 2016 16:42:47 +0000 (10:42 -0600)]
Semantics for ORR variants (including two MOV instructions), ORN and AND/ANDS variants

The semantics use the newly added LogicalOp enum to identify the type of
logical operation.

3 years agoMerge branch 'upstream/arm64/feature/semantics' of coriander.cs.wisc.edu:/p/paradyn...
Xiaozhu Meng [Mon, 7 Nov 2016 14:51:19 +0000 (08:51 -0600)]
Merge branch 'upstream/arm64/feature/semantics' of coriander.cs.wisc.edu:/p/paradyn/development/xmeng/dyninstapi/dyninst_development/dyninst into upstream/arm64/feature/semantics

3 years agoInstruction decoding fix: Alias ORR to MOV when the first source operand is WZR and...
Sunny Shah [Sun, 6 Nov 2016 23:41:34 +0000 (17:41 -0600)]
Instruction decoding fix: Alias ORR to MOV when the first source operand is WZR and the 'shift'
and 'imm6' fields are both 0.

3 years agoMerge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into...
Xiaozhu Meng [Fri, 4 Nov 2016 18:53:35 +0000 (13:53 -0500)]
Merge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into upstream/arm64/feature/semantics

3 years agoFix for decoding error in register based load/store instructions
Sunny Shah [Fri, 4 Nov 2016 17:14:35 +0000 (12:14 -0500)]
Fix for decoding error in register based load/store instructions

The shift amount for the second source register in load/store (register)
instructions should depend only on the value of the 'S' field.

3 years agoUpdated semantics for SBFM and UBFM variants
Sunny Shah [Thu, 3 Nov 2016 19:28:59 +0000 (14:28 -0500)]
Updated semantics for SBFM and UBFM variants

Semantics updated to not make redundant function calls with the same arguments. Also added implementation for DispatcherARM64::getBitfieldMask().

3 years agoAllow reading of operands with a SgAsmBinaryLsr as the root expression
Sunny Shah [Tue, 1 Nov 2016 21:49:40 +0000 (16:49 -0500)]
Allow reading of operands with a SgAsmBinaryLsr as the root expression

3 years agoAdded ability to read operands that have a SgAsmBinaryAsr as the root expression
Sunny Shah [Tue, 1 Nov 2016 20:45:27 +0000 (15:45 -0500)]
Added ability to read operands that have a SgAsmBinaryAsr as the root expression

3 years agoSemantics for MOVZ, MOVK, MOVN and the MOV variants of MOVZ and MOVN
Sunny Shah [Mon, 31 Oct 2016 22:19:01 +0000 (17:19 -0500)]
Semantics for MOVZ, MOVK, MOVN and the MOV variants of MOVZ and MOVN

Also added enum (MoveWideOp) used in these semantics to determine the
type of move

3 years agoAdded a method to get the target SgAsmExpression when executing
Sunny Shah [Mon, 31 Oct 2016 21:52:30 +0000 (16:52 -0500)]
Added a method to get the target SgAsmExpression when executing
write-back for load/store instructions

3 years agoSemantics for UBFM and SBFM variants
Sunny Shah [Thu, 20 Oct 2016 21:48:49 +0000 (16:48 -0500)]
Semantics for UBFM and SBFM variants

This commit introduces semantics for the 5 UBFM variants (UXTB, UXTH, UBFM, UBFIZ, UBFX) and SBFM variants (SXTB, SXTH, SBFM, SBFIZ, SBFX), and a couple functions in the DispatcherARM64 class used by these semantics. Implementation of one of these functions needs to be updated (next commit) and UXTB's semantics are modified to proceed with jump table analysis for now; the original semantics are still present as comments and will be restored in a future commit.

3 years agoFixed typo that caused low bit to be gretaer than the high bit when extracting a...
Sunny Shah [Tue, 11 Oct 2016 21:33:39 +0000 (16:33 -0500)]
Fixed typo that caused low bit to be gretaer than the high bit when extracting a value from an integer in DispatcherARM64::getRegSize()

3 years ago1. Should delete alias AST when a part of it is assigned a new value.
Xiaozhu Meng [Tue, 11 Oct 2016 20:01:44 +0000 (15:01 -0500)]
1. Should delete alias AST when a part of it is assigned a new value.
2. Change Arch_x86 and Arch_x86_64 checking to use address width

3 years agoModified implementation of DispatcherARM64::ConditionHolds()
Sunny Shah [Tue, 11 Oct 2016 18:19:57 +0000 (13:19 -0500)]
Modified implementation of DispatcherARM64::ConditionHolds()

The previous implementation did not make use of the fact the condition value in the expression can be retrieved as a raw integer value and does not have to be treated as a SValuePtr. Treating as an integer greatly simplifies assignment expression for all flags and also makes the code more readable.

3 years agoBug fixes for converting Dyninst Instruction API objects to ROSE SgAsmInstruction...
Sunny Shah [Tue, 11 Oct 2016 18:17:11 +0000 (13:17 -0500)]
Bug fixes for converting Dyninst Instruction API objects to ROSE SgAsmInstruction objects for ARM64.

* RoseImpl.C: Fixed a bug that caused a stackoverflow when retrieving the SgAsmType of a SgAsmBinaryExpression
* ExpressionConversionVisitor.C: Fixed a typo (there was a && instead of &) that caused all registers to fall through to the call to getROSERegister (this should not be happening when the register is PSTATE)

3 years agoMerge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into...
Xiaozhu Meng [Thu, 6 Oct 2016 21:36:09 +0000 (16:36 -0500)]
Merge branch 'arm64/feature/semantics' of /home/ssunny/dyninst/dyninst-code into upstream/arm64/feature/semantics

3 years agoSemantics for FMOV
Sunny Shah [Thu, 6 Oct 2016 19:37:16 +0000 (14:37 -0500)]
Semantics for FMOV

Added semantics manaully for FMOV. Floating point operations ar enot yet supported; however, the variant of FMOV we are seeing in jump tables does nothing but move a value from a FP register to a general purpose register. To allow the analysis to continue, the semantics for this instruction are thus manually added for now.

3 years agoBug fix for setting major and minor numbers of the ZR register when
Sunny Shah [Thu, 6 Oct 2016 18:49:43 +0000 (13:49 -0500)]
Bug fix for setting major and minor numbers of the ZR register when
converting from Dyninst to ROSE's representation.

The category of ZR/WZR in Dyninst is SPR and not GPR -- this fix moves
the major and minor number setting block to the appropriate case
statement.

3 years agoAdded ability to convert the ARM64 SIMD/FP registers between ROSE(semantics) and...
Sunny Shah [Thu, 6 Oct 2016 16:11:47 +0000 (11:11 -0500)]
Added ability to convert the ARM64 SIMD/FP registers between ROSE(semantics) and Dyninst.
- getROSERegister() supports computing the different values of a
RegisterDescriptor for ARM64 SIMD/FP registers
- RegisterDescriptors for all accessible parts of a SIMD/FP register
(8-bit, 16-bit, 32-bit, upper and lower 64-bit and 128-bit) are added to
the RegisterDictionary for ARM64 in ROSE semantics
- SymEvalSemantics now converts from SIMD/FP registers to
Dyninst::MachRegisters.

3 years ago1. Jump table contents can be first multiplied and then added to a jump base.
Xiaozhu Meng [Wed, 5 Oct 2016 01:45:57 +0000 (20:45 -0500)]
1. Jump table contents can be first multiplied and then added to a jump base.
2. On ARMV8, the PC value is pre-instruction, while the PC value is post-instruction on x86/x64

3 years agoThe mask used when modifying a certain range of bits of a value was clearing out...
Sunny Shah [Tue, 4 Oct 2016 17:56:50 +0000 (12:56 -0500)]
The mask used when modifying a certain range of bits of a value was clearing out the bits that didn't need to be modified and perserving those that needed to be. Fixed to use the invert of this as the actual mask.
Additionally, the 'imm' and 'bit_pos' variables correspond to the second, and not the first, operand in the operand list.

3 years ago1. Add an architecture-independent interface to check whether a register represents...
Xiaozhu Meng [Tue, 4 Oct 2016 15:55:46 +0000 (10:55 -0500)]
1. Add an architecture-independent interface to check whether a register represents a flag
2. In jump table analysis, perform shift-left operations if both operands are constant and use architecture-independent interface

3 years agoWhen converting read/written registers to assignments for an instruction, replace...
Sunny Shah [Mon, 3 Oct 2016 16:57:12 +0000 (11:57 -0500)]
When converting read/written registers to assignments for an instruction, replace all references to PSTATE with N, Z, C and V for ARM64.

3 years agoIgnore the PSTATE register when converting an instruction to ROSE's format
Sunny Shah [Wed, 28 Sep 2016 23:30:35 +0000 (18:30 -0500)]
Ignore the PSTATE register when converting an instruction to ROSE's format

3 years ago1. Create an architecture independent interface to get the zero flag register and...
Xiaozhu Meng [Wed, 28 Sep 2016 18:54:58 +0000 (13:54 -0500)]
1. Create an architecture independent interface to get the zero flag register and use it in jump table analysis
2. Change slicing code to use architecture independent interface to get program counter

3 years agoUpdated semantics to use register descriptor REG_N, REG_Z, REG_C, REG_V
Sunny Shah [Tue, 27 Sep 2016 19:08:51 +0000 (14:08 -0500)]
Updated semantics to use register descriptor REG_N, REG_Z, REG_C, REG_V
for the flags instead of REG_NZCV.

3 years agoModify DispatcherARM64 methods accessing flags to read/write them
Sunny Shah [Mon, 26 Sep 2016 19:42:32 +0000 (14:42 -0500)]
Modify DispatcherARM64 methods accessing flags to read/write them
individually from/to the respective registers. This includes changes to
the method signatures where required.

3 years agoRegister definitions for treating the 4 ARM64 flags separately
Sunny Shah [Fri, 23 Sep 2016 17:49:43 +0000 (12:49 -0500)]
Register definitions for treating the 4 ARM64 flags separately

As with dataflow analysis on other architectures, each flag should be treated as a distinct unit. Following changes, made as part of this commit, achieve this:
- n, z, c and v have been added as individual register definitions in dyn_regs with their baseIDs indicating their positions in the pstate register. The conversions from Dyninst to ROSE registers for these new additions are also defined.
- The 'nzcv' enum value in ARMv8PstateFields (for use in ARM semantics) is split into 4 different values, one for each flag. Each of these is also added to the register dictionary for ARMv8 in Registers.C.

3 years agoThe argument to SymEvalSemantics::addWithCarries for unsign-extending
Sunny Shah [Sun, 18 Sep 2016 23:39:47 +0000 (18:39 -0500)]
The argument to SymEvalSemantics::addWithCarries for unsign-extending
the second addend should be the second operand from the instruction AST.

The bug here was that the first operand from the AST was being passed
for the unsign-extend operation. This caused the semantic expression and
hence the resulting assignment expansion for the instructions calling
this function to be incorrect.

3 years agoWhen determining the ROSE register category for ARM registers, comparisions of the...
Sunny Shah [Wed, 14 Sep 2016 17:54:12 +0000 (12:54 -0500)]
When determining the ROSE register category for ARM registers, comparisions of the MachRegisters with 'baseID' should only use the MachRegister's lowermost 16 bits.

3 years agoEffective address calculation and load/store instruction semantics fixes.
Sunny Shah [Mon, 12 Sep 2016 22:05:14 +0000 (17:05 -0500)]
Effective address calculation and load/store instruction semantics fixes.

The 'address' variable in the semantics for load/store instructions should not directly call Dispatcher::read(), but should only store the address of the target location in memory. The semantics have been updated to reflect this. A new method - DispatcherARM64::effectiveAddress() - is added which is called in the above scenario.

In addition, the pre-fix part of the address calculation doesn't have to be performed again in dataflow API since the required information is already encoded in the AST by instruction API.

3 years agoMinor fixes for ARM64 semantics
Sunny Shah [Mon, 12 Sep 2016 22:02:22 +0000 (17:02 -0500)]
Minor fixes for ARM64 semantics

* Fixed order of arguments in initialization of a boolean SValue in SymEvalSemantics
* Dispatcher::read() in BaseSemantics now does not assert if the input expression is an SgAsmBinaryLsl

3 years agoAdded semantics for the following instructions:
Sunny Shah [Fri, 9 Sep 2016 16:29:59 +0000 (11:29 -0500)]
Added semantics for the following instructions:

* Immediate and register variants of LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH
* Literal variants of LDR and LDRSW

The signatures of readMemory() and writeMemory() in SymEvalSemantics::StateARM64 and SymEvalSemantics::MemoryStateARM64 are modified to be able to pass in the read and write sizes.

3 years agoFix register conversion between Dyninst and ROSE
Sunny Shah [Thu, 21 Jul 2016 20:54:29 +0000 (15:54 -0500)]
Fix register conversion between Dyninst and ROSE
* The conversion of a Dyninst register to ROSE was using the full integer value in MachRegister, whereas only the lower 16 bits have to be used.
* convert() in SymEvalSemantics now takes in a RegisterDescriptor as argument to support all register categories other than SIMD/FPR.

Also fixed a few small bugs in the Dispatcher class for ARM.

3 years agoMerge pull request #127 from dyninst/arm64/feature/semantics_setup
ssunny7 [Thu, 21 Jul 2016 20:39:44 +0000 (15:39 -0500)]
Merge pull request #127 from dyninst/arm64/feature/semantics_setup

Merge arm64/feature/semantics_setup into master

3 years agoset_type() in SgAsmExpression has to be virtual 127/head
Sunny Shah [Mon, 18 Jul 2016 22:13:12 +0000 (17:13 -0500)]
set_type() in SgAsmExpression has to be virtual

3 years agoMerge pull request #124 from dyninst/v9.2_patches
John Detter [Fri, 15 Jul 2016 15:55:56 +0000 (10:55 -0500)]
Merge pull request #124 from dyninst/v9.2_patches

V9.2 patches

3 years agoFixed issues seen while parsing a simple ARM binary
Sunny Shah [Thu, 14 Jul 2016 19:13:56 +0000 (14:13 -0500)]
Fixed issues seen while parsing a simple ARM binary

* Direct register expressions need to have their type set - this is set to SgAsmIntegerType for now. The type's signed-ness is set to unsigned, but it shouldn't matter because the only place register expressions' types are used is when accessing the width.
* regPos wasn't being set correctly for ARM flags when converting a Dyninst register to a ROSE register.
* The correct jump table analysis functions are now being called for ARM binaries.

3 years agoCreate Dispatcher object during symbolic expansion for instruction processing
Sunny Shah [Wed, 13 Jul 2016 16:25:23 +0000 (11:25 -0500)]
Create Dispatcher object during symbolic expansion for instruction processing

A BaseSemantics::Dispatcher object is created using the passed in RiscOperators object during the expansion of ARM64 instructions. A similar thing will be done for other architectures once they move to the new semantics.

3 years agoFixed issues seen while building SymEvalSemantics.C.
Sunny Shah [Wed, 13 Jul 2016 16:04:08 +0000 (11:04 -0500)]
Fixed issues seen while building SymEvalSemantics.C.

3 years agoAdded implementation for RiscOperators::addWithCarries().
Sunny Shah [Wed, 13 Jul 2016 16:02:26 +0000 (11:02 -0500)]
Added implementation for RiscOperators::addWithCarries().

4 years agoMerge pull request #118 from dyninst/release9.2/fixes/liveness-patch 124/head
John Detter [Tue, 12 Jul 2016 21:57:36 +0000 (16:57 -0500)]
Merge pull request #118 from dyninst/release9.2/fixes/liveness-patch

Release9.2/fixes/liveness patch

4 years agoAdded redundant register definitions 118/head
John Detter [Tue, 12 Jul 2016 21:51:39 +0000 (16:51 -0500)]
Added redundant register definitions

4 years agoMerge branch 'master' into release9.2/fixes/liveness-patch
John Detter [Tue, 12 Jul 2016 21:03:11 +0000 (16:03 -0500)]
Merge branch 'master' into release9.2/fixes/liveness-patch

4 years agoFix for #114. Support has been added for 32 bit YMM, ZMM and K mask registers to...
John Detter [Tue, 12 Jul 2016 20:59:28 +0000 (15:59 -0500)]
Fix for #114. Support has been added for 32 bit YMM, ZMM and K mask registers to prevent future similar issues.

4 years agoAllow accessing StateARM64's Dyninst::Address member in RegisterStateARM64 for use...
Sunny Shah [Tue, 12 Jul 2016 17:50:44 +0000 (12:50 -0500)]
Allow accessing StateARM64's Dyninst::Address member in RegisterStateARM64 for use by wrap().

When calling wrap() in RegisterStateARM64::readRegister(), the Dyninst::Address member passed in to StateARM64 needs to be accessed. A new RegisterStateARM64::readRegister is added which takes the RegisterDescriptor and the Dyninst::Address, and the default readRegister() causes an assert().

RiscOperators in SymEvalSemantics is renamed to RiscOperatorsARM64. Two methods in it were wrongly named -- they have been renamed to their correct versions.

Building of SymEvalSemantics is also enabled now.

4 years agoWhen reaching shared blocks that have been parsed, we still need to invalidate the...
Xiaozhu Meng [Tue, 12 Jul 2016 16:36:34 +0000 (11:36 -0500)]
When reaching shared blocks that have been parsed, we still need to invalidate the cache of the current function as the function should include all the shared blocks

4 years agoMerge branch 'release9.2/fixes/aes-extension' into v9.2_patches
John Detter [Mon, 11 Jul 2016 07:00:48 +0000 (02:00 -0500)]
Merge branch 'release9.2/fixes/aes-extension' into v9.2_patches

4 years agoMerge branch 'release9.2/fixes/modify-data-assert' into v9.2_patches
John Detter [Mon, 11 Jul 2016 07:00:30 +0000 (02:00 -0500)]
Merge branch 'release9.2/fixes/modify-data-assert' into v9.2_patches

4 years agoAdded definitions for the remaining pure virtual members of the RiscOperators class...
Sunny Shah [Fri, 8 Jul 2016 21:56:40 +0000 (16:56 -0500)]
Added definitions for the remaining pure virtual members of the RiscOperators class for use by SymEvalSemantics.

4 years agoAdded definitions for about half of the pure virtual methods of the RiscOperators...
Sunny Shah [Fri, 8 Jul 2016 21:26:29 +0000 (16:26 -0500)]
Added definitions for about half of the pure virtual methods of the RiscOperators class.

Most of these micro-operations just translate to the creation of a unary/binary/ternary AST. Utility methods for creating such ASTs and then wrapping them around a SValuePtr are also added.

4 years agoDefinitions of the register state, memory state and value type for SymEval semantics...
Sunny Shah [Fri, 8 Jul 2016 17:29:16 +0000 (12:29 -0500)]
Definitions of the register state, memory state and value type for SymEval semantics are now complete.

Also modified the intialization of all 4 required components in SymEval.C to use the new definitions instead of those in BaseSemantics2.h. The final RiscOperators object is thus setup to be usable by Dyninst.

4 years agoFix for #116
John Detter [Thu, 7 Jul 2016 21:04:52 +0000 (16:04 -0500)]
Fix for #116

4 years agoRemoved slicing check for "skipRegs".
Matt Morehouse [Thu, 7 Jul 2016 20:34:56 +0000 (15:34 -0500)]
Removed slicing check for "skipRegs".

Instruction displacement updates were being incorrectly calculated
for registers labeled as skipRegs.  Simply labeling such registers
as non-skipRegs fixes the issue.  Fixes #113.

4 years agoAdded missing CRC32 instruction variation 115/head
John Detter [Wed, 6 Jul 2016 21:19:09 +0000 (16:19 -0500)]
Added missing CRC32 instruction variation

4 years agoAES instruction extension complete.
John Detter [Wed, 6 Jul 2016 20:59:06 +0000 (15:59 -0500)]
AES instruction extension complete.

4 years agoAdding support for aes instruction set extension
John Detter [Wed, 6 Jul 2016 20:30:34 +0000 (15:30 -0500)]
Adding support for aes instruction set extension

4 years agoAdded definitions/declarations of methods for the ARM64 register state
Sunny Shah [Tue, 5 Jul 2016 18:00:27 +0000 (13:00 -0500)]
Added definitions/declarations of methods for the ARM64 register state

4 years agoClass declarations for SymEvalSemantics
Sunny Shah [Fri, 1 Jul 2016 22:02:15 +0000 (17:02 -0500)]
Class declarations for SymEvalSemantics

SymEvalPolicy is now called "SymEvalSemantics" - in line with the terminology of the new semantics framework. Using this requires the implementation of 4 main classes - SValue (the value type), RegisterState, MemoryState and RiscOperators. All of these inherit from their respective definitions in BaseSemantics2.h.

Everything from the old policy (eg. SymEvalPolicy) needs to be mapped to these 4 classes. Currently, the implementation of SValue is mostly complete (a couple methods are yet to be implemented and few others need a little more thought) and declarations for some methods in RiscOperators have been added.

4 years agoInitialize semantics for use with ARM64
Sunny Shah [Thu, 30 Jun 2016 18:21:25 +0000 (13:21 -0500)]
Initialize semantics for use with ARM64

Before the dispatcher for ARM64 can be called for instruction processing, the value type, register state, memory state and RISC operators need to be initialized. Ideally, these should be specific to Dyninst's SymEvalPolicy. That policy, however, needs to be re-written to work with the new semantics - this hasn't been done yet. Thus the current initializations of the type, states and operators use the base types (defined in BaseSemantics2.h) and will later by replaced by concretized versions.

4 years agoUpdate version numbers and dates in doc manuals v9.2.0
Xiaozhu Meng [Wed, 29 Jun 2016 21:54:14 +0000 (16:54 -0500)]
Update version numbers and dates in doc manuals

4 years agoBump version number and date for dyninstAPI and proccontrol manuals
Xiaozhu Meng [Wed, 29 Jun 2016 21:59:35 +0000 (16:59 -0500)]
Bump version number and date for dyninstAPI and proccontrol manuals

4 years agoAdd dataflow manual.
Bill Williams [Wed, 29 Jun 2016 21:50:18 +0000 (16:50 -0500)]
Add dataflow manual.

4 years agoUpdate manuals and docs target for 9.2.
Bill Williams [Wed, 29 Jun 2016 21:49:44 +0000 (16:49 -0500)]
Update manuals and docs target for 9.2.

4 years agoBump version to 9.2.0 and update README with 9.2 release notes.
Bill Williams [Wed, 29 Jun 2016 21:16:44 +0000 (16:16 -0500)]
Bump version to 9.2.0 and update README with 9.2 release notes.

4 years agoTrack the relationship between base and subregisters.
Matt Morehouse [Wed, 29 Jun 2016 19:17:31 +0000 (14:17 -0500)]
Track the relationship between base and subregisters.

Any modification of a base register (e.g., RAX) has a related
modification on its subregister (e.g., EAX).  The opposite is also
true.  This commit introduces functionality to track that
relationship so that modifying one register in the pair affects the
other register appropriately.

4 years agoRemove flag tracking from StackAnalysis.
Matt Morehouse [Wed, 29 Jun 2016 18:11:09 +0000 (13:11 -0500)]
Remove flag tracking from StackAnalysis.

4 years agoImprove handling of XOR.
Matt Morehouse [Wed, 29 Jun 2016 18:04:41 +0000 (13:04 -0500)]
Improve handling of XOR.

Add memory tracking to StackAnalysis::handleXor() and replace
the default handling with more correct handling.

4 years agoChange representation of delta functions.
Matt Morehouse [Wed, 29 Jun 2016 17:40:13 +0000 (12:40 -0500)]
Change representation of delta functions.

Represent delta functions as "copies with deltas", where the from
and target locations are the same.  This representation simplifies
much of the accumulation logic for deltas.

4 years agoRemove sentinel values from Height and TransferFunc classes.
Matt Morehouse [Wed, 29 Jun 2016 17:25:39 +0000 (12:25 -0500)]
Remove sentinel values from Height and TransferFunc classes.

Use a flag to specify TOP and BOTTOM rather than MAX_LONG and
MIN_LONG.

4 years agoReorganize StackAnalysis header file.
Matt Morehouse [Wed, 29 Jun 2016 17:00:33 +0000 (12:00 -0500)]
Reorganize StackAnalysis header file.

Move some implementation details to the implementation file to
avoid clutter.  Also ensure uniform indentation in both files.

4 years agoAdd function summary capability to StackAnalysis.
Matt Morehouse [Wed, 29 Jun 2016 16:20:45 +0000 (11:20 -0500)]
Add function summary capability to StackAnalysis.

A function summary is a mapping from Abslocs to TransferFuncs. Each
Absloc in the mapping represents an abstract location that is
modified by the function. Each TransferFunc in the mapping
describes how the corresponding Absloc is defined in terms of
function inputs after the function returns. This commit adds the
StackAnalysis::getFunctionSummary() method which generates and
returns function summaries for the specified function.

4 years agoMiscellaneous accumulation logic fixes.
Matt Morehouse [Wed, 29 Jun 2016 00:16:32 +0000 (19:16 -0500)]
Miscellaneous accumulation logic fixes.

4 years agoFix return handling and add memory tracking for leave instructions.
Matt Morehouse [Wed, 29 Jun 2016 00:14:58 +0000 (19:14 -0500)]
Fix return handling and add memory tracking for leave instructions.

4 years agoAdd memory tracking for push/pop instructions.
Matt Morehouse [Wed, 29 Jun 2016 00:05:28 +0000 (19:05 -0500)]
Add memory tracking for push/pop instructions.

4 years agoRename aliasFunc to copyFunc.
Matt Morehouse [Wed, 29 Jun 2016 00:03:45 +0000 (19:03 -0500)]
Rename aliasFunc to copyFunc.

Copying is a more accurate description of the operation that
aliasFunc has been capturing since the copied value can be modified
without changing any of the other copies.

4 years agoAdd check for stack accesses with unknown offsets.
Matt Morehouse [Tue, 28 Jun 2016 23:59:22 +0000 (18:59 -0500)]
Add check for stack accesses with unknown offsets.

4 years agoMerge branch 'arm64/feature/semantics_importnew'
Sunny Shah [Wed, 29 Jun 2016 18:03:13 +0000 (13:03 -0500)]
Merge branch 'arm64/feature/semantics_importnew'

4 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sunny Shah [Wed, 29 Jun 2016 18:02:53 +0000 (13:02 -0500)]
Merge branch 'master' of https://github.com/dyninst/dyninst

4 years agoMerge pull request #112 from dyninst/release9.2/fixes/rewriter_assert
John Detter [Wed, 29 Jun 2016 15:59:17 +0000 (10:59 -0500)]
Merge pull request #112 from dyninst/release9.2/fixes/rewriter_assert

Disabled condition decoding in stack rewriting.

4 years agoDisabled condition decoding in stack rewriting. 112/head
John Detter [Wed, 29 Jun 2016 14:35:33 +0000 (09:35 -0500)]
Disabled condition decoding in stack rewriting.

4 years agoMerge pull request #109 from cuviper/paged-papercuts
Bill Williams [Tue, 28 Jun 2016 21:11:06 +0000 (16:11 -0500)]
Merge pull request #109 from cuviper/paged-papercuts

symtabAPI: Apply corrections for the library_adjust page offset

4 years agoMerge pull request #107 from dyninst/VEX
John Detter [Tue, 28 Jun 2016 20:32:19 +0000 (15:32 -0500)]
Merge pull request #107 from dyninst/VEX

Rewriter fixes, instruction decoding fixes.

4 years agoProperly check the return value of inferior malloc irpc 107/head
Xiaozhu Meng [Tue, 28 Jun 2016 18:34:12 +0000 (13:34 -0500)]
Properly check the return value of inferior malloc irpc

4 years agosymtabAPI: Apply corrections for the library_adjust page offset 109/head
Josh Stone [Tue, 28 Jun 2016 00:44:49 +0000 (17:44 -0700)]
symtabAPI: Apply corrections for the library_adjust page offset

This commit aggregates the incremental fixes that Bill Williams and I
found while investigating issue #93, rewriting libc.so.

- The offsets of new sections need to account for library_adjust when
  placing themselves after the first new section.
- TLS symbol values need *not* be adjusted, as they're section-relative.
- DT_INIT/FINI values need to be adjusted.
- x86 IRELATIVE relocations need their addends adjusted.

Fixes #93.

4 years agoMerge branch 'VEX' of http://github.com/dyninst/dyninst into VEX
John Detter [Tue, 28 Jun 2016 00:26:21 +0000 (19:26 -0500)]
Merge branch 'VEX' of github.com/dyninst/dyninst into VEX

4 years agoFixed Mark Krentel's build issue
John Detter [Mon, 27 Jun 2016 23:47:43 +0000 (18:47 -0500)]
Fixed Mark Krentel's build issue

4 years agoMerge pull request #105 from pefoley2/llvm_travis
Bill Williams [Mon, 27 Jun 2016 21:13:49 +0000 (16:13 -0500)]
Merge pull request #105 from pefoley2/llvm_travis

Don't use broken llvm apt mirror

4 years agoMerge branch 'master' of https://github.com/dyninst/dyninst
Sunny Shah [Mon, 27 Jun 2016 17:21:23 +0000 (12:21 -0500)]
Merge branch 'master' of https://github.com/dyninst/dyninst

4 years agoIntegration of ROSE's new semantics framework with Dyninst
Sunny Shah [Mon, 27 Jun 2016 17:07:07 +0000 (12:07 -0500)]
Integration of ROSE's new semantics framework with Dyninst

This commit brings in and sets up all the files required to use the new ROSE semantics framework from within Dyninst. The starting point for this was the src/midend/binaryAnalyses/instructionSemantics folder within ROSE's source tree. All the other files have been added because semantics directlyu or indirectly depends on them.

After adding the file to the Dyninst source, several changes may or may not have been made to it. Most of the changes revolve around updating the include paths and removing any macros used by ROSE but not required by Dyninst. Other minor changes have also been made based on build errors/warnings.

Currently, he build succeeds but with a ton of warnings. I've suppressed them for the time being.

By doing this, both old and new instruction semantics should ideally be able to co-exist, although this hasn't been tested yet.

4 years agoMerge pull request #108 from pefoley2/VEX_win
John Detter [Mon, 27 Jun 2016 16:40:43 +0000 (11:40 -0500)]
Merge pull request #108 from pefoley2/VEX_win

fix dll linkage on windows