Instructions in the load/store category with V (bit 26) set to 1 use SIMD registers...
authorSunny Shah <shah28@wisc.edu>
Sun, 13 Mar 2016 06:18:31 +0000 (00:18 -0600)
committerSunny Shah <shah28@wisc.edu>
Sun, 13 Mar 2016 06:18:31 +0000 (00:18 -0600)
commit952820a7f9b9f0ed472e85f2f7d819e75a9e108c
tree4d4f09f6c44e5bca8c4fdeb88ae2f9e783428004
parent441b073d018fc23aecba510a5c084f3285b37fec
Instructions in the load/store category with V (bit 26) set to 1 use SIMD registers for Rd and Rn. Fixed now to handle this case.
instructionAPI/src/InstructionDecoder-aarch64.C
instructionAPI/src/InstructionDecoder-aarch64.h