Modified logic for constructing an AST for a branch instruction.
authorSunny Shah <shah28@wisc.edu>
Wed, 11 Nov 2015 20:14:48 +0000 (14:14 -0600)
committerSunny Shah <shah28@wisc.edu>
Wed, 11 Nov 2015 20:14:48 +0000 (14:14 -0600)
commit0f96f157bfc83a6a49c069840cfab16bbe9e1962
tree70ee3b47f56e35703f583926d1a4234daefaf891
parent4302dd009138581bb66feb89819b46e4bc48964f
Modified logic for constructing an AST for a branch instruction.

Branches that are calls (BL and BLR) will add PC+4 as fallthrough instead of LR.
instructionAPI/src/InstructionDecoder-aarch64.C
instructionAPI/src/InstructionDecoder-aarch64.h