Bugfixes for slicing and general compile fixes for SymEval component
[dyninst.git] / symEval / rose / SgAsmx86Instruction.h
1 #if !defined(SG_ASM_X86_INSN_H)
2 #define SG_ASM_X86_INSN_H
3 // This information is cut from a generated SAGEIII file. 
4 // Since we only need the data structure definition I've
5 // extracted that from the larger generated file.
6
7 // All methods that do not appear to be used by x86InstructionSemantics.h
8 // have been commented out. 
9
10 #include "enums.h"
11 #include "typedefs.h"
12 #include "SgNode.h"
13
14 #include "SgAsmOperandList.h"
15
16 class SgAsmx86Instruction : public SgNode {
17  public:
18     /*! \brief returns a string representing the class name */
19     virtual std::string class_name() const;
20     
21     /*! \brief returns new style SageIII enum values */
22     virtual VariantT variantT() const; // MS: new variant used in tree traversal
23     
24     /*! \brief static variant value */
25     static const VariantT static_variant = V_SgAsmx86Instruction;
26     
27     /* the generated cast function */
28     /*! \brief Casts pointer from base class to derived class */
29     friend       SgAsmx86Instruction* isSgAsmx86Instruction(       SgNode * s );
30     /*! \brief Casts pointer from base class to derived class (for const pointers) */
31     friend const SgAsmx86Instruction* isSgAsmx86Instruction( const SgNode * s );
32     
33     X86InstructionKind get_kind() const;
34     void set_kind(X86InstructionKind kind);
35     
36     X86InstructionSize get_baseSize() const;
37     void set_baseSize(X86InstructionSize baseSize);
38     
39     X86InstructionSize get_operandSize() const;
40     void set_operandSize(X86InstructionSize operandSize);
41     
42     X86InstructionSize get_addressSize() const;
43     void set_addressSize(X86InstructionSize addressSize);
44     
45     bool get_lockPrefix() const;
46     void set_lockPrefix(bool lockPrefix);
47     
48     X86RepeatPrefix get_repeatPrefix() const;
49     void set_repeatPrefix(X86RepeatPrefix repeatPrefix);
50     
51     X86BranchPrediction get_branchPrediction() const;
52     void set_branchPrediction(X86BranchPrediction branchPrediction);
53     
54     X86SegmentRegister get_segmentOverride() const;
55     void set_segmentOverride(X86SegmentRegister segmentOverride);
56     
57     virtual ~SgAsmx86Instruction();
58     
59     SgAsmx86Instruction(rose_addr_t address = 0, 
60                         std::string mnemonic = "", 
61                         X86InstructionKind kind = x86_unknown_instruction, 
62                         X86InstructionSize baseSize = x86_insnsize_none, 
63                         X86InstructionSize operandSize = x86_insnsize_none, 
64                         X86InstructionSize addressSize = x86_insnsize_none); 
65
66     std::string get_mnemonic() const;
67     void set_mnemonic(std::string mnemonic);
68     
69     SgUnsignedCharList get_raw_bytes() const;
70     void set_raw_bytes(SgUnsignedCharList raw_bytes);
71     
72     SgAsmOperandList* get_operandList() const;
73     void set_operandList(SgAsmOperandList* operandList);
74     
75     rose_addr_t get_address() const;
76     void set_address(rose_addr_t address);
77
78     std::string get_comment() const;
79     void set_comment(std::string comment);
80     
81     
82  protected:
83     std::string p_mnemonic;
84     
85     SgUnsignedCharList p_raw_bytes;
86     
87     SgAsmOperandList* p_operandList;
88
89     rose_addr_t p_address;
90           
91     std::string p_comment;
92
93
94     X86InstructionKind p_kind;
95     
96     X86InstructionSize p_baseSize;
97     
98     X86InstructionSize p_operandSize;
99     
100     X86InstructionSize p_addressSize;
101     
102     bool p_lockPrefix;
103           
104     X86RepeatPrefix p_repeatPrefix;
105           
106     X86BranchPrediction p_branchPrediction;
107           
108     X86SegmentRegister p_segmentOverride;
109     
110     // End of memberFunctionString
111     
112 };
113
114 // from  src/frontend/BinaryDisassembly/x86InstructionProperties.h
115
116 bool x86InstructionIsConditionalFlagControlTransfer(SgAsmx86Instruction* inst);
117 bool x86InstructionIsConditionalFlagDataTransfer(SgAsmx86Instruction* inst);
118 bool x86InstructionIsConditionalControlTransfer(SgAsmx86Instruction* inst);
119 bool x86InstructionIsConditionalDataTransfer(SgAsmx86Instruction* inst);
120
121 bool x86InstructionIsConditionalFlagBitAndByte(SgAsmx86Instruction* inst);
122
123 bool x86InstructionIsControlTransfer(SgAsmx86Instruction* inst);
124 bool x86InstructionIsUnconditionalBranch(SgAsmx86Instruction* inst);
125 bool x86InstructionIsConditionalBranch(SgAsmx86Instruction* inst);
126 bool x86InstructionIsDataTransfer(SgAsmx86Instruction* inst);
127 bool x86GetKnownBranchTarget(SgAsmx86Instruction* insn, uint64_t& addr);
128 // SgAsmx86Instruction* x86GetInstructionDestination(SgAsmx86Instruction* inst); // Returns non-fallthrough destination
129 // std::vector<SgAsmx86Instruction*> x86GetInstructionOutEdges(SgAsmx86Instruction* inst); // Returns all possible targets and fallthrough
130
131 const char* regclassToString(X86RegisterClass n);
132 const char* gprToString(X86GeneralPurposeRegister n);
133 const char* segregToString(X86SegmentRegister n);
134 const char* flagToString(X86Flag n);
135
136
137 #endif