2 * Copyright (c) 1996-2009 Barton P. Miller
4 * We provide the Paradyn Parallel Performance Tools (below
5 * described as "Paradyn") on an AS IS basis, and do not warrant its
6 * validity or performance. We reserve the right to update, modify,
7 * or discontinue this software at any time. We shall have no
8 * obligation to supply such updates or modifications or any other
9 * form of support to you.
11 * By your use of Paradyn, you understand and agree that we (or any
12 * other person or entity with proprietary rights in Paradyn) are
13 * under no obligation to provide either maintenance services,
14 * update services, notices of latent defects, or correction of
15 * defects for Paradyn.
17 * This library is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU Lesser General Public
19 * License as published by the Free Software Foundation; either
20 * version 2.1 of the License, or (at your option) any later version.
22 * This library is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * Lesser General Public License for more details.
27 * You should have received a copy of the GNU Lesser General Public
28 * License along with this library; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
36 #include "Dereference.h"
37 #include "Immediate.h"
38 #include "BinaryFunction.h"
44 using namespace Dyninst;
45 using namespace InstructionAPI;
46 using namespace Dyninst::InsnAdapter;
47 using namespace Dyninst::ParseAPI;
49 std::map<Architecture, RegisterAST::Ptr> IA_IAPI::framePtr;
50 std::map<Architecture, RegisterAST::Ptr> IA_IAPI::stackPtr;
51 std::map<Architecture, RegisterAST::Ptr> IA_IAPI::thePC;
53 void IA_IAPI::initASTs()
57 framePtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86)));
58 framePtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86_64)));
59 framePtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc32)));
60 framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64)));
64 stackPtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86)));
65 stackPtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86_64)));
66 stackPtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc32)));
67 stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64)));
71 thePC[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_x86)));
72 thePC[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_x86_64)));
73 thePC[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc32)));
74 thePC[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc64)));
78 IA_IAPI::IA_IAPI(InstructionDecoder dec_,
82 InstructionSource *isrc) :
83 InstructionAdapter(where_, o, r, isrc),
88 hascftstatus.first = false;
89 tailCall.first = false;
90 boost::tuples::tie(curInsnIter, boost::tuples::ignore) = allInsns.insert(std::make_pair(current, dec.decode()));
94 void IA_IAPI::advance()
97 parsing_printf("..... WARNING: failed to advance InstructionAdapter at 0x%lx, allInsns.size() = %d\n", current,
101 InstructionAdapter::advance();
102 current += curInsn()->size();
103 boost::tuples::tie(curInsnIter, boost::tuples::ignore) = allInsns.insert(std::make_pair(current, dec.decode()));
106 parsing_printf("......WARNING: after advance at 0x%lx, curInsn() NULL\n", current);
109 hascftstatus.first = false;
110 tailCall.first = false;
113 void IA_IAPI::retreat()
116 parsing_printf("..... WARNING: failed to retreat InstructionAdapter at 0x%lx, allInsns.size() = %d\n", current,
120 InstructionAdapter::retreat();
121 std::map<Address,Instruction::Ptr>::iterator remove = curInsnIter;
122 if(curInsnIter != allInsns.begin()) {
124 allInsns.erase(remove);
125 current = curInsnIter->first;
126 if(curInsnIter != allInsns.begin()) {
127 std::map<Address,Instruction::Ptr>::iterator pit = curInsnIter;
129 previous = curInsnIter->first;
134 parsing_printf("..... WARNING: cowardly refusal to retreat past first instruction at 0x%lx\n", current);
137 /* blind duplication -- nate */
139 hascftstatus.first = false;
140 tailCall.first = false;
145 size_t IA_IAPI::getSize() const
147 Instruction::Ptr ci = curInsn();
152 bool IA_IAPI::hasCFT() const
154 if(hascftstatus.first) return hascftstatus.second;
155 InsnCategory c = curInsn()->getCategory();
156 hascftstatus.second = false;
157 if(c == c_BranchInsn ||
160 hascftstatus.second = true;
165 hascftstatus.second = true;
167 if(isDynamicCall()) {
168 hascftstatus.second = true;
171 hascftstatus.second = true;
174 hascftstatus.first = true;
175 return hascftstatus.second;
178 bool IA_IAPI::isAbortOrInvalidInsn() const
180 entryID e = curInsn()->getOperation().getID();
183 parsing_printf("...WARNING: un-decoded instruction at 0x%x\n", current);
185 return e == e_No_Entry ||
190 bool IA_IAPI::isFrameSetupInsn() const
192 return isFrameSetupInsn(curInsn());
195 bool IA_IAPI::isDynamicCall() const
197 Instruction::Ptr ci = curInsn();
198 if(ci && (ci->getCategory() == c_CallInsn))
202 parsing_printf("... Call 0x%lx is indirect\n", current);
209 bool IA_IAPI::isAbsoluteCall() const
211 Instruction::Ptr ci = curInsn();
212 if(ci->getCategory() == c_CallInsn)
214 Expression::Ptr cft = ci->getControlFlowTarget();
215 if(cft && dyn_detail::boost::dynamic_pointer_cast<Immediate>(cft))
224 bool IA_IAPI::isReturn() const
226 return curInsn()->getCategory() == c_ReturnInsn;
228 bool IA_IAPI::isBranch() const
230 return curInsn()->getCategory() == c_BranchInsn;
232 bool IA_IAPI::isCall() const
234 return curInsn()->getCategory() == c_CallInsn;
237 bool IA_IAPI::isInterruptOrSyscall() const
239 return (isInterrupt() && isSyscall());
242 bool IA_IAPI::isSyscall() const
244 static RegisterAST::Ptr gs(new RegisterAST(x86::gs));
246 Instruction::Ptr ci = curInsn();
248 return (((ci->getOperation().getID() == e_call) &&
249 /*(curInsn()->getOperation().isRead(gs))) ||*/
250 (ci->getOperand(0).format() == "16")) ||
251 (ci->getOperation().getID() == e_syscall) ||
252 (ci->getOperation().getID() == e_int) ||
253 (ci->getOperation().getID() == power_op_sc));
257 bool IA_IAPI::isInterrupt() const
259 Instruction::Ptr ci = curInsn();
260 return ((ci->getOperation().getID() == e_int) ||
261 (ci->getOperation().getID() == e_int3));
264 void IA_IAPI::getNewEdges(
265 std::vector<std::pair< Address, EdgeTypeEnum> >& outEdges,
268 unsigned int num_insns,
269 dyn_hash_map<Address, std::string> *plt_entries) const
271 Instruction::Ptr ci = curInsn();
273 // Only call this on control flow instructions!
274 if(ci->getCategory() == c_CallInsn)
276 Address target = getCFT();
277 if(isRealCall() || isDynamicCall())
279 outEdges.push_back(std::make_pair(target, NOEDGE));
283 if(_isrc->isValidAddress(target))
287 parsing_printf("[%s:%u] call at 0x%lx simulated as "
289 FILE__,__LINE__,getAddr(),getCFT());
290 outEdges.push_back(std::make_pair(target, DIRECT));
295 outEdges.push_back(std::make_pair(getAddr() + getSize(),
299 else if(ci->getCategory() == c_BranchInsn)
302 if(ci->allowsFallThrough())
304 outEdges.push_back(std::make_pair(getCFT(),
306 outEdges.push_back(std::make_pair(getNextAddr(), COND_NOT_TAKEN));
310 else if((target = getCFT()) != 0)
313 if(_cr->findCatchBlock(getNextAddr(),catchStart))
315 outEdges.push_back(std::make_pair(catchStart, CATCH));
319 if(!isTailCall(context,num_insns))
321 if(plt_entries->find(target) == plt_entries->end())
323 outEdges.push_back(std::make_pair(target,DIRECT));
327 parsing_printf("%s[%d]: PLT tail call to %x (%s)\n",
328 FILE__, __LINE__, target,
329 (*plt_entries)[target].c_str());
330 outEdges.push_back(std::make_pair(target, NOEDGE));
331 tailCall.second = true;
336 parsing_printf("%s[%d]: tail call to %x\n",
337 FILE__, __LINE__, target);
338 outEdges.push_back(std::make_pair(target, NOEDGE));
344 parsing_printf("... indirect jump at 0x%x\n", current);
345 if( num_insns == 2 ) {
346 parsing_printf("... uninstrumentable due to 0 size\n");
349 if(isTailCall(context,num_insns)) {
350 parsing_printf("%s[%d]: indirect tail call %s at 0x%lx\n", FILE__, __LINE__,
351 ci->format().c_str(), current);
354 parsing_printf("%s[%d]: jump table candidate %s at 0x%lx\n", FILE__, __LINE__,
355 ci->format().c_str(), current);
356 parsedJumpTable = true;
357 successfullyParsedJumpTable = parseJumpTable(currBlk, outEdges);
359 if(!successfullyParsedJumpTable || outEdges.empty()) {
360 outEdges.push_back(std::make_pair((Address)-1,INDIRECT));
365 else if(ci->getCategory() == c_ReturnInsn)
367 if(ci->allowsFallThrough())
369 outEdges.push_back(std::make_pair(getNextAddr(), FALLTHROUGH));
374 fprintf(stderr, "Unhandled instruction %s\n", ci->format().c_str());
378 bool IA_IAPI::isIPRelativeBranch() const
380 // These don't exist on IA32...
381 #if !defined(arch_x86_64)
384 Instruction::Ptr ci = curInsn();
386 if(ci->getCategory() == c_BranchInsn &&
389 Expression::Ptr cft = ci->getControlFlowTarget();
390 if(cft->isUsed(thePC[_isrc->getArch()]))
392 parsing_printf("\tIP-relative indirect jump to %s at 0x%lx\n",
393 cft->format().c_str(), current);
401 Instruction::Ptr IA_IAPI::curInsn() const
403 return curInsnIter->second;
406 bool IA_IAPI::isLeave() const
408 Instruction::Ptr ci = curInsn();
409 return ci && (ci->getOperation().getID() == e_leave);
412 bool IA_IAPI::isDelaySlot() const
414 #if defined(arch_sparc)
415 assert(!"Implement delay slots on SPARC!");
420 Instruction::Ptr IA_IAPI::getInstruction()
425 bool IA_IAPI::isRealCall() const
427 if(getCFT() == getNextAddr())
429 parsing_printf("... getting PC\n");
432 if(!_isrc->isValidAddress(getCFT()))
434 parsing_printf(" isREalCall whacked by _isrc->isVAlidAddress(%lx)\n",
441 std::map<Address, bool> IA_IAPI::thunkAtTarget;
443 bool IA_IAPI::isConditional() const
445 return curInsn()->allowsFallThrough();
448 bool IA_IAPI::simulateJump() const
450 // TODO: we don't simulate jumps on x86 architectures; add logic as we need it.
454 Address IA_IAPI::getCFT() const
456 if(validCFT) return cachedCFT;
457 Expression::Ptr callTarget = curInsn()->getControlFlowTarget();
458 // FIXME: templated bind(),dammit!
459 callTarget->bind(thePC[_isrc->getArch()].get(), Result(s64, current));
460 parsing_printf("%s[%d]: binding PC %s in %s to 0x%x...", FILE__, __LINE__,
461 thePC[_isrc->getArch()]->format().c_str(), curInsn()->format().c_str(), current);
462 Result actualTarget = callTarget->eval();
463 if(actualTarget.defined)
465 cachedCFT = actualTarget.convert<Address>();
466 parsing_printf("SUCCESS (CFT=0x%x)\n", cachedCFT);
471 parsing_printf("FAIL (CFT=0x%x), callTarget exp: %s\n", cachedCFT,callTarget->format().c_str());
477 bool IA_IAPI::isRelocatable(InstrumentableLevel lvl) const
479 Instruction::Ptr ci = curInsn();
480 if(ci && (ci->getCategory() == c_CallInsn))
484 if(!_isrc->isValidAddress(getCFT()))
486 parsing_printf("... Call to 0x%lx is invalid (outside code or data)\n",
492 if(lvl == HAS_BR_INDIR)
499 InstrumentableLevel IA_IAPI::getInstLevel(Function * context, unsigned int num_insns) const
501 InstrumentableLevel ret = InstructionAdapter::getInstLevel(context, num_insns);
502 /* if(ret == HAS_BR_INDIR && isIPRelativeBranch())