Segment registers were 32-bit and should have been 16-bit.
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
2  * Copyright (c) 1996-2011 Barton P. Miller
3  * 
4  * We provide the Paradyn Parallel Performance Tools (below
5  * described as "Paradyn") on an AS IS basis, and do not warrant its
6  * validity or performance.  We reserve the right to update, modify,
7  * or discontinue this software at any time.  We shall have no
8  * obligation to supply such updates or modifications or any other
9  * form of support to you.
10  * 
11  * By your use of Paradyn, you understand and agree that we (or any
12  * other person or entity with proprietary rights in Paradyn) are
13  * under no obligation to provide either maintenance services,
14  * update services, notices of latent defects, or correction of
15  * defects for Paradyn.
16  * 
17  * This library is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU Lesser General Public
19  * License as published by the Free Software Foundation; either
20  * version 2.1 of the License, or (at your option) any later version.
21  * 
22  * This library is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
25  * Lesser General Public License for more details.
26  * 
27  * You should have received a copy of the GNU Lesser General Public
28  * License along with this library; if not, write to the Free Software
29  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
30  */
31
32 #define INSIDE_INSTRUCTION_API
33
34 #include "common/h/Types.h"
35 #include "InstructionDecoder-x86.h"
36 #include "Expression.h"
37 #include "common/h/arch-x86.h"
38 #include "Register.h"
39 #include "Dereference.h"
40 #include "Immediate.h"
41 #include "BinaryFunction.h"
42 #include "common/h/singleton_object_pool.h"
43
44 using namespace std;
45 using namespace NS_x86;
46 namespace Dyninst
47 {
48     namespace InstructionAPI
49     {
50     
51         bool readsOperand(unsigned int opsema, unsigned int i)
52         {
53             switch(opsema) {
54                 case s1R2R:
55                     return (i == 0 || i == 1);
56                 case s1R:
57                 case s1RW:
58                     return i == 0;
59                 case s1W:
60                     return false;
61                 case s1W2RW:
62                 case s1W2R:   // second operand read, first operand written (e.g. mov)
63                     return i == 1;
64                 case s1RW2R:  // two operands read, first written (e.g. add)
65                 case s1RW2RW: // e.g. xchg
66                 case s1R2RW:
67                     return i == 0 || i == 1;
68                 case s1W2R3R: // e.g. imul
69                 case s1W2RW3R: // some mul
70                 case s1W2R3RW: // (stack) push & pop
71                     return i == 1 || i == 2;
72                 case s1W2W3R: // e.g. les
73                     return i == 2;
74                 case s1RW2R3R: // shld/shrd
75                 case s1RW2RW3R: // [i]div, cmpxch8b
76                 case s1R2R3R:
77                     return i == 0 || i == 1 || i == 2;
78                     break;
79                 case sNONE:
80                 default:
81                     return false;
82             }
83       
84         }
85       
86         bool writesOperand(unsigned int opsema, unsigned int i)
87         {
88             switch(opsema) {
89                 case s1R2R:
90                 case s1R:
91                     return false;
92                 case s1RW:
93                 case s1W:
94                     case s1W2R:   // second operand read, first operand written (e.g. mov)
95                         case s1RW2R:  // two operands read, first written (e.g. add)
96                             case s1W2R3R: // e.g. imul
97                                 case s1RW2R3R: // shld/shrd
98                                     return i == 0;
99                 case s1R2RW:
100                     return i == 1;
101                 case s1W2RW:
102                     case s1RW2RW: // e.g. xchg
103                         case s1W2RW3R: // some mul
104                             case s1W2W3R: // e.g. les
105                                 case s1RW2RW3R: // [i]div, cmpxch8b
106                                     return i == 0 || i == 1;
107                                     case s1W2R3RW: // (stack) push & pop
108                                         return i == 0 || i == 2;
109                 case sNONE:
110                 default:
111                     return false;
112             }
113         }
114
115
116     
117     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
118       InstructionDecoderImpl(a),
119     locs(NULL),
120     decodedInstruction(NULL),
121     sizePrefixPresent(false)
122     {
123     }
124     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
125     {
126         if(decodedInstruction) decodedInstruction->~ia32_instruction();
127         free(decodedInstruction);
128         if(locs) locs->~ia32_locations();
129         free(locs);
130
131     }
132     static const unsigned char modrm_use_sib = 4;
133     
134     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
135     {
136         ia32_set_mode_64(is64);
137     }
138     
139       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
140     {
141         unsigned scale;
142         Register index;
143         Register base;
144         Result_Type registerType = ia32_is_mode_64() ? u32 : u64;
145
146         decode_SIB(locs->sib_byte, scale, index, base);
147
148         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
149         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
150                                     locs->rex_x))));
151         Expression::Ptr baseAST;
152         if(base == 0x05)
153         {
154             switch(locs->modrm_mod)
155             {
156                 case 0x00:
157                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
158                     break;
159                     case 0x01: {
160                         MachRegister reg;
161                         if (locs->rex_b)
162                             reg = x86_64::r13;
163                         else
164                           reg = MachRegister::getFramePointer(m_Arch);
165                         
166                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
167                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
168                                                     registerType);
169                         break;
170                     }
171                     case 0x02: {
172                         MachRegister reg;
173                         if (locs->rex_b)
174                             reg = x86_64::r13;
175                         else
176                             reg = MachRegister::getFramePointer(m_Arch);
177
178                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
179                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
180                                                     registerType);
181                         break;
182                     }
183                 case 0x03:
184                 default:
185                     assert(0);
186                     break;
187             };
188         }
189         else
190         {
191             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
192                                                                                                registerType,
193                                                                                                locs->rex_b)));
194         }
195         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
196         {
197             return baseAST;
198         }
199         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
200     }
201
202       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
203                                                                   unsigned int opType)
204     {
205         unsigned int regType = op_d;
206         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
207         if(ia32_is_mode_64())
208         {
209             regType = op_q;
210         }
211         Expression::Ptr e =
212             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
213         switch(locs->modrm_mod)
214         {
215             case 0:
216                 if(locs->modrm_rm == modrm_use_sib) {
217                     e = makeSIBExpression(b);
218                 }
219                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
220                 {
221                     assert(locs->opcode_position > -1);
222                     if(ia32_is_mode_64())
223                     {
224                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
225                                             getModRMDisplacement(b), aw);
226                     }
227                     else
228                     {
229                         e = getModRMDisplacement(b);
230                     }
231         
232                 }
233                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
234                 {
235                     e = getModRMDisplacement(b);
236                 }
237                 if(opType == op_lea)
238                 {
239                     return e;
240                 }
241                 return makeDereferenceExpression(e, makeSizeType(opType));
242                 assert(0);
243                 break;
244             case 1:
245             case 2:
246             {
247                 if(locs->modrm_rm == modrm_use_sib) {
248                     e = makeSIBExpression(b);
249                 }
250                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
251                 if(opType == op_lea)
252                 {
253                     return disp_e;
254                 }
255                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
256             }
257             assert(0);
258             break;
259             case 3:
260                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
261             default:
262                 return Expression::Ptr();
263         
264         };
265         // can't get here, but make the compiler happy...
266         assert(0);
267         return Expression::Ptr();
268     }
269
270     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
271                                                             bool isSigned)
272     {
273         switch(opType)
274         {
275             case op_b:
276                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
277                 break;
278             case op_d:
279                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
280             case op_w:
281                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
282                 break;
283             case op_q:
284                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
285                 break;
286             case op_v:
287             case op_z:
288         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
289         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
290                 if(!sizePrefixPresent)
291                 {
292                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
293                 }
294                 else
295                 {
296                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
297                 }
298         
299                 break;
300             case op_p:
301         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
302         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
303                 if(!sizePrefixPresent)
304                 {
305                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
306                 }
307                 else
308                 {
309                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
310                 }
311         
312                 break;
313             case op_a:
314             case op_dq:
315             case op_pd:
316             case op_ps:
317             case op_s:
318             case op_si:
319             case op_lea:
320             case op_allgprs:
321             case op_512:
322             case op_c:
323                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
324                 return Expression::Ptr();
325             default:
326                 assert(!"Can't happen: opType out of range");
327                 return Expression::Ptr();
328         }
329     }
330     
331     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
332     {
333         int disp_pos;
334
335         if(locs->sib_position != -1)
336         {
337             disp_pos = locs->sib_position + 1;
338         }
339         else
340         {
341             disp_pos = locs->modrm_position + 1;
342         }
343         switch(locs->modrm_mod)
344         {
345             case 1:
346                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
347                         disp_pos)))));
348                 break;
349             case 2:
350                 if(sizePrefixPresent)
351                 {
352                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
353                             disp_pos)))));
354                 }
355                 else
356                 {
357                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
358                             disp_pos)))));
359                 }
360                 break;
361             case 0:
362                 // In 16-bit mode, the word displacement is modrm r/m 6
363                 if(sizePrefixPresent)
364                 {
365                     if(locs->modrm_rm == 6)
366                     {
367                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
368                                            *((const dword_t*)(b.start + disp_pos)))));
369                     }
370                     else
371                     {
372                         assert(b.start + disp_pos + 1 <= b.end);
373                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
374                     }
375                     break;
376                 }
377                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
378                 else
379                 {
380                     if(locs->modrm_rm == 5)
381                     {
382                         assert(b.start + disp_pos + 4 <= b.end);
383                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
384                                            *((const dword_t*)(b.start + disp_pos)))));
385                     }
386                     else
387                     {
388                         assert(b.start + disp_pos + 1 <= b.end);
389                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
390                     }
391                     break;
392                 }
393             default:
394                 assert(b.start + disp_pos + 1 <= b.end);
395                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
396                 break;
397         }
398     }
399
400     enum intelRegBanks
401     {
402         b_8bitNoREX = 0,
403         b_16bit,
404         b_32bit,
405         b_segment,
406         b_64bit,
407         b_xmm,
408         b_xmmhigh,
409         b_mm,
410         b_cr,
411         b_dr,
412         b_tr,
413         b_amd64ext,
414         b_8bitWithREX,
415         b_fpstack
416     };
417     static MachRegister IntelRegTable32[][8] = {
418         {
419             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
420         },
421         {
422             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
423         },
424         {
425             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
426         },
427         {
428            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
429         },
430         {
431             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
432         },
433         {
434             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
435         },
436         {
437             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
438         },
439         {
440             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
441         },
442         {
443             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
444         },
445         {
446             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
447         },
448         {
449             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
450         },
451         {
452             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
453         },
454         {
455             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
456         },
457         {
458             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
459         }
460
461     };
462     static MachRegister IntelRegTable64[][8] = {
463         {
464             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
465         },
466         {
467             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
468         },
469         {
470             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
471         },
472         {
473             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
474         },
475         {
476             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
477         },
478         {
479             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
480         },
481         {
482             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
483         },
484         {
485             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
486         },
487         {
488             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
489         },
490         {
491             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
492         },
493         {
494             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
495         },
496         {
497             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
498         },
499         {
500             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
501         },
502         {
503             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
504         }
505
506     };
507
508   /* Uses the appropriate lookup table based on the 
509      decoder architecture */
510   class IntelRegTable_access {
511     public:
512         inline MachRegister operator()(Architecture arch,
513                                        intelRegBanks bank,
514                                        int index)
515         {
516             assert(index >= 0 && index < 8);
517     
518             if(arch == Arch_x86_64)
519                 return IntelRegTable64[bank][index];
520             else if(arch == Arch_x86)
521                 return IntelRegTable32[bank][index];
522             else
523                 assert(0);
524             return IntelRegTable32[bank][index];
525         }
526
527   };
528   static IntelRegTable_access IntelRegTable;
529
530     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
531                                         bool isExtendedReg)
532     {
533         MachRegister retVal;
534
535         if(isExtendedReg)
536         {
537             retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
538         }
539         /* Promotion to 64-bit only applies to the operand types
540            that are varible (c,v,z). Ignoring c and z because they
541            do the right thing on 32- and 64-bit code.
542         else if(locs->rex_w)
543         {
544             // AMD64 with 64-bit operands
545             retVal = IntelRegTable[b_64bit][intelReg];
546         }
547         */
548         else
549         {
550             switch(opType)
551             {
552                 case op_v:
553                     if(locs->rex_w)
554                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
555                     else
556                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
557                     break;
558                 case op_b:
559                     if (locs->rex_position == -1) {
560                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
561                     } else {
562                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
563                     }
564                     break;
565                 case op_q:
566                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
567                     break;
568                 case op_w:
569                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
570                     break;
571                 case op_f:
572                 case op_dbl:
573                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
574                     break;
575                 case op_d:
576                 case op_si:
577                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
578                     break;
579                 default:
580                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
581                     break;
582             }
583         }
584
585         if (!ia32_is_mode_64()) {
586           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
587             assert(0);
588         }
589
590         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
591     }
592     
593     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
594     {
595         switch(opType)
596         {
597             case op_b:
598             case op_c:
599                 return u8;
600             case op_d:
601             case op_ss:
602             case op_allgprs:
603             case op_si:
604                 return u32;
605             case op_w:
606             case op_a:
607                 return u16;
608             case op_q:
609             case op_sd:
610                 return u64;
611             case op_v:
612             case op_lea:
613             case op_z:
614               if(!ia32_is_mode_64() ^ sizePrefixPresent)
615                 {
616                     return u32;
617                 }
618                 else
619                 {
620                     return u16;
621                 }
622                 break;
623             case op_p:
624                 // book says operand size; arch-x86 says word + word * operand size
625                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
626                 {
627                     return u48;
628                 }
629                 else
630                 {
631                     return u32;
632                 }
633             case op_dq:
634                 return u64;
635             case op_512:
636                 return m512;
637             case op_pi:
638             case op_ps:
639             case op_pd:
640                 return dbl128;
641             case op_s:
642                 return u48;
643             case op_f:
644                 return sp_float;
645             case op_dbl:
646                 return dp_float;
647             case op_14:
648                 return m14;
649             default:
650                 assert(!"Can't happen!");
651                 return u8;
652         }
653     }
654
655
656     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
657                                                   const ia32_operand& operand,
658                                                   int & imm_index, /* immediate operand index */
659                                                   const Instruction* insn_to_complete, 
660                                                   bool isRead, bool isWritten)
661     {
662       bool isCFT = false;
663       bool isCall = false;
664       bool isConditional = false;
665       InsnCategory cat = insn_to_complete->getCategory();
666       if(cat == c_BranchInsn || cat == c_CallInsn)
667         {
668           isCFT = true;
669           if(cat == c_CallInsn)
670             {
671               isCall = true;
672             }
673         }
674       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
675         isConditional = true;
676       }
677
678       unsigned int optype = operand.optype;
679       if (sizePrefixPresent && 
680           ((optype == op_v) ||
681            (optype == op_z))) {
682         optype = op_w;
683       }
684                 switch(operand.admet)
685                 {
686                     case 0:
687                     // No operand
688                     {
689 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
690                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
691                             fprintf(stderr, "%x ", b.start[i]);
692                         }
693                         fprintf(stderr, "\n");*/
694                         assert(!"Mismatched number of operands--check tables");
695                         return false;
696                     }
697                     case am_A:
698                     {
699                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
700                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
701                         Expression::Ptr op(makeDereferenceExpression(addr, makeSizeType(optype)));
702                         insn_to_complete->addSuccessor(op, isCall, false, false, false);
703                     }
704                     break;
705                     case am_C:
706                     {
707                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
708                         insn_to_complete->appendOperand(op, isRead, isWritten);
709                     }
710                     break;
711                     case am_D:
712                     {
713                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
714                         insn_to_complete->appendOperand(op, isRead, isWritten);
715                     }
716                     break;
717                     case am_E:
718                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
719                     // mod of 0x03 specifies direct register access).
720                     case am_M:
721                     // am_R is the inverse of am_M; it should only have a mod of 3
722                     case am_R:
723                         if(isCFT)
724                         {
725                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
726                         }
727                         else
728                         {
729                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
730                         }
731                     break;
732                     case am_F:
733                     {
734                         Expression::Ptr op(makeRegisterExpression(x86::flags));
735                         insn_to_complete->appendOperand(op, isRead, isWritten);
736                     }
737                     break;
738                     case am_G:
739                     {
740                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
741                                 optype, locs->rex_r)));
742                         insn_to_complete->appendOperand(op, isRead, isWritten);
743                     }
744                     break;
745                     case am_I:
746                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
747                                                                         locs->imm_position[imm_index++]), 
748                                                         isRead, isWritten);
749                         break;
750                     case am_J:
751                     {
752                         Expression::Ptr Offset(decodeImmediate(optype, 
753                                                                b.start + locs->imm_position[imm_index++], 
754                                                                true));
755                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
756                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
757                             decodedInstruction->getSize()))));
758                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
759
760                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
761                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
762                         if (isConditional) 
763                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
764                     }
765                     break;
766                     case am_O:
767                     {
768                     // Address/offset width, which is *not* what's encoded by the optype...
769                     // The deref's width is what's actually encoded here.
770                         int pseudoOpType;
771                         switch(locs->address_size)
772                         {
773                             case 1:
774                                 pseudoOpType = op_b;
775                                 break;
776                             case 2:
777                                 pseudoOpType = op_w;
778                                 break;
779                             case 4:
780                                 pseudoOpType = op_d;
781                                 break;
782                             case 0:
783                                 // closest I can get to "will be address size by default"
784                                 pseudoOpType = op_v;
785                                 break;
786                             default:
787                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
788                                 pseudoOpType = op_b;
789                                 break;
790                         }
791
792
793                         int offset_position = locs->opcode_position;
794                         if(locs->modrm_position > offset_position && locs->modrm_operand <
795                            (int)(insn_to_complete->m_Operands.size()))
796                         {
797                             offset_position = locs->modrm_position;
798                         }
799                         if(locs->sib_position > offset_position)
800                         {
801                             offset_position = locs->sib_position;
802                         }
803                         offset_position++;
804                         insn_to_complete->appendOperand(makeDereferenceExpression(
805                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
806                                                         isRead, isWritten);
807                     }
808                     break;
809                     case am_P:
810                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
811                                 isRead, isWritten);
812                         break;
813                     case am_Q:
814         
815                         switch(locs->modrm_mod)
816                         {
817                             // direct dereference
818                             case 0x00:
819                             case 0x01:
820                             case 0x02:
821                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
822                                 break;
823                             case 0x03:
824                                 // use of actual register
825                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
826                                                                isRead, isWritten);
827                                 break;
828                             default:
829                                 assert(!"2-bit value modrm_mod out of range");
830                                 break;
831                         };
832                         break;
833                     case am_S:
834                     // Segment register in modrm reg field.
835                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
836                                 isRead, isWritten);
837                         break;
838                     case am_T:
839                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
840                         // NOTE: this only appears in deprecated opcodes
841                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
842                                                        isRead, isWritten);
843                         break;
844                     case am_V:
845                        
846                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
847                                 (locs->rex_r == 1 )? b_xmmhigh : b_xmm,locs->modrm_reg)),
848                                     isRead, isWritten);
849                         break;
850                     case am_W:
851                         switch(locs->modrm_mod)
852                         {
853                             // direct dereference
854                             case 0x00:
855                             case 0x01:
856                             case 0x02:
857                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
858                                                                isRead, isWritten);
859                                 break;
860                             case 0x03:
861                             // use of actual register
862                             {
863                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
864                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
865                                         isRead, isWritten);
866                                 break;
867                             }
868                             default:
869                                 assert(!"2-bit value modrm_mod out of range");
870                                 break;
871                         };
872                         break;
873                     case am_X:
874                     {
875                         MachRegister si_reg;
876                         if(m_Arch == Arch_x86)
877                         {
878                                 if(addrSizePrefixPresent)
879                                 {
880                                         si_reg = x86::si;
881                                 } else
882                                 {
883                                         si_reg = x86::esi;
884                                 }
885                         }
886                         else
887                         {
888                                 if(addrSizePrefixPresent)
889                                 {
890                                         si_reg = x86_64::esi;
891                                 } else
892                                 {
893                                         si_reg = x86_64::rsi;
894                                 }
895                         }
896                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
897                         Expression::Ptr si(makeRegisterExpression(si_reg));
898                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
899                                 Result(u32, 0x10))));
900                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
901                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
902                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
903                                                        isRead, isWritten);
904                     }
905                     break;
906                     case am_Y:
907                     {
908                         MachRegister di_reg;
909                         if(m_Arch == Arch_x86)
910                         {
911                                 if(addrSizePrefixPresent)
912                                 {
913                                         di_reg = x86::di;
914                                 } else
915                                 {
916                                         di_reg = x86::edi;
917                                 }
918                         }
919                         else
920                         {
921                                 if(addrSizePrefixPresent)
922                                 {
923                                         di_reg = x86_64::edi;
924                                 } else
925                                 {
926                                         di_reg = x86_64::rdi;
927                                 }
928                         }
929                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
930                         Expression::Ptr di(makeRegisterExpression(di_reg));
931                         Expression::Ptr es_segment = makeMultiplyExpression(es,
932                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
933                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
934                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
935                                                        isRead, isWritten);
936                     }
937                     break;
938                     case am_tworeghack:
939                     {
940                         if(optype == op_edxeax)
941                         {
942                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
943                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
944                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
945                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
946                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
947                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
948                             insn_to_complete->appendOperand(op, isRead, isWritten);
949                         }
950                         else if (optype == op_ecxebx)
951                         {
952                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
953                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
954                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
955                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
956                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
957                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
958                             insn_to_complete->appendOperand(op, isRead, isWritten);
959                         }
960                     }
961                     break;
962                     
963                     case am_reg:
964                     {
965                         MachRegister r(optype);
966                         r = MachRegister(r.val() & ~r.getArchitecture() | m_Arch);
967                         if(locs->rex_b && insn_to_complete->m_Operands.empty())
968                         {
969                             // FP stack registers are not affected by the rex_b bit in AM_REG.
970                             if(r.regClass() != x86::MMX)
971                             {
972                                 r = MachRegister((r.val()) | x86_64::r8.val());
973                             }
974                         }
975                         if(sizePrefixPresent)
976                         {
977                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
978                         }
979                         Expression::Ptr op(makeRegisterExpression(r));
980                         insn_to_complete->appendOperand(op, isRead, isWritten);
981                     }
982                     break;
983                 case am_stackH:
984                 case am_stackP:
985                 // handled elsewhere
986                     break;
987                 case am_allgprs:
988                 {
989                     if(m_Arch == Arch_x86)
990                     {
991                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
992                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
993                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
994                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
995                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
996                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
997                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
998                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
999                     }
1000                     else
1001                     {
1002                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1003                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1004                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1005                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1006                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1007                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1008                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1009                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1010                     }
1011                 }
1012                     break;
1013                 case am_ImplImm: {
1014                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1015                   break;
1016                 }
1017
1018                 default:
1019                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1020                         break;
1021                 };
1022                 return true;
1023             }
1024
1025     extern ia32_entry invalid;
1026     
1027     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1028     {
1029         if(decodedInstruction == NULL)
1030         {
1031             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1032             assert(decodedInstruction);
1033         }
1034         if(locs == NULL)
1035         {
1036             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1037             assert(locs);
1038         }
1039         locs = new(locs) ia32_locations; //reinit();
1040         assert(locs->sib_position == -1);
1041         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1042         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1043         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1044         if (decodedInstruction->getPrefix()->rexW()) {
1045            // as per 2.2.1.2 - rex.w overrides 66h
1046            sizePrefixPresent = false;
1047         }
1048         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1049     }
1050     
1051     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1052     {
1053         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1054         doIA32Decode(b);
1055         if(decodedInstruction->getEntry()) {
1056             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1057                                     decodedInstruction->getPrefix(), locs, m_Arch));
1058         }
1059         else
1060         {
1061                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1062                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1063                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1064                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1065                 // yell at the user.
1066             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1067                                     decodedInstruction->getPrefix(), locs, m_Arch));
1068         }
1069         b.start += decodedInstruction->getSize();
1070     }
1071     
1072       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1073     {
1074         int imm_index = 0; // handle multiple immediate operands
1075         if(!decodedInstruction) return false;
1076         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1077         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1078         
1079         for(unsigned i = 0; i < 3; i++)
1080         {
1081             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1082                decodedInstruction->getEntry()->operands[i].optype == 0)
1083                 return true;
1084             if(!decodeOneOperand(b,
1085                                  decodedInstruction->getEntry()->operands[i], 
1086                                  imm_index, 
1087                                  insn_to_complete, 
1088                                  readsOperand(opsema, i),
1089                                  writesOperand(opsema, i)))
1090             {
1091                 return false;
1092             }
1093         }
1094     
1095         return true;
1096     }
1097
1098     
1099       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1100     {
1101         return InstructionDecoderImpl::decode(b);
1102     }
1103     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1104     {
1105       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1106       //insn_to_complete->m_Operands.reserve(4);
1107       doIA32Decode(b);        
1108       decodeOperands(insn_to_complete);
1109     }
1110     
1111 };
1112 };
1113