Merge branch 'master' into patchapi_snippet
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
2  * Copyright (c) 1996-2011 Barton P. Miller
3  * 
4  * We provide the Paradyn Parallel Performance Tools (below
5  * described as "Paradyn") on an AS IS basis, and do not warrant its
6  * validity or performance.  We reserve the right to update, modify,
7  * or discontinue this software at any time.  We shall have no
8  * obligation to supply such updates or modifications or any other
9  * form of support to you.
10  * 
11  * By your use of Paradyn, you understand and agree that we (or any
12  * other person or entity with proprietary rights in Paradyn) are
13  * under no obligation to provide either maintenance services,
14  * update services, notices of latent defects, or correction of
15  * defects for Paradyn.
16  * 
17  * This library is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU Lesser General Public
19  * License as published by the Free Software Foundation; either
20  * version 2.1 of the License, or (at your option) any later version.
21  * 
22  * This library is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
25  * Lesser General Public License for more details.
26  * 
27  * You should have received a copy of the GNU Lesser General Public
28  * License along with this library; if not, write to the Free Software
29  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
30  */
31
32 #define INSIDE_INSTRUCTION_API
33
34 #include "common/h/Types.h"
35 #include "InstructionDecoder-x86.h"
36 #include "Expression.h"
37 #include "common/h/arch-x86.h"
38 #include "Register.h"
39 #include "Dereference.h"
40 #include "Immediate.h" 
41 #include "BinaryFunction.h"
42 #include "common/h/singleton_object_pool.h"
43
44 using namespace std;
45 using namespace NS_x86;
46 namespace Dyninst
47 {
48     namespace InstructionAPI
49     {
50     
51         bool readsOperand(unsigned int opsema, unsigned int i)
52         {
53             switch(opsema) {
54                 case s1R2R:
55                     return (i == 0 || i == 1);
56                 case s1R:
57                 case s1RW:
58                     return i == 0;
59                 case s1W:
60                     return false;
61                 case s1W2RW:
62                 case s1W2R:   // second operand read, first operand written (e.g. mov)
63                     return i == 1;
64                 case s1RW2R:  // two operands read, first written (e.g. add)
65                 case s1RW2RW: // e.g. xchg
66                 case s1R2RW:
67                     return i == 0 || i == 1;
68                 case s1W2R3R: // e.g. imul
69                 case s1W2RW3R: // some mul
70                 case s1W2R3RW: // (stack) push & pop
71                     return i == 1 || i == 2;
72                 case s1W2W3R: // e.g. les
73                     return i == 2;
74                 case s1RW2R3R: // shld/shrd
75                 case s1RW2RW3R: // [i]div, cmpxch8b
76                 case s1R2R3R:
77                     return i == 0 || i == 1 || i == 2;
78                     break;
79                 case sNONE:
80                 default:
81                     return false;
82             }
83       
84         }
85       
86         bool writesOperand(unsigned int opsema, unsigned int i)
87         {
88             switch(opsema) {
89                 case s1R2R:
90                 case s1R:
91                     return false;
92                 case s1RW:
93                 case s1W:
94                     case s1W2R:   // second operand read, first operand written (e.g. mov)
95                         case s1RW2R:  // two operands read, first written (e.g. add)
96                             case s1W2R3R: // e.g. imul
97                                 case s1RW2R3R: // shld/shrd
98                                     return i == 0;
99                 case s1R2RW:
100                     return i == 1;
101                 case s1W2RW:
102                     case s1RW2RW: // e.g. xchg
103                         case s1W2RW3R: // some mul
104                             case s1W2W3R: // e.g. les
105                                 case s1RW2RW3R: // [i]div, cmpxch8b
106                                     return i == 0 || i == 1;
107                                     case s1W2R3RW: // (stack) push & pop
108                                         return i == 0 || i == 2;
109                 case sNONE:
110                 default:
111                     return false;
112             }
113         }
114
115
116     
117     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
118       InstructionDecoderImpl(a),
119     locs(NULL),
120     decodedInstruction(NULL),
121     sizePrefixPresent(false)
122     {
123     }
124     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
125     {
126         if(decodedInstruction) decodedInstruction->~ia32_instruction();
127         free(decodedInstruction);
128         if(locs) locs->~ia32_locations();
129         free(locs);
130
131     }
132     static const unsigned char modrm_use_sib = 4;
133     
134     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
135     {
136         ia32_set_mode_64(is64);
137     }
138     
139       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
140     {
141         unsigned scale;
142         Register index;
143         Register base;
144         Result_Type registerType = ia32_is_mode_64() ? u32 : u64;
145
146         decode_SIB(locs->sib_byte, scale, index, base);
147
148         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
149         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
150                                     locs->rex_x))));
151         Expression::Ptr baseAST;
152         if(base == 0x05)
153         {
154             switch(locs->modrm_mod)
155             {
156                 case 0x00:
157                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
158                     break;
159                     case 0x01: {
160                         MachRegister reg;
161                         if (locs->rex_b)
162                             reg = x86_64::r13;
163                         else
164                           reg = MachRegister::getFramePointer(m_Arch);
165                         
166                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
167                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
168                                                     registerType);
169                         break;
170                     }
171                     case 0x02: {
172                         MachRegister reg;
173                         if (locs->rex_b)
174                             reg = x86_64::r13;
175                         else
176                             reg = MachRegister::getFramePointer(m_Arch);
177
178                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
179                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
180                                                     registerType);
181                         break;
182                     }
183                 case 0x03:
184                 default:
185                     assert(0);
186                     break;
187             };
188         }
189         else
190         {
191             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
192                                                                                                registerType,
193                                                                                                locs->rex_b)));
194         }
195         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
196         {
197             return baseAST;
198         }
199         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
200     }
201
202       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
203                                                                   unsigned int opType)
204     {
205        unsigned int regType = op_d;
206         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
207         if(ia32_is_mode_64())
208         {
209             regType = op_q;
210         }
211         Expression::Ptr e =
212             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
213         switch(locs->modrm_mod)
214         {
215             case 0:
216                 if(locs->modrm_rm == modrm_use_sib) {
217                     e = makeSIBExpression(b);
218                 }
219                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
220                 {
221                     assert(locs->opcode_position > -1);
222                     if(ia32_is_mode_64())
223                     {
224                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
225                                             getModRMDisplacement(b), aw);
226                     }
227                     else
228                     {
229                         e = getModRMDisplacement(b);
230                     }
231         
232                 }
233                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
234                 {
235                     e = getModRMDisplacement(b);
236                 }
237                 if(opType == op_lea)
238                 {
239                     return e;
240                 }
241                 return makeDereferenceExpression(e, makeSizeType(opType));
242                 assert(0);
243                 break;
244             case 1:
245             case 2:
246             {
247                 if(locs->modrm_rm == modrm_use_sib) {
248                     e = makeSIBExpression(b);
249                 }
250                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
251                 if(opType == op_lea)
252                 {
253                     return disp_e;
254                 }
255                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
256             }
257             assert(0);
258             break;
259             case 3:
260                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
261             default:
262                 return Expression::Ptr();
263         
264         };
265         // can't get here, but make the compiler happy...
266         assert(0);
267         return Expression::Ptr();
268     }
269
270     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
271                                                             bool isSigned)
272     {
273         switch(opType)
274         {
275             case op_b:
276                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
277                 break;
278             case op_d:
279                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
280             case op_w:
281                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
282                 break;
283             case op_q:
284                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
285                 break;
286             case op_v:
287             case op_z:
288         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
289         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
290                 if(!sizePrefixPresent)
291                 {
292                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
293                 }
294                 else
295                 {
296                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
297                 }
298         
299                 break;
300             case op_p:
301         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
302         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
303                 if(!sizePrefixPresent)
304                 {
305                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
306                 }
307                 else
308                 {
309                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
310                 }
311         
312                 break;
313             case op_a:
314             case op_dq:
315             case op_pd:
316             case op_ps:
317             case op_s:
318             case op_si:
319             case op_lea:
320             case op_allgprs:
321             case op_512:
322             case op_c:
323                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
324                 return Expression::Ptr();
325             default:
326                 assert(!"Can't happen: opType out of range");
327                 return Expression::Ptr();
328         }
329     }
330     
331     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
332     {
333         int disp_pos;
334
335         if(locs->sib_position != -1)
336         {
337             disp_pos = locs->sib_position + 1;
338         }
339         else
340         {
341             disp_pos = locs->modrm_position + 1;
342         }
343         switch(locs->modrm_mod)
344         {
345             case 1:
346                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
347                         disp_pos)))));
348                 break;
349             case 2:
350                 if(sizePrefixPresent)
351                 {
352                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
353                             disp_pos)))));
354                 }
355                 else
356                 {
357                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
358                             disp_pos)))));
359                 }
360                 break;
361             case 0:
362                 // In 16-bit mode, the word displacement is modrm r/m 6
363                 if(sizePrefixPresent)
364                 {
365                     if(locs->modrm_rm == 6)
366                     {
367                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
368                                            *((const dword_t*)(b.start + disp_pos)))));
369                     }
370                     // TODO FIXME; this was decoding wrong, but I'm not sure
371                     // why...
372                     else if (locs->modrm_rm == 5) {
373                         assert(b.start + disp_pos + 4 <= b.end);
374                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
375                                            *((const dword_t*)(b.start + disp_pos)))));
376                     } else {
377                         assert(b.start + disp_pos + 1 <= b.end);
378                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
379                     }
380                     break;
381                 }
382                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
383                 else
384                 {
385                     if(locs->modrm_rm == 5)
386                     {
387                         assert(b.start + disp_pos + 4 <= b.end);
388                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
389                                            *((const dword_t*)(b.start + disp_pos)))));
390                     }
391                     else
392                     {
393                         assert(b.start + disp_pos + 1 <= b.end);
394                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
395                     }
396                     break;
397                 }
398             default:
399                 assert(b.start + disp_pos + 1 <= b.end);
400                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
401                 break;
402         }
403     }
404
405     enum intelRegBanks
406     {
407         b_8bitNoREX = 0,
408         b_16bit,
409         b_32bit,
410         b_segment,
411         b_64bit,
412         b_xmm,
413         b_xmmhigh,
414         b_mm,
415         b_cr,
416         b_dr,
417         b_tr,
418         b_amd64ext,
419         b_8bitWithREX,
420         b_fpstack,
421         amd64_ext_8,
422         amd64_ext_16,
423         amd64_ext_32
424     };
425     static MachRegister IntelRegTable32[][8] = {
426         {
427             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
428         },
429         {
430             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
431         },
432         {
433             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
434         },
435         {
436            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
437         },
438         {
439             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
440         },
441         {
442             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
443         },
444         {
445             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
446         },
447         {
448             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
449         },
450         {
451             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
452         },
453         {
454             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
455         },
456         {
457             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
458         },
459         {
460             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
461         },
462         {
463             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
464         },
465         {
466             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
467         }
468
469     };
470     static MachRegister IntelRegTable64[][8] = {
471         {
472             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
473         },
474         {
475             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
476         },
477         {
478             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
479         },
480         {
481             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
482         },
483         {
484             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
485         },
486         {
487             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
488         },
489         {
490             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
491         },
492         {
493             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
494         },
495         {
496             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
497         },
498         {
499             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
500         },
501         {
502             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
503         },
504         {
505             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
506         },
507         {
508             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
509         },
510         {
511             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
512         },
513         {
514             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
515         },
516         {
517             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
518         },
519         {
520             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
521         }
522
523     };
524
525   /* Uses the appropriate lookup table based on the 
526      decoder architecture */
527   class IntelRegTable_access {
528     public:
529         inline MachRegister operator()(Architecture arch,
530                                        intelRegBanks bank,
531                                        int index)
532         {
533             assert(index >= 0 && index < 8);
534     
535             if(arch == Arch_x86_64)
536                 return IntelRegTable64[bank][index];
537             else if(arch == Arch_x86)
538                 return IntelRegTable32[bank][index];
539             else
540                 assert(0);
541             return IntelRegTable32[bank][index];
542         }
543
544   };
545   static IntelRegTable_access IntelRegTable;
546
547     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
548                                         bool isExtendedReg)
549     {
550         MachRegister retVal;
551
552         if(isExtendedReg)
553         {
554             switch(opType)
555             {
556                 case op_q:  
557                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
558                     break;
559                 case op_d:
560                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
561                     break;
562                 case op_w:
563                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
564                     break;
565                 case op_b:
566                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
567                     break;
568                 case op_v:
569                     if (locs->rex_w)
570                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
571                     else if (!sizePrefixPresent)
572                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
573                     else
574                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
575                     break;      
576                 case op_p:
577                 case op_z:
578                     if (!sizePrefixPresent)
579                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
580                     else
581                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
582                     break;
583                 default:
584                     fprintf(stderr, "%d\n", opType);
585                     fprintf(stderr, "%s\n",  decodedInstruction->getEntry()->name(locs));
586                     assert(0 && "opType=" && opType);
587             }
588         }
589         /* Promotion to 64-bit only applies to the operand types
590            that are varible (c,v,z). Ignoring c and z because they
591            do the right thing on 32- and 64-bit code.
592         else if(locs->rex_w)
593         {
594             // AMD64 with 64-bit operands
595             retVal = IntelRegTable[b_64bit][intelReg];
596         }
597         */
598         else
599         {
600             switch(opType)
601             {
602                 case op_v:
603                     if(locs->rex_w)
604                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
605                     else
606                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
607                     break;
608                 case op_b:
609                     if (locs->rex_position == -1) {
610                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
611                     } else {
612                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
613                     }
614                     break;
615                 case op_q:
616                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
617                     break;
618                 case op_w:
619                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
620                     break;
621                 case op_f:
622                 case op_dbl:
623                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
624                     break;
625                 case op_d:
626                 case op_si:
627                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
628                     break;
629                 default:
630                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
631                     break;
632             }
633         }
634
635         if (!ia32_is_mode_64()) {
636           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
637             assert(0);
638         }
639
640         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
641     }
642     
643     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
644     {
645         switch(opType)
646         {
647             case op_b:
648             case op_c:
649                 return u8;
650             case op_d:
651             case op_ss:
652             case op_allgprs:
653             case op_si:
654                 return u32;
655             case op_w:
656             case op_a:
657                 return u16;
658             case op_q:
659             case op_sd:
660                 return u64;
661             case op_v:
662             case op_lea:
663             case op_z:
664               if(!ia32_is_mode_64() ^ sizePrefixPresent)
665                 {
666                     return u32;
667                 }
668                 else
669                 {
670                     return u16;
671                 }
672                 break;
673             case op_p:
674                 // book says operand size; arch-x86 says word + word * operand size
675                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
676                 {
677                     return u48;
678                 }
679                 else
680                 {
681                     return u32;
682                 }
683             case op_dq:
684                 return u64;
685             case op_512:
686                 return m512;
687             case op_pi:
688             case op_ps:
689             case op_pd:
690                 return dbl128;
691             case op_s:
692                 return u48;
693             case op_f:
694                 return sp_float;
695             case op_dbl:
696                 return dp_float;
697             case op_14:
698                 return m14;
699             default:
700                 assert(!"Can't happen!");
701                 return u8;
702         }
703     }
704
705
706     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
707                                                   const ia32_operand& operand,
708                                                   int & imm_index, /* immediate operand index */
709                                                   const Instruction* insn_to_complete, 
710                                                   bool isRead, bool isWritten)
711     {
712        bool isCFT = false;
713       bool isCall = false;
714       bool isConditional = false;
715       InsnCategory cat = insn_to_complete->getCategory();
716       if(cat == c_BranchInsn || cat == c_CallInsn)
717         {
718           isCFT = true;
719           if(cat == c_CallInsn)
720             {
721               isCall = true;
722             }
723         }
724       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
725         isConditional = true;
726       }
727
728       unsigned int optype = operand.optype;
729       if (sizePrefixPresent && 
730           ((optype == op_v) ||
731            (optype == op_z))) {
732         optype = op_w;
733       }
734                 switch(operand.admet)
735                 {
736                     case 0:
737                     // No operand
738                     {
739 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
740                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
741                             fprintf(stderr, "%x ", b.start[i]);
742                         }
743                         fprintf(stderr, "\n");*/
744                         assert(!"Mismatched number of operands--check tables");
745                         return false;
746                     }
747                     case am_A:
748                     {
749                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
750                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
751                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
752                     }
753                     break;
754                     case am_C:
755                     {
756                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
757                         insn_to_complete->appendOperand(op, isRead, isWritten);
758                     }
759                     break;
760                     case am_D:
761                     {
762                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
763                         insn_to_complete->appendOperand(op, isRead, isWritten);
764                     }
765                     break;
766                     case am_E:
767                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
768                     // mod of 0x03 specifies direct register access).
769                     case am_M:
770                     // am_R is the inverse of am_M; it should only have a mod of 3
771                     case am_R:
772                         if(isCFT)
773                         {
774                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
775                         }
776                         else
777                         {
778                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
779                         }
780                     break;
781                     case am_F:
782                     {
783                         Expression::Ptr op(makeRegisterExpression(x86::flags));
784                         insn_to_complete->appendOperand(op, isRead, isWritten);
785                     }
786                     break;
787                     case am_G:
788                     {
789                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
790                                 optype, locs->rex_r)));
791                         insn_to_complete->appendOperand(op, isRead, isWritten);
792                     }
793                     break;
794                     case am_I:
795                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
796                                                                         locs->imm_position[imm_index++]), 
797                                                         isRead, isWritten);
798                         break;
799                     case am_J:
800                     {
801                         Expression::Ptr Offset(decodeImmediate(optype, 
802                                                                b.start + locs->imm_position[imm_index++], 
803                                                                true));
804                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
805                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
806                             decodedInstruction->getSize()))));
807                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
808
809                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
810                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
811                         if (isConditional) 
812                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
813                     }
814                     break;
815                     case am_O:
816                     {
817                     // Address/offset width, which is *not* what's encoded by the optype...
818                     // The deref's width is what's actually encoded here.
819                         int pseudoOpType;
820                         switch(locs->address_size)
821                         {
822                             case 1:
823                                 pseudoOpType = op_b;
824                                 break;
825                             case 2:
826                                 pseudoOpType = op_w;
827                                 break;
828                             case 4:
829                                 pseudoOpType = op_d;
830                                 break;
831                             case 0:
832                                 // closest I can get to "will be address size by default"
833                                 pseudoOpType = op_v;
834                                 break;
835                             default:
836                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
837                                 pseudoOpType = op_b;
838                                 break;
839                         }
840
841
842                         int offset_position = locs->opcode_position;
843                         if(locs->modrm_position > offset_position && locs->modrm_operand <
844                            (int)(insn_to_complete->m_Operands.size()))
845                         {
846                             offset_position = locs->modrm_position;
847                         }
848                         if(locs->sib_position > offset_position)
849                         {
850                             offset_position = locs->sib_position;
851                         }
852                         offset_position++;
853                         insn_to_complete->appendOperand(makeDereferenceExpression(
854                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
855                                                         isRead, isWritten);
856                     }
857                     break;
858                     case am_P:
859                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
860                                 isRead, isWritten);
861                         break;
862                     case am_Q:
863         
864                         switch(locs->modrm_mod)
865                         {
866                             // direct dereference
867                             case 0x00:
868                             case 0x01:
869                             case 0x02:
870                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
871                                 break;
872                             case 0x03:
873                                 // use of actual register
874                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
875                                                                isRead, isWritten);
876                                 break;
877                             default:
878                                 assert(!"2-bit value modrm_mod out of range");
879                                 break;
880                         };
881                         break;
882                     case am_S:
883                     // Segment register in modrm reg field.
884                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
885                                 isRead, isWritten);
886                         break;
887                     case am_T:
888                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
889                         // NOTE: this only appears in deprecated opcodes
890                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
891                                                        isRead, isWritten);
892                         break;
893                     case am_V:
894                        
895                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
896                                 (locs->rex_r == 1 )? b_xmmhigh : b_xmm,locs->modrm_reg)),
897                                     isRead, isWritten);
898                         break;
899                     case am_W:
900                         switch(locs->modrm_mod)
901                         {
902                             // direct dereference
903                             case 0x00:
904                             case 0x01:
905                             case 0x02:
906                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
907                                                                isRead, isWritten);
908                                 break;
909                             case 0x03:
910                             // use of actual register
911                             {
912                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
913                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
914                                         isRead, isWritten);
915                                 break;
916                             }
917                             default:
918                                 assert(!"2-bit value modrm_mod out of range");
919                                 break;
920                         };
921                         break;
922                     case am_X:
923                     {
924                         MachRegister si_reg;
925                         if(m_Arch == Arch_x86)
926                         {
927                                 if(addrSizePrefixPresent)
928                                 {
929                                         si_reg = x86::si;
930                                 } else
931                                 {
932                                         si_reg = x86::esi;
933                                 }
934                         }
935                         else
936                         {
937                                 if(addrSizePrefixPresent)
938                                 {
939                                         si_reg = x86_64::esi;
940                                 } else
941                                 {
942                                         si_reg = x86_64::rsi;
943                                 }
944                         }
945                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
946                         Expression::Ptr si(makeRegisterExpression(si_reg));
947                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
948                                 Result(u32, 0x10))));
949                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
950                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
951                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
952                                                        isRead, isWritten);
953                     }
954                     break;
955                     case am_Y:
956                     {
957                         MachRegister di_reg;
958                         if(m_Arch == Arch_x86)
959                         {
960                                 if(addrSizePrefixPresent)
961                                 {
962                                         di_reg = x86::di;
963                                 } else
964                                 {
965                                         di_reg = x86::edi;
966                                 }
967                         }
968                         else
969                         {
970                                 if(addrSizePrefixPresent)
971                                 {
972                                         di_reg = x86_64::edi;
973                                 } else
974                                 {
975                                         di_reg = x86_64::rdi;
976                                 }
977                         }
978                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
979                         Expression::Ptr di(makeRegisterExpression(di_reg));
980                         Expression::Ptr es_segment = makeMultiplyExpression(es,
981                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
982                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
983                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
984                                                        isRead, isWritten);
985                     }
986                     break;
987                     case am_tworeghack:
988                     {
989                         if(optype == op_edxeax)
990                         {
991                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
992                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
993                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
994                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
995                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
996                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
997                             insn_to_complete->appendOperand(op, isRead, isWritten);
998                         }
999                         else if (optype == op_ecxebx)
1000                         {
1001                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1002                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1003                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1004                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1005                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1006                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1007                             insn_to_complete->appendOperand(op, isRead, isWritten);
1008                         }
1009                     }
1010                     break;
1011                     
1012                     case am_reg:
1013                     {
1014                         MachRegister r(optype);
1015                         r = MachRegister(r.val() & ~r.getArchitecture() | m_Arch);
1016                         entryID entryid = decodedInstruction->getEntry()->getID(locs);
1017                         if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1018                             (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1019                         {
1020                             // FP stack registers are not affected by the rex_b bit in AM_REG.
1021                            if(r.regClass() != (unsigned) x86::MMX)
1022                             {
1023                                 r = MachRegister((r.val()) | x86_64::r8.val());
1024                             }
1025                         }
1026                         if(sizePrefixPresent)
1027                         {
1028                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1029                         }
1030                         Expression::Ptr op(makeRegisterExpression(r));
1031                         insn_to_complete->appendOperand(op, isRead, isWritten);
1032                     }
1033                     break;
1034                 case am_stackH:
1035                 case am_stackP:
1036                 // handled elsewhere
1037                     break;
1038                 case am_allgprs:
1039                 {
1040                     if(m_Arch == Arch_x86)
1041                     {
1042                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1043                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1044                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1045                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1046                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1047                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1048                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1049                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1050                     }
1051                     else
1052                     {
1053                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1054                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1055                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1056                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1057                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1058                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1059                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1060                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1061                     }
1062                 }
1063                     break;
1064                 case am_ImplImm: {
1065                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1066                   break;
1067                 }
1068
1069                 default:
1070                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1071                         break;
1072                 };
1073                 return true;
1074             }
1075
1076     extern ia32_entry invalid;
1077     
1078     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1079     {
1080         if(decodedInstruction == NULL)
1081         {
1082             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1083             assert(decodedInstruction);
1084         }
1085         if(locs == NULL)
1086         {
1087             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1088             assert(locs);
1089         }
1090         locs = new(locs) ia32_locations; //reinit();
1091         assert(locs->sib_position == -1);
1092         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1093         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1094         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1095         if (decodedInstruction->getPrefix()->rexW()) {
1096            // as per 2.2.1.2 - rex.w overrides 66h
1097            sizePrefixPresent = false;
1098         }
1099         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1100     }
1101     
1102     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1103     {
1104         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1105         doIA32Decode(b);
1106         if(decodedInstruction->getEntry()) {
1107             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1108                                     decodedInstruction->getPrefix(), locs, m_Arch));
1109             
1110         }
1111         else
1112         {
1113                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1114                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1115                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1116                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1117                 // yell at the user.
1118             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1119                                     decodedInstruction->getPrefix(), locs, m_Arch));
1120         }
1121         b.start += decodedInstruction->getSize();
1122     }
1123     
1124       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1125     {
1126        int imm_index = 0; // handle multiple immediate operands
1127         if(!decodedInstruction) return false;
1128         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1129         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1130
1131         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1132             decodedInstruction->getEntry()->getID() == e_ret_far) {
1133            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1134                                                                 ia32_is_mode_64() ? u64 : u32);
1135            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1136         }
1137
1138         for(unsigned i = 0; i < 3; i++)
1139         {
1140             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1141                decodedInstruction->getEntry()->operands[i].optype == 0)
1142                 return true;
1143             if(!decodeOneOperand(b,
1144                                  decodedInstruction->getEntry()->operands[i], 
1145                                  imm_index, 
1146                                  insn_to_complete, 
1147                                  readsOperand(opsema, i),
1148                                  writesOperand(opsema, i)))
1149             {
1150                 return false;
1151             }
1152         }
1153     
1154         return true;
1155     }
1156
1157     
1158       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1159     {
1160         return InstructionDecoderImpl::decode(b);
1161     }
1162     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1163     {
1164       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1165       //insn_to_complete->m_Operands.reserve(4);
1166       doIA32Decode(b);        
1167       decodeOperands(insn_to_complete);
1168     }
1169     
1170 };
1171 };
1172