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[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
2 * Copyright (c) 1996-2009 Barton P. Miller
3 *
4 * We provide the Paradyn Parallel Performance Tools (below
5 * described as "Paradyn") on an AS IS basis, and do not warrant its
6 * validity or performance.  We reserve the right to update, modify,
7 * or discontinue this software at any time.  We shall have no
8 * obligation to supply such updates or modifications or any other
9 * form of support to you.
10 *
11 * By your use of Paradyn, you understand and agree that we (or any
12 * other person or entity with proprietary rights in Paradyn) are
13 * under no obligation to provide either maintenance services,
14 * update services, notices of latent defects, or correction of
15 * defects for Paradyn.
16 *
17 * This library is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU Lesser General Public
19 * License as published by the Free Software Foundation; either
20 * version 2.1 of the License, or (at your option) any later version.
21 *
22 * This library is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
25 * Lesser General Public License for more details.
26 *
27 * You should have received a copy of the GNU Lesser General Public
28 * License along with this library; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32 #define INSIDE_INSTRUCTION_API
33
34 #include "common/h/Types.h"
35 #include "InstructionDecoder-x86.h"
36 #include "Expression.h"
37 #include "common/h/arch-x86.h"
38 #include "Register.h"
39 #include "Dereference.h"
40 #include "Immediate.h"
41 #include "BinaryFunction.h"
42 #include "common/h/singleton_object_pool.h"
43
44 using namespace std;
45 using namespace NS_x86;
46 namespace Dyninst
47 {
48     namespace InstructionAPI
49     {
50     
51         bool readsOperand(unsigned int opsema, unsigned int i)
52         {
53             switch(opsema) {
54                 case s1R2R:
55                     return (i == 0 || i == 1);
56                 case s1R:
57                 case s1RW:
58                     return i == 0;
59                 case s1W:
60                     return false;
61                 case s1W2RW:
62                 case s1W2R:   // second operand read, first operand written (e.g. mov)
63                     return i == 1;
64                 case s1RW2R:  // two operands read, first written (e.g. add)
65                 case s1RW2RW: // e.g. xchg
66                 case s1R2RW:
67                     return i == 0 || i == 1;
68                 case s1W2R3R: // e.g. imul
69                 case s1W2RW3R: // some mul
70                 case s1W2R3RW: // (stack) push & pop
71                     return i == 1 || i == 2;
72                 case s1W2W3R: // e.g. les
73                     return i == 2;
74                 case s1RW2R3R: // shld/shrd
75                 case s1RW2RW3R: // [i]div, cmpxch8b
76                 case s1R2R3R:
77                     return i == 0 || i == 1 || i == 2;
78                     break;
79                 case sNONE:
80                 default:
81                     return false;
82             }
83       
84         }
85       
86         bool writesOperand(unsigned int opsema, unsigned int i)
87         {
88             switch(opsema) {
89                 case s1R2R:
90                 case s1R:
91                     return false;
92                 case s1RW:
93                 case s1W:
94                     case s1W2R:   // second operand read, first operand written (e.g. mov)
95                         case s1RW2R:  // two operands read, first written (e.g. add)
96                             case s1W2R3R: // e.g. imul
97                                 case s1RW2R3R: // shld/shrd
98                                     return i == 0;
99                 case s1R2RW:
100                     return i == 1;
101                 case s1W2RW:
102                     case s1RW2RW: // e.g. xchg
103                         case s1W2RW3R: // some mul
104                             case s1W2W3R: // e.g. les
105                                 case s1RW2RW3R: // [i]div, cmpxch8b
106                                     return i == 0 || i == 1;
107                                     case s1W2R3RW: // (stack) push & pop
108                                         return i == 0 || i == 2;
109                 case sNONE:
110                 default:
111                     return false;
112             }
113         }
114
115
116     
117     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
118       InstructionDecoderImpl(a),
119     locs(NULL),
120     decodedInstruction(NULL),
121     is32BitMode(true),
122     sizePrefixPresent(false)
123     {
124     }
125     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
126     {
127         if(decodedInstruction) decodedInstruction->~ia32_instruction();
128         free(decodedInstruction);
129         if(locs) locs->~ia32_locations();
130         free(locs);
131
132     }
133     static const unsigned char modrm_use_sib = 4;
134     
135     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
136     {
137         ia32_set_mode_64(is64);
138     }
139     
140       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
141     {
142         unsigned scale;
143         Register index;
144         Register base;
145         Result_Type registerType = ia32_is_mode_64() ? u32 : u64;
146
147         decode_SIB(locs->sib_byte, scale, index, base);
148
149         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
150         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
151                                     locs->rex_x))));
152         Expression::Ptr baseAST;
153         if(base == 0x05)
154         {
155             switch(locs->modrm_mod)
156             {
157                 case 0x00:
158                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
159                     break;
160                     case 0x01: {
161                         MachRegister reg;
162                         if (locs->rex_b)
163                             reg = x86_64::r13;
164                         else
165                           reg = MachRegister::getFramePointer(m_Arch);
166                         
167                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
168                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
169                                                     registerType);
170                         break;
171                     }
172                     case 0x02: {
173                         MachRegister reg;
174                         if (locs->rex_b)
175                             reg = x86_64::r13;
176                         else
177                             reg = MachRegister::getFramePointer(m_Arch);
178
179                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
180                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
181                                                     registerType);
182                         break;
183                     }
184                 case 0x03:
185                 default:
186                     assert(0);
187                     break;
188             };
189         }
190         else
191         {
192             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
193                                                                                                registerType,
194                                                                                                locs->rex_b)));
195         }
196         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
197         {
198             return baseAST;
199         }
200         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
201     }
202
203       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
204                                                                   unsigned int opType)
205     {
206         unsigned int regType = op_d;
207         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
208         if(ia32_is_mode_64())
209         {
210             regType = op_q;
211         }
212         Expression::Ptr e =
213             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
214         switch(locs->modrm_mod)
215         {
216             case 0:
217                 if(locs->modrm_rm == modrm_use_sib) {
218                     e = makeSIBExpression(b);
219                 }
220                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
221                 {
222                     assert(locs->opcode_position > -1);
223                     if(ia32_is_mode_64())
224                     {
225                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
226                                             getModRMDisplacement(b), aw);
227                     }
228                     else
229                     {
230                         e = getModRMDisplacement(b);
231                     }
232         
233                 }
234                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
235                 {
236                     e = getModRMDisplacement(b);
237                 }
238                 if(opType == op_lea)
239                 {
240                     return e;
241                 }
242                 return makeDereferenceExpression(e, makeSizeType(opType));
243                 assert(0);
244                 break;
245             case 1:
246             case 2:
247             {
248                 if(locs->modrm_rm == modrm_use_sib) {
249                     e = makeSIBExpression(b);
250                 }
251                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
252                 if(opType == op_lea)
253                 {
254                     return disp_e;
255                 }
256                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
257             }
258             assert(0);
259             break;
260             case 3:
261                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
262             default:
263                 return Expression::Ptr();
264         
265         };
266         // can't get here, but make the compiler happy...
267         assert(0);
268         return Expression::Ptr();
269     }
270
271     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
272                                                             bool isSigned)
273     {
274         switch(opType)
275         {
276             case op_b:
277                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
278                 break;
279             case op_d:
280                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
281             case op_w:
282                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
283                 break;
284             case op_q:
285                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
286                 break;
287             case op_v:
288             case op_z:
289         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
290         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
291                 if(!sizePrefixPresent)
292                 {
293                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
294                 }
295                 else
296                 {
297                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
298                 }
299         
300                 break;
301             case op_p:
302         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
303         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
304                 if(!sizePrefixPresent)
305                 {
306                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
307                 }
308                 else
309                 {
310                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
311                 }
312         
313                 break;
314             case op_a:
315             case op_dq:
316             case op_pd:
317             case op_ps:
318             case op_s:
319             case op_si:
320             case op_lea:
321             case op_allgprs:
322             case op_512:
323             case op_c:
324                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
325                 return Expression::Ptr();
326             default:
327                 assert(!"Can't happen: opType out of range");
328                 return Expression::Ptr();
329         }
330     }
331     
332     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
333     {
334         int disp_pos;
335
336         if(locs->sib_position != -1)
337         {
338             disp_pos = locs->sib_position + 1;
339         }
340         else
341         {
342             disp_pos = locs->modrm_position + 1;
343         }
344         switch(locs->modrm_mod)
345         {
346             case 1:
347                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
348                         disp_pos)))));
349                 break;
350             case 2:
351                 if(sizePrefixPresent)
352                 {
353                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
354                             disp_pos)))));
355                 }
356                 else
357                 {
358                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
359                             disp_pos)))));
360                 }
361                 break;
362             case 0:
363                 // In 16-bit mode, the word displacement is modrm r/m 6
364                 if(sizePrefixPresent)
365                 {
366                     if(locs->modrm_rm == 6)
367                     {
368                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
369                                            *((const dword_t*)(b.start + disp_pos)))));
370                     }
371                     else
372                     {
373                         assert(b.start + disp_pos + 1 <= b.end);
374                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
375                     }
376                     break;
377                 }
378                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
379                 else
380                 {
381                     if(locs->modrm_rm == 5)
382                     {
383                         assert(b.start + disp_pos + 4 <= b.end);
384                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
385                                            *((const dword_t*)(b.start + disp_pos)))));
386                     }
387                     else
388                     {
389                         assert(b.start + disp_pos + 1 <= b.end);
390                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
391                     }
392                     break;
393                 }
394             default:
395                 assert(b.start + disp_pos + 1 <= b.end);
396                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
397                 break;
398         }
399     }
400
401     enum intelRegBanks
402     {
403         b_8bitNoREX = 0,
404         b_16bit,
405         b_32bit,
406         b_segment,
407         b_64bit,
408         b_xmm,
409         b_mm,
410         b_cr,
411         b_dr,
412         b_tr,
413         b_amd64ext,
414         b_8bitWithREX,
415         b_fpstack
416     };
417     static MachRegister IntelRegTable32[][8] = {
418         {
419             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
420         },
421         {
422             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
423         },
424         {
425             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
426         },
427         {
428            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
429         },
430         {
431             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
432         },
433         {
434             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
435         },
436         {
437             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
438         },
439         {
440             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
441         },
442         {
443             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
444         },
445         {
446             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
447         },
448         {
449             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
450         },
451         {
452             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
453         },
454         {
455             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
456         }
457
458     };
459     static MachRegister IntelRegTable64[][8] = {
460         {
461             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
462         },
463         {
464             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
465         },
466         {
467             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
468         },
469         {
470             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
471         },
472         {
473             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
474         },
475         {
476             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
477         },
478         {
479             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
480         },
481         {
482             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
483         },
484         {
485             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
486         },
487         {
488             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
489         },
490         {
491             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
492         },
493         {
494             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
495         },
496         {
497             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
498         }
499
500     };
501
502   /* Uses the appropriate lookup table based on the 
503      decoder architecture */
504   class IntelRegTable_access {
505     public:
506         inline MachRegister operator()(Architecture arch,
507                                        intelRegBanks bank,
508                                        int index)
509         {
510             assert(index >= 0 && index < 8);
511     
512             if(arch == Arch_x86_64)
513                 return IntelRegTable64[bank][index];
514             else if(arch == Arch_x86)
515                 return IntelRegTable32[bank][index];
516             else
517                 assert(0);
518             return IntelRegTable32[bank][index];
519         }
520
521   };
522   static IntelRegTable_access IntelRegTable;
523
524     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
525                                         bool isExtendedReg)
526     {
527         MachRegister retVal;
528
529         if(isExtendedReg)
530         {
531             retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
532         }
533         /* Promotion to 64-bit only applies to the operand types
534            that are varible (c,v,z). Ignoring c and z because they
535            do the right thing on 32- and 64-bit code.
536         else if(locs->rex_w)
537         {
538             // AMD64 with 64-bit operands
539             retVal = IntelRegTable[b_64bit][intelReg];
540         }
541         */
542         else
543         {
544             switch(opType)
545             {
546                 case op_v:
547                     if(locs->rex_w)
548                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
549                     else
550                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
551                     break;
552                 case op_b:
553                     if (locs->rex_position == -1) {
554                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
555                     } else {
556                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
557                     }
558                     break;
559                 case op_q:
560                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
561                     break;
562                 case op_w:
563                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
564                     break;
565                 case op_f:
566                 case op_dbl:
567                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
568                     break;
569                 case op_d:
570                 case op_si:
571                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
572                     break;
573                 default:
574                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
575                     break;
576             }
577         }
578
579         if (!ia32_is_mode_64()) {
580           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
581             assert(0);
582         }
583
584         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
585     }
586     
587     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
588     {
589         switch(opType)
590         {
591             case op_b:
592             case op_c:
593                 return u8;
594             case op_d:
595             case op_ss:
596             case op_allgprs:
597             case op_si:
598                 return u32;
599             case op_w:
600             case op_a:
601                 return u16;
602             case op_q:
603             case op_sd:
604                 return u64;
605             case op_v:
606             case op_lea:
607             case op_z:
608                 if(is32BitMode ^ sizePrefixPresent)
609                 {
610                     return u32;
611                 }
612                 else
613                 {
614                     return u16;
615                 }
616                 break;
617             case op_p:
618                 // book says operand size; arch-x86 says word + word * operand size
619                 if(is32BitMode ^ sizePrefixPresent)
620                 {
621                     return u48;
622                 }
623                 else
624                 {
625                     return u32;
626                 }
627             case op_dq:
628                 return u64;
629             case op_512:
630                 return m512;
631             case op_pi:
632             case op_ps:
633             case op_pd:
634                 return dbl128;
635             case op_s:
636                 return u48;
637             case op_f:
638                 return sp_float;
639             case op_dbl:
640                 return dp_float;
641             case op_14:
642                 return m14;
643             default:
644                 assert(!"Can't happen!");
645                 return u8;
646         }
647     }
648
649
650     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
651                                                   const ia32_operand& operand,
652                                                   int & imm_index, /* immediate operand index */
653                                                   const Instruction* insn_to_complete, 
654                                                   bool isRead, bool isWritten)
655     {
656       bool isCFT = false;
657       bool isCall = false;
658       bool isConditional = false;
659       InsnCategory cat = insn_to_complete->getCategory();
660       if(cat == c_BranchInsn || cat == c_CallInsn)
661         {
662           isCFT = true;
663           if(cat == c_CallInsn)
664             {
665               isCall = true;
666             }
667         }
668       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
669         isConditional = true;
670       }
671
672       unsigned int optype = operand.optype;
673       if (sizePrefixPresent && 
674           ((optype == op_v) ||
675            (optype == op_z))) {
676         optype = op_w;
677       }
678                 switch(operand.admet)
679                 {
680                     case 0:
681                     // No operand
682                     {
683 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
684                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
685                             fprintf(stderr, "%x ", b.start[i]);
686                         }
687                         fprintf(stderr, "\n");*/
688                         assert(!"Mismatched number of operands--check tables");
689                         return false;
690                     }
691                     case am_A:
692                     {
693                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
694                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
695                         Expression::Ptr op(makeDereferenceExpression(addr, makeSizeType(optype)));
696                         insn_to_complete->addSuccessor(op, isCall, false, false, false);
697                     }
698                     break;
699                     case am_C:
700                     {
701                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
702                         insn_to_complete->appendOperand(op, isRead, isWritten);
703                     }
704                     break;
705                     case am_D:
706                     {
707                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
708                         insn_to_complete->appendOperand(op, isRead, isWritten);
709                     }
710                     break;
711                     case am_E:
712                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
713                     // mod of 0x03 specifies direct register access).
714                     case am_M:
715                     // am_R is the inverse of am_M; it should only have a mod of 3
716                     case am_R:
717                         if(isCFT)
718                         {
719                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
720                         }
721                         else
722                         {
723                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
724                         }
725                     break;
726                     case am_F:
727                     {
728                         Expression::Ptr op(makeRegisterExpression(x86::flags));
729                         insn_to_complete->appendOperand(op, isRead, isWritten);
730                     }
731                     break;
732                     case am_G:
733                     {
734                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
735                                 optype, locs->rex_r)));
736                         insn_to_complete->appendOperand(op, isRead, isWritten);
737                     }
738                     break;
739                     case am_I:
740                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
741                                                                         locs->imm_position[imm_index++]), 
742                                                         isRead, isWritten);
743                         break;
744                     case am_J:
745                     {
746                         Expression::Ptr Offset(decodeImmediate(optype, 
747                                                                b.start + locs->imm_position[imm_index++], 
748                                                                true));
749                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
750                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
751                             decodedInstruction->getSize()))));
752                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
753
754                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
755                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
756                         if (isConditional) 
757                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
758                     }
759                     break;
760                     case am_O:
761                     {
762                     // Address/offset width, which is *not* what's encoded by the optype...
763                     // The deref's width is what's actually encoded here.
764                         int pseudoOpType;
765                         switch(locs->address_size)
766                         {
767                             case 1:
768                                 pseudoOpType = op_b;
769                                 break;
770                             case 2:
771                                 pseudoOpType = op_w;
772                                 break;
773                             case 4:
774                                 pseudoOpType = op_d;
775                                 break;
776                             case 0:
777                                 // closest I can get to "will be address size by default"
778                                 pseudoOpType = op_v;
779                                 break;
780                             default:
781                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
782                                 pseudoOpType = op_b;
783                                 break;
784                         }
785
786
787                         int offset_position = locs->opcode_position;
788                         if(locs->modrm_position > offset_position && locs->modrm_operand <
789                            (int)(insn_to_complete->m_Operands.size()))
790                         {
791                             offset_position = locs->modrm_position;
792                         }
793                         if(locs->sib_position > offset_position)
794                         {
795                             offset_position = locs->sib_position;
796                         }
797                         offset_position++;
798                         insn_to_complete->appendOperand(makeDereferenceExpression(
799                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
800                                                         isRead, isWritten);
801                     }
802                     break;
803                     case am_P:
804                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
805                                 isRead, isWritten);
806                         break;
807                     case am_Q:
808         
809                         switch(locs->modrm_mod)
810                         {
811                             // direct dereference
812                             case 0x00:
813                             case 0x01:
814                             case 0x02:
815                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
816                                 break;
817                             case 0x03:
818                                 // use of actual register
819                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
820                                                                isRead, isWritten);
821                                 break;
822                             default:
823                                 assert(!"2-bit value modrm_mod out of range");
824                                 break;
825                         };
826                         break;
827                     case am_S:
828                     // Segment register in modrm reg field.
829                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
830                                 isRead, isWritten);
831                         break;
832                     case am_T:
833                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
834                         // NOTE: this only appears in deprecated opcodes
835                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
836                                                        isRead, isWritten);
837                         break;
838                     case am_V:
839                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_xmm,locs->modrm_reg)),
840                                                        isRead, isWritten);
841                         break;
842                     case am_W:
843                         switch(locs->modrm_mod)
844                         {
845                             // direct dereference
846                             case 0x00:
847                             case 0x01:
848                             case 0x02:
849                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
850                                                                isRead, isWritten);
851                                 break;
852                             case 0x03:
853                             // use of actual register
854                             {
855                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_xmm,locs->modrm_rm)),
856                                                                isRead, isWritten);
857                                 break;
858                             }
859                             default:
860                                 assert(!"2-bit value modrm_mod out of range");
861                                 break;
862                         };
863                         break;
864                     case am_X:
865                     {
866                         MachRegister si_reg;
867                         if(m_Arch == Arch_x86)
868                         {
869                                 if(addrSizePrefixPresent)
870                                 {
871                                         si_reg = x86::si;
872                                 } else
873                                 {
874                                         si_reg = x86::esi;
875                                 }
876                         }
877                         else
878                         {
879                                 if(addrSizePrefixPresent)
880                                 {
881                                         si_reg = x86_64::esi;
882                                 } else
883                                 {
884                                         si_reg = x86_64::rsi;
885                                 }
886                         }
887                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
888                         Expression::Ptr si(makeRegisterExpression(si_reg));
889                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
890                                 Result(u32, 0x10))));
891                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
892                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
893                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
894                                                        isRead, isWritten);
895                     }
896                     break;
897                     case am_Y:
898                     {
899                         MachRegister di_reg;
900                         if(m_Arch == Arch_x86)
901                         {
902                                 if(addrSizePrefixPresent)
903                                 {
904                                         di_reg = x86::di;
905                                 } else
906                                 {
907                                         di_reg = x86::edi;
908                                 }
909                         }
910                         else
911                         {
912                                 if(addrSizePrefixPresent)
913                                 {
914                                         di_reg = x86_64::edi;
915                                 } else
916                                 {
917                                         di_reg = x86_64::rdi;
918                                 }
919                         }
920                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
921                         Expression::Ptr di(makeRegisterExpression(di_reg));
922                         Expression::Ptr es_segment = makeMultiplyExpression(es,
923                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
924                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
925                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
926                                                        isRead, isWritten);
927                     }
928                     break;
929                     case am_tworeghack:
930                     {
931                         if(optype == op_edxeax)
932                         {
933                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
934                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
935                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
936                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
937                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
938                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
939                             insn_to_complete->appendOperand(op, isRead, isWritten);
940                         }
941                         else if (optype == op_ecxebx)
942                         {
943                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
944                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
945                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
946                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
947                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
948                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
949                             insn_to_complete->appendOperand(op, isRead, isWritten);
950                         }
951                     }
952                     break;
953                     
954                     case am_reg:
955                     {
956                         MachRegister r(optype);
957                         r = MachRegister(r.val() & ~r.getArchitecture() | m_Arch);
958                         if(locs->rex_b && insn_to_complete->m_Operands.empty())
959                         {
960                             r = MachRegister((r.val()) | x86_64::r8.val());
961                         }
962                         if(sizePrefixPresent)
963                         {
964                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
965                         }
966                         Expression::Ptr op(makeRegisterExpression(r));
967                         insn_to_complete->appendOperand(op, isRead, isWritten);
968                     }
969                     break;
970                 case am_stackH:
971                 case am_stackP:
972                 // handled elsewhere
973                     break;
974                 case am_allgprs:
975                 {
976                     if(m_Arch == Arch_x86)
977                     {
978                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
979                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
980                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
981                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
982                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
983                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
984                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
985                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
986                     }
987                     else
988                     {
989                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
990                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
991                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
992                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
993                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
994                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
995                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
996                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
997                     }
998                 }
999                     break;
1000                 case am_ImplImm: {
1001                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1002                   break;
1003                 }
1004
1005                 default:
1006                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1007                         break;
1008                 };
1009                 return true;
1010             }
1011
1012     extern ia32_entry invalid;
1013     
1014     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1015     {
1016         if(decodedInstruction == NULL)
1017         {
1018             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1019             assert(decodedInstruction);
1020         }
1021         if(locs == NULL)
1022         {
1023             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1024             assert(locs);
1025         }
1026         locs = new(locs) ia32_locations; //reinit();
1027         assert(locs->sib_position == -1);
1028         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1029         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1030         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1031         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1032     }
1033     
1034     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1035     {
1036         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1037         doIA32Decode(b);
1038         if(decodedInstruction->getEntry()) {
1039             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1040                                     decodedInstruction->getPrefix(), locs, m_Arch));
1041         }
1042         else
1043         {
1044                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1045                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1046                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1047                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1048                 // yell at the user.
1049             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1050                                     decodedInstruction->getPrefix(), locs, m_Arch));
1051         }
1052         b.start += decodedInstruction->getSize();
1053     }
1054     
1055       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1056     {
1057         int imm_index = 0; // handle multiple immediate operands
1058         if(!decodedInstruction) return false;
1059         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1060         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1061         
1062         for(unsigned i = 0; i < 3; i++)
1063         {
1064             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1065                decodedInstruction->getEntry()->operands[i].optype == 0)
1066                 return true;
1067             if(!decodeOneOperand(b,
1068                                  decodedInstruction->getEntry()->operands[i], 
1069                                  imm_index, 
1070                                  insn_to_complete, 
1071                                  readsOperand(opsema, i),
1072                                  writesOperand(opsema, i)))
1073             {
1074                 return false;
1075             }
1076         }
1077     
1078         return true;
1079     }
1080
1081     
1082       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1083     {
1084         return InstructionDecoderImpl::decode(b);
1085     }
1086     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1087     {
1088       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1089       //insn_to_complete->m_Operands.reserve(4);
1090       doIA32Decode(b);        
1091       decodeOperands(insn_to_complete);
1092     }
1093     
1094 };
1095 };
1096