All AVX and AVX2 Series instructions (included 4 op) decoded
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
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30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3RW:
74                 case s1RW2R3R: // shld/shrd
75                 case s1RW2RW3R: // [i]div, cmpxch8b
76                 case s1R2R3R:
77                     return i == 0 || i == 1 || i == 2;
78                 case s1W2R3R4R:
79                     return i == 1 || i == 2 || i == 3;
80                 case s1RW2R3R4R:
81                     return i == 0 || i == 1 || i == 2 || i == 3;
82                 case sNONE:
83                 default:
84                     return false;
85             }
86       
87         }
88       
89         bool writesOperand(unsigned int opsema, unsigned int i)
90         {
91             switch(opsema) {
92                 case s1R2R:
93                 case s1R:
94                     return false;
95                 case s1RW:
96                 case s1W:
97                 case s1W2R:   // second operand read, first operand written (e.g. mov)
98                 case s1RW2R:  // two operands read, first written (e.g. add)
99                 case s1W2R3R: // e.g. imul
100                 case s1RW2R3R: // shld/shrd
101                 case s1RW2R3R4R:
102                   return i == 0;
103                 case s1R2RW:
104                   return i == 1;
105                 case s1W2RW:
106                 case s1RW2RW: // e.g. xchg
107                 case s1W2RW3R: // some mul
108                 case s1W2W3R: // e.g. les
109                 case s1RW2RW3R: // [i]div, cmpxch8b
110                   return i == 0 || i == 1;
111                 case s1W2R3RW: // (stack) push & pop
112                   return i == 0 || i == 2;
113                 case s1RW2R3RW:
114                   return i == 0 || i == 2;
115                 case sNONE:
116                 default:
117                     return false;
118             }
119         }
120
121
122     
123     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
124       InstructionDecoderImpl(a),
125     locs(NULL),
126     decodedInstruction(NULL),
127     sizePrefixPresent(false),
128     addrSizePrefixPresent(false)
129     {
130       if(a == Arch_x86_64) setMode(true);
131       
132     }
133     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
134     {
135         if(decodedInstruction) decodedInstruction->~ia32_instruction();
136         free(decodedInstruction);
137         if(locs) locs->~ia32_locations();
138         free(locs);
139
140     }
141     static const unsigned char modrm_use_sib = 4;
142     
143     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
144     {
145         ia32_set_mode_64(is64);
146     }
147     
148       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
149     {
150         unsigned scale;
151         Register index;
152         Register base;
153         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
154
155         decode_SIB(locs->sib_byte, scale, index, base);
156
157         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
158         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
159                                     locs->rex_x))));
160         Expression::Ptr baseAST;
161         if(base == 0x05)
162         {
163             switch(locs->modrm_mod)
164             {
165                 case 0x00:
166                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1, true);
167                     break;
168                 case 0x01: 
169                 case 0x02: 
170                     baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
171                                                                                                registerType,
172                                                                                                locs->rex_b)));
173                     break;
174                 case 0x03:
175                 default:
176                     assert(0);
177                     break;
178             };
179         }
180         else
181         {
182             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
183                                                                                                registerType,
184                                                                                                locs->rex_b)));
185         }
186
187         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
188         {
189             return baseAST;
190         }
191         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
192     }
193
194       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
195                                                                   unsigned int opType)
196     {
197        unsigned int regType = op_d;
198         Result_Type aw = ia32_is_mode_64() ? u64 : u32;
199         if (opType == op_lea) {
200             // For an LEA, aw (address width) is insufficient, use makeSizeType
201             aw = makeSizeType(opType);
202         }
203         if(ia32_is_mode_64())
204         {
205             regType = op_q;
206         }
207         Expression::Ptr e =
208             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, locs->rex_b));
209         switch(locs->modrm_mod)
210         {
211             case 0:
212                 if(locs->modrm_rm == modrm_use_sib) {
213                     e = makeSIBExpression(b);
214                 }
215                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
216                 {
217                     assert(locs->opcode_position > -1);
218                     if(ia32_is_mode_64())
219                     {
220                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
221                                             getModRMDisplacement(b), aw);
222                     }
223                     else
224                     {
225                         e = getModRMDisplacement(b);
226                     }
227         
228                 }
229                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
230                 {
231                     e = getModRMDisplacement(b);
232                 }
233                 if(opType == op_lea)
234                 {
235                     return e;
236                 }
237                 return makeDereferenceExpression(e, makeSizeType(opType));
238                 assert(0);
239                 break;
240             case 1:
241             case 2:
242             {
243                 if(locs->modrm_rm == modrm_use_sib) {
244                     e = makeSIBExpression(b);
245                 }
246                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
247                 if(opType == op_lea)
248                 {
249                     return disp_e;
250                 }
251                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
252             }
253             assert(0);
254             break;
255             case 3:
256                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, locs->rex_b));
257             default:
258                 return Expression::Ptr();
259         
260         };
261         // can't get here, but make the compiler happy...
262         assert(0);
263         return Expression::Ptr();
264     }
265
266     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
267                                                             bool isSigned)
268     {
269         // rex_w indicates we need to sign-extend also.
270         isSigned = isSigned || locs->rex_w;
271
272         switch(opType)
273         {
274             case op_b:
275                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
276                 break;
277             case op_d:
278                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
279             case op_w:
280                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
281                 break;
282             case op_q:
283                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
284                 break;
285             case op_v:
286                 if (locs->rex_w) {
287                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
288                 }
289                 //FALLTHROUGH
290             case op_z:
291                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
292                 // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
293                 if(!sizePrefixPresent)
294                 {
295                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
296                 }
297                 else
298                 {
299                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
300                 }
301                 break;
302             case op_p:
303                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
304                 // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
305                 if(!sizePrefixPresent)
306                 {
307                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
308                 }
309                 else
310                 {
311                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
312                 }
313
314                 break;
315             case op_a:
316             case op_dq:
317             case op_pd:
318             case op_ps:
319             case op_s:
320             case op_si:
321             case op_lea:
322             case op_allgprs:
323             case op_512:
324             case op_c:
325                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
326                 return Expression::Ptr();
327             default:
328                 assert(!"Can't happen: opType out of range");
329                 return Expression::Ptr();
330         }
331     }
332     
333     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
334     {
335         int disp_pos;
336
337         if(locs->sib_position != -1)
338         {
339             disp_pos = locs->sib_position + 1;
340         }
341         else
342         {
343             disp_pos = locs->modrm_position + 1;
344         }
345         switch(locs->modrm_mod)
346         {
347             case 1:
348                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
349                         disp_pos)))));
350                 break;
351             case 2:
352                 if(sizePrefixPresent)
353                 {
354                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
355                             disp_pos)))));
356                 }
357                 else
358                 {
359                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
360                             disp_pos)))));
361                 }
362                 break;
363             case 0:
364                 // In 16-bit mode, the word displacement is modrm r/m 6
365                 if(sizePrefixPresent)
366                 {
367                     if(locs->modrm_rm == 6)
368                     {
369                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
370                                            *((const dword_t*)(b.start + disp_pos)))));
371                     }
372                     // TODO FIXME; this was decoding wrong, but I'm not sure
373                     // why...
374                     else if (locs->modrm_rm == 5) {
375                         assert(b.start + disp_pos + 4 <= b.end);
376                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
377                                            *((const dword_t*)(b.start + disp_pos)))));
378                     } else {
379                         assert(b.start + disp_pos + 1 <= b.end);
380                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
381                     }
382                     break;
383                 }
384                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
385                 else
386                 {
387                     if(locs->modrm_rm == 5)
388                     {
389                         if (b.start + disp_pos + 4 <= b.end) 
390                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
391                                                *((const dword_t*)(b.start + disp_pos)))));
392                         else
393                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
394                     }
395                     else
396                     {
397                         if (b.start + disp_pos + 1 <= b.end)
398                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
399                         else
400                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
401                     }
402                     break;
403                 }
404             default:
405                 assert(b.start + disp_pos + 1 <= b.end);
406                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
407                 break;
408         }
409     }
410
411     enum intelRegBanks
412     {
413         b_8bitNoREX = 0,
414         b_16bit,
415         b_32bit,
416         b_segment,
417         b_64bit,
418         b_xmm,
419         b_xmmhigh,
420         b_mm,
421         b_cr,
422         b_dr,
423         b_tr,
424         b_amd64ext,
425         b_8bitWithREX,
426         b_fpstack,
427         amd64_ext_8,
428         amd64_ext_16,
429         amd64_ext_32
430     };
431     static MachRegister IntelRegTable32[][8] = {
432         {
433             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
434         },
435         {
436             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
437         },
438         {
439             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
440         },
441         {
442            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
443         },
444         {
445             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
446         },
447         {
448             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
449         },
450         {
451             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
452         },
453         {
454             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
455         },
456         {
457             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
458         },
459         {
460             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
461         },
462         {
463             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
464         },
465         {
466             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
467         },
468         {
469             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
470         },
471         {
472             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
473         }
474
475     };
476     static MachRegister IntelRegTable64[][8] = {
477         {
478             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
479         },
480         {
481             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
482         },
483         {
484             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
485         },
486         {
487             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
488         },
489         {
490             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
491         },
492         {
493             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
494         },
495         {
496             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
497         },
498         {
499             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
500         },
501         {
502             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
503         },
504         {
505             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
506         },
507         {
508             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
509         },
510         {
511             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
512         },
513         {
514             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
515         },
516         {
517             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
518         },
519         {
520             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
521         },
522         {
523             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
524         },
525         {
526             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
527         },
528   {
529     x86_64::ymm0, x86_64::ymm1, x86_64::ymm2, x86_64::ymm3, x86_64::ymm4, x86_64::ymm5, x86_64::ymm6, x86_64::ymm7
530   },
531   {
532     x86_64::ymm8, x86_64::ymm9, x86_64::ymm10, x86_64::ymm11, x86_64::ymm12, x86_64::ymm13, x86_64::ymm14, x86_64::ymm15
533   }
534
535     };
536
537   /* Uses the appropriate lookup table based on the 
538      decoder architecture */
539   class IntelRegTable_access {
540     public:
541         inline MachRegister operator()(Architecture arch,
542                                        intelRegBanks bank,
543                                        int index)
544         {
545             assert(index >= 0 && index < 8);
546     
547             if(arch == Arch_x86_64)
548                 return IntelRegTable64[bank][index];
549             else if(arch == Arch_x86) 
550             {
551               if(bank > b_fpstack) return InvalidReg;
552               return IntelRegTable32[bank][index];
553             }
554             assert(0);
555             return InvalidReg;
556         }
557
558   };
559   static IntelRegTable_access IntelRegTable;
560
561       bool InstructionDecoder_x86::isDefault64Insn()
562       {
563         switch(m_Operation->getID())
564         {
565         case e_jmp:
566         case e_pop:
567         case e_push:
568         case e_call:
569           return true;
570         default:
571           return false;
572         }
573         
574       }
575       
576
577     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
578                                         bool isExtendedReg)
579     {
580         MachRegister retVal;
581         
582
583         if(isExtendedReg)
584         {
585             switch(opType)
586             {
587                 case op_q:  
588                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
589                     break;
590                 case op_d:
591                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
592                     break;
593                 case op_w:
594                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
595                     break;
596                 case op_b:
597                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
598                     break;
599                 case op_v:
600                     if (locs->rex_w || isDefault64Insn())
601                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
602                     else if (!sizePrefixPresent)
603                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
604                     else
605                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
606                     break;      
607                 case op_p:
608                 case op_z:
609                     if (!sizePrefixPresent)
610                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
611                     else
612                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
613                     break;
614                 default:
615                     retVal = InvalidReg;
616             }
617         }
618         /* Promotion to 64-bit only applies to the operand types
619            that are varible (c,v,z). Ignoring c and z because they
620            do the right thing on 32- and 64-bit code.
621         else if(locs->rex_w)
622         {
623             // AMD64 with 64-bit operands
624             retVal = IntelRegTable[b_64bit][intelReg];
625         }
626         */
627         else
628         {
629             switch(opType)
630             {
631                 case op_v:
632                   if(locs->rex_w || isDefault64Insn())
633                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
634                     else
635                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
636                     break;
637                 case op_b:
638                     if (locs->rex_position == -1) {
639                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
640                     } else {
641                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
642                     }
643                     break;
644                 case op_q:
645                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
646                     break;
647                 case op_w:
648                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
649                     break;
650                 case op_f:
651                 case op_dbl:
652                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
653                     break;
654                 case op_d:
655                 case op_si:
656                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
657                     break;
658                 default:
659                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
660                     break;
661             }
662         }
663
664         if (!ia32_is_mode_64()) {
665           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
666             assert(0);
667         }
668
669         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
670     }
671     
672     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
673     {
674         switch(opType)
675         {
676             case op_b:
677             case op_c:
678                 return u8;
679             case op_d:
680             case op_ss:
681             case op_allgprs:
682             case op_si:
683                 return u32;
684             case op_w:
685             case op_a:
686                 return u16;
687             case op_q:
688             case op_sd:
689                 return u64;
690             case op_v:
691             case op_lea:
692             case op_z:
693                 if (locs->rex_w) 
694                 {
695                     return u64;
696                 }
697               if(ia32_is_mode_64() || !sizePrefixPresent)
698                 {
699                     return u32;
700                 }
701                 else
702                 {
703                     return u16;
704                 }
705                 break;
706             case op_y:
707                 if(ia32_is_mode_64())
708                         return u64;
709                 else
710                         return u32;
711                 break;
712             case op_p:
713                 // book says operand size; arch-x86 says word + word * operand size
714                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
715                 {
716                     return u48;
717                 }
718                 else
719                 {
720                     return u32;
721                 }
722             case op_dq:
723             case op_qq:
724                 return u64;
725             case op_512:
726                 return m512;
727             case op_pi:
728             case op_ps:
729             case op_pd:
730                 return dbl128;
731             case op_s:
732                 return u48;
733             case op_f:
734                 return sp_float;
735             case op_dbl:
736                 return dp_float;
737             case op_14:
738                 return m14;
739             default:
740                 assert(!"Can't happen!");
741                 return u8;
742         }
743     }
744
745
746     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
747                                                   const ia32_operand& operand,
748                                                   int & imm_index, /* immediate operand index */
749                                                   const Instruction* insn_to_complete, 
750                                                   bool isRead, bool isWritten)
751     {
752        bool isCFT = false;
753       bool isCall = false;
754       bool isConditional = false;
755       InsnCategory cat = insn_to_complete->getCategory();
756       if(cat == c_BranchInsn || cat == c_CallInsn)
757         {
758           isCFT = true;
759           if(cat == c_CallInsn)
760             {
761               isCall = true;
762             }
763         }
764       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
765         isConditional = true;
766       }
767
768       unsigned int optype = operand.optype;
769       int vex_vvvv = 0;
770       // int vex_l = 0;
771     if(decodedInstruction && decodedInstruction->getPrefix()->vex_prefix[0])
772     {
773       /* The vvvv bits are bits 3, 4, 5, 6 and are in 1's complement */
774       if(decodedInstruction->getPrefix()->vex_prefix[1])
775       {
776         // vex_l = decodedInstruction->getPrefix()->vex_prefix[1] & VEX3_L;
777         vex_vvvv = (unsigned char)VEXGET_VVVV(decodedInstruction->getPrefix()->vex_prefix[1]);
778       } else {
779         // vex_l = decodedInstruction->getPrefix()->vex_prefix[0] & VEX2_L;
780         vex_vvvv = (unsigned char)VEXGET_VVVV(decodedInstruction->getPrefix()->vex_prefix[0]);
781       }
782
783       vex_vvvv = (unsigned char)((~vex_vvvv) & 0x0f);
784       if(vex_vvvv >= 0x0f)
785           vex_vvvv = -1;
786     }
787       if (sizePrefixPresent && 
788           ((optype == op_v) ||
789            (optype == op_z))) {
790         optype = op_w;
791       }
792       if(optype == op_y) {
793           if(ia32_is_mode_64() && locs->rex_w)
794                   optype = op_q;
795           else
796                   optype = op_d;
797       }
798                 switch(operand.admet)
799                 {
800                     case 0:
801                     // No operand
802                     {
803 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
804                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
805                             fprintf(stderr, "%x ", b.start[i]);
806                         }
807                         fprintf(stderr, "\n");*/
808                         assert(!"Mismatched number of operands--check tables");
809                         return false;
810                     }
811                     case am_A:
812                     {
813                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
814                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
815                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
816                     }
817                     break;
818                     case am_C:
819                     {
820                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
821                         insn_to_complete->appendOperand(op, isRead, isWritten);
822                     }
823                     break;
824                     case am_D:
825                     {
826                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
827                         insn_to_complete->appendOperand(op, isRead, isWritten);
828                     }
829                     break;
830                     case am_E:
831                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
832                     // mod of 0x03 specifies direct register access).
833                     case am_M:
834                     // am_R is the inverse of am_M; it should only have a mod of 3
835                     case am_R:
836                     // can be am_R or am_M      
837                     case am_RM: 
838                         if(isCFT)
839                         {
840                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
841                         }
842                         else
843                         {
844                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
845                         }
846                     break;
847                     case am_F:
848                     {
849                         Expression::Ptr op(makeRegisterExpression(x86::flags));
850                         insn_to_complete->appendOperand(op, isRead, isWritten);
851                     }
852                     break;
853                     case am_G:
854                     {
855                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
856                                 optype, locs->rex_r)));
857                         insn_to_complete->appendOperand(op, isRead, isWritten);
858                     }
859                     break;
860                     case am_H:
861                       {
862                         if(vex_vvvv < 0)
863                         {
864                           printf("BAD VVVV: 0x%x\n", vex_vvvv);
865                           assert(0);
866                           break; /* Invalid instruction */
867                         }
868                           /* Operand comes from the VEX.vvvv bits */
869                          insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
870                               vex_vvvv <= 7 ? b_xmm : b_xmmhigh, vex_vvvv <= 7 ? vex_vvvv : vex_vvvv - 8)),
871                               isRead, isWritten);
872                       }
873                       break;
874                     case am_I:
875                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
876                                                                         locs->imm_position[imm_index++]), 
877                                                         isRead, isWritten);
878                         break;
879                     case am_J:
880                     {
881                         Expression::Ptr Offset(decodeImmediate(optype, 
882                                                                b.start + locs->imm_position[imm_index++], 
883                                                                true));
884                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
885                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
886                             decodedInstruction->getSize()))));
887                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
888
889                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
890                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
891                         if (isConditional) 
892                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
893                     }
894                     break;
895                     case am_O:
896                     {
897                     // Address/offset width, which is *not* what's encoded by the optype...
898                     // The deref's width is what's actually encoded here.
899                         int pseudoOpType;
900                         switch(locs->address_size)
901                         {
902                             case 1:
903                                 pseudoOpType = op_b;
904                                 break;
905                             case 2:
906                                 pseudoOpType = op_w;
907                                 break;
908                             case 4:
909                                 pseudoOpType = op_d;
910                                 break;
911                             case 0:
912                                 // closest I can get to "will be address size by default"
913                                 pseudoOpType = op_v;
914                                 break;
915                             default:
916                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
917                                 pseudoOpType = op_b;
918                                 break;
919                         }
920
921
922                         int offset_position = locs->opcode_position;
923                         if(locs->modrm_position > offset_position && locs->modrm_operand <
924                            (int)(insn_to_complete->m_Operands.size()))
925                         {
926                             offset_position = locs->modrm_position;
927                         }
928                         if(locs->sib_position > offset_position)
929                         {
930                             offset_position = locs->sib_position;
931                         }
932                         offset_position++;
933                         insn_to_complete->appendOperand(makeDereferenceExpression(
934                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
935                                                         isRead, isWritten);
936                     }
937                     break;
938                     case am_P:
939                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
940                                 isRead, isWritten);
941                         break;
942                     case am_Q:
943         
944                         switch(locs->modrm_mod)
945                         {
946                             // direct dereference
947                             case 0x00:
948                             case 0x01:
949                             case 0x02:
950                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
951                                 break;
952                             case 0x03:
953                                 // use of actual register
954                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
955                                                                isRead, isWritten);
956                                 break;
957                             default:
958                                 assert(!"2-bit value modrm_mod out of range");
959                                 break;
960                         };
961                         break;
962                     case am_S:
963                     // Segment register in modrm reg field.
964                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
965                                 isRead, isWritten);
966                         break;
967                     case am_T:
968                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
969                         // NOTE: this only appears in deprecated opcodes
970                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
971                                                        isRead, isWritten);
972                         break;
973                     case am_UM:
974                         switch(locs->modrm_mod)
975                         {
976                         // direct dereference
977                         case 0x00:
978                         case 0x01:
979                         case 0x02:
980                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
981                                                 isRead, isWritten);
982                                 break;
983                         case 0x03:
984                                 // use of actual register
985                                 {
986                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
987                                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
988                                                         isRead, isWritten);
989                                         break;
990                                 }
991                         default:
992                                 assert(!"2-bit value modrm_mod out of range");
993                                 break;
994                         };
995                         break;
996                     case am_V:
997                        
998                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
999                                 locs->rex_r ? b_xmmhigh : b_xmm,locs->modrm_reg)),
1000                                     isRead, isWritten);
1001                         break;
1002                     case am_U:
1003                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
1004                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
1005                                         isRead, isWritten);
1006                         break;
1007                     case am_W:
1008                         switch(locs->modrm_mod)
1009                         {
1010                             // direct dereference
1011                             case 0x00:
1012                             case 0x01:
1013                             case 0x02:
1014                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
1015                                                                isRead, isWritten);
1016                                 break;
1017                             case 0x03:
1018                             // use of actual register
1019                             {
1020                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
1021                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
1022                                         isRead, isWritten);
1023                                 break;
1024                             }
1025                             default:
1026                                 assert(!"2-bit value modrm_mod out of range");
1027                                 break;
1028                         };
1029                         break;
1030                     case am_X:
1031                     {
1032                         MachRegister si_reg;
1033                         if(m_Arch == Arch_x86)
1034                         {
1035                                 if(addrSizePrefixPresent)
1036                                 {
1037                                         si_reg = x86::si;
1038                                 } else
1039                                 {
1040                                         si_reg = x86::esi;
1041                                 }
1042                         }
1043                         else
1044                         {
1045                                 if(addrSizePrefixPresent)
1046                                 {
1047                                         si_reg = x86_64::esi;
1048                                 } else
1049                                 {
1050                                         si_reg = x86_64::rsi;
1051                                 }
1052                         }
1053                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1054                         Expression::Ptr si(makeRegisterExpression(si_reg));
1055                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1056                                 Result(u32, 0x10))));
1057                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1058                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1059                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1060                                                        isRead, isWritten);
1061                     }
1062                     break;
1063                     case am_Y:
1064                     {
1065                         MachRegister di_reg;
1066                         if(m_Arch == Arch_x86)
1067                         {
1068                                 if(addrSizePrefixPresent)
1069                                 {
1070                                         di_reg = x86::di;
1071                                 } else
1072                                 {
1073                                         di_reg = x86::edi;
1074                                 }
1075                         }
1076                         else
1077                         {
1078                                 if(addrSizePrefixPresent)
1079                                 {
1080                                         di_reg = x86_64::edi;
1081                                 } else
1082                                 {
1083                                         di_reg = x86_64::rdi;
1084                                 }
1085                         }
1086                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1087                         Expression::Ptr di(makeRegisterExpression(di_reg));
1088                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1089                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1090                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1091                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1092                                                        isRead, isWritten);
1093                     }
1094                     break;
1095                     case am_tworeghack:
1096                     {
1097                         if(optype == op_edxeax)
1098                         {
1099                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1100                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1101                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1102                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1103                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1104                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1105                             insn_to_complete->appendOperand(op, isRead, isWritten);
1106                         }
1107                         else if (optype == op_ecxebx)
1108                         {
1109                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1110                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1111                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1112                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1113                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1114                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1115                             insn_to_complete->appendOperand(op, isRead, isWritten);
1116                         }
1117                     }
1118                     break;
1119                     
1120                     case am_reg:
1121                     {
1122                         MachRegister r(optype);
1123                         r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1124                         entryID entryid = decodedInstruction->getEntry()->getID(locs);
1125                         if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1126                             (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1127                         {
1128                             // FP stack registers are not affected by the rex_b bit in AM_REG.
1129                            if(r.regClass() != (unsigned) x86::MMX)
1130                             {
1131                                 r = MachRegister((r.val()) | x86_64::r8.val());
1132                             }
1133                         }
1134                         if(sizePrefixPresent)
1135                         {
1136                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1137                         }
1138                         Expression::Ptr op(makeRegisterExpression(r));
1139                         insn_to_complete->appendOperand(op, isRead, isWritten);
1140                     }
1141                     break;
1142                 case am_stackH:
1143                 case am_stackP:
1144                 // handled elsewhere
1145                     break;
1146                 case am_allgprs:
1147                 {
1148                     if(m_Arch == Arch_x86)
1149                     {
1150                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1151                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1152                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1153                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1154                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1155                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1156                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1157                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1158                     }
1159                     else
1160                     {
1161                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1162                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1163                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1164                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1165                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1166                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1167                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1168                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1169                     }
1170                 }
1171                     break;
1172                 case am_ImplImm: {
1173                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1174                   break;
1175                 }
1176
1177                 default:
1178                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1179                         break;
1180                 };
1181                 return true;
1182             }
1183
1184     extern ia32_entry invalid;
1185     
1186     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1187     {
1188         if(decodedInstruction == NULL)
1189         {
1190             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1191             assert(decodedInstruction);
1192         }
1193         if(locs == NULL)
1194         {
1195             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1196             assert(locs);
1197         }
1198         locs = new(locs) ia32_locations; //reinit();
1199         assert(locs->sib_position == -1);
1200         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1201         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1202         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1203         if (decodedInstruction->getPrefix()->rexW()) {
1204            // as per 2.2.1.2 - rex.w overrides 66h
1205            sizePrefixPresent = false;
1206         }
1207         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1208         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1209         if(decodedInstruction->getEntry()) {
1210             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1211                                     decodedInstruction->getPrefix(), locs, m_Arch));
1212             
1213         }
1214         else
1215         {
1216                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1217                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1218                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1219                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1220                 // yell at the user.
1221             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1222                                     decodedInstruction->getPrefix(), locs, m_Arch));
1223         }
1224
1225     }
1226     
1227     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1228     {
1229         doIA32Decode(b);
1230         b.start += decodedInstruction->getSize();
1231     }
1232     
1233       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1234     {
1235        int imm_index = 0; // handle multiple immediate operands
1236         if(!decodedInstruction) return false;
1237         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1238         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1239
1240         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1241             decodedInstruction->getEntry()->getID() == e_ret_far) {
1242            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1243                                                                 ia32_is_mode_64() ? u64 : u32);
1244            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1245         }
1246
1247         for(int i = 0; i < 3; i++)
1248         {
1249             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1250                decodedInstruction->getEntry()->operands[i].optype == 0)
1251                 return true;
1252             if(!decodeOneOperand(b,
1253                                  decodedInstruction->getEntry()->operands[i], 
1254                                  imm_index, 
1255                                  insn_to_complete, 
1256                                  readsOperand(opsema, i),
1257                                  writesOperand(opsema, i)))
1258             {
1259                 return false;
1260             }
1261         }
1262
1263         /* Does this instruction have a 4th operand? */
1264         if(decodedInstruction->getEntry()->opsema >= s4OP)
1265         {
1266           if(!decodeOneOperand(b,
1267             {am_I, op_b}, /* This is always an IMM8 */
1268             imm_index,
1269             insn_to_complete,
1270             readsOperand(opsema, 3),
1271             writesOperand(opsema, 3)))
1272             {
1273                 return false;
1274             }
1275         }
1276     
1277         return true;
1278     }
1279
1280     
1281       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1282     {
1283         return InstructionDecoderImpl::decode(b);
1284     }
1285     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1286     {
1287       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1288       //insn_to_complete->m_Operands.reserve(4);
1289       doIA32Decode(b);        
1290       decodeOperands(insn_to_complete);
1291     }
1292     
1293 };
1294 };
1295