Starting more in depth testing
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
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3  * 
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29  */
30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3R: // shld/shrd
74                 case s1RW2RW3R: // [i]div, cmpxch8b
75                 case s1R2R3R:
76                     return i == 0 || i == 1 || i == 2;
77                     break;
78                 case sNONE:
79                 default:
80                     return false;
81             }
82       
83         }
84       
85         bool writesOperand(unsigned int opsema, unsigned int i)
86         {
87             switch(opsema) {
88                 case s1R2R:
89                 case s1R:
90                     return false;
91                 case s1RW:
92                 case s1W:
93                     case s1W2R:   // second operand read, first operand written (e.g. mov)
94                         case s1RW2R:  // two operands read, first written (e.g. add)
95                             case s1W2R3R: // e.g. imul
96                                 case s1RW2R3R: // shld/shrd
97                                     return i == 0;
98                 case s1R2RW:
99                     return i == 1;
100                 case s1W2RW:
101                     case s1RW2RW: // e.g. xchg
102                         case s1W2RW3R: // some mul
103                             case s1W2W3R: // e.g. les
104                                 case s1RW2RW3R: // [i]div, cmpxch8b
105                                     return i == 0 || i == 1;
106                                     case s1W2R3RW: // (stack) push & pop
107                                         return i == 0 || i == 2;
108                 case sNONE:
109                 default:
110                     return false;
111             }
112         }
113
114
115     
116     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
117       InstructionDecoderImpl(a),
118     locs(NULL),
119     decodedInstruction(NULL),
120     sizePrefixPresent(false),
121     addrSizePrefixPresent(false)
122     {
123       if(a == Arch_x86_64) setMode(true);
124       
125     }
126     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
127     {
128         if(decodedInstruction) decodedInstruction->~ia32_instruction();
129         free(decodedInstruction);
130         if(locs) locs->~ia32_locations();
131         free(locs);
132
133     }
134     static const unsigned char modrm_use_sib = 4;
135     
136     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
137     {
138         ia32_set_mode_64(is64);
139     }
140     
141       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
142     {
143         unsigned scale;
144         Register index;
145         Register base;
146         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
147
148         decode_SIB(locs->sib_byte, scale, index, base);
149
150         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
151         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
152                                     locs->rex_x))));
153         Expression::Ptr baseAST;
154         if(base == 0x05)
155         {
156             switch(locs->modrm_mod)
157             {
158                 case 0x00:
159                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1, true);
160                     break;
161                 case 0x01: 
162                 case 0x02: 
163                     baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
164                                                                                                registerType,
165                                                                                                locs->rex_b)));
166                     break;
167                 case 0x03:
168                 default:
169                     assert(0);
170                     break;
171             };
172         }
173         else
174         {
175             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
176                                                                                                registerType,
177                                                                                                locs->rex_b)));
178         }
179
180         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
181         {
182             return baseAST;
183         }
184         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
185     }
186
187       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
188                                                                   unsigned int opType)
189     {
190        unsigned int regType = op_d;
191        Result_Type aw;
192        if(ia32_is_mode_64())
193        {
194            if(addrSizePrefixPresent) {
195                aw = u32;
196            } else {
197                aw = u64;
198                regType = op_q;
199            }
200        }
201        else
202        {
203            if(!addrSizePrefixPresent) {
204                aw = u32;
205            } else {
206                aw = u16;
207                regType = op_w;
208            }
209        }
210         if (opType == op_lea) {
211             // For an LEA, aw (address width) is insufficient, use makeSizeType
212             aw = makeSizeType(opType);
213         }
214         Expression::Ptr e =
215             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, locs->rex_b));
216         switch(locs->modrm_mod)
217         {
218             case 0:
219                 if(locs->modrm_rm == modrm_use_sib) {
220                     e = makeSIBExpression(b);
221                 }
222                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
223                 {
224                     assert(locs->opcode_position > -1);
225                     if(ia32_is_mode_64())
226                     {
227                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
228                                             getModRMDisplacement(b), aw);
229                     }
230                     else
231                     {
232                         e = getModRMDisplacement(b);
233                     }
234         
235                 }
236                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
237                 {
238                     e = getModRMDisplacement(b);
239                 }
240                 if(opType == op_lea)
241                 {
242                     return e;
243                 }
244                 return makeDereferenceExpression(e, makeSizeType(opType));
245                 assert(0);
246                 break;
247             case 1:
248             case 2:
249             {
250                 if(locs->modrm_rm == modrm_use_sib) {
251                     e = makeSIBExpression(b);
252                 }
253                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
254                 if(opType == op_lea)
255                 {
256                     return disp_e;
257                 }
258                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
259             }
260             assert(0);
261             break;
262             case 3:
263                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, locs->rex_b));
264             default:
265                 return Expression::Ptr();
266         
267         };
268         // can't get here, but make the compiler happy...
269         assert(0);
270         return Expression::Ptr();
271     }
272
273     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
274                                                             bool isSigned)
275     {
276         // rex_w indicates we need to sign-extend also.
277         isSigned = isSigned || locs->rex_w;
278         
279         switch(opType)
280         {
281             case op_b:
282                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
283                 break;
284             case op_d:
285                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
286             case op_w:
287                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
288                 break;
289             case op_q:
290                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
291                 break;
292             case op_v:
293                 if (locs->rex_w || isDefault64Insn()) {
294                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
295                 }
296                 //if(!sizePrefixPresent)
297                 //{
298                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
299                     //}
300                     //else
301                     //{
302                     //return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
303                     //}
304                 break;
305             case op_z:
306                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
307                 // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
308                 //if(!addrSizePrefixPresent)
309                 //{
310                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
311                     //}
312                     //else
313                     //{
314                     //return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
315                     //}
316                 break;
317             case op_p:
318                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
319                 // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
320                 if(!sizePrefixPresent)
321                 {
322                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
323                 }
324                 else
325                 {
326                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
327                 }
328
329                 break;
330             case op_a:
331             case op_dq:
332             case op_pd:
333             case op_ps:
334             case op_s:
335             case op_si:
336             case op_lea:
337             case op_allgprs:
338             case op_512:
339             case op_c:
340                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
341                 return Expression::Ptr();
342             default:
343                 assert(!"Can't happen: opType out of range");
344                 return Expression::Ptr();
345         }
346     }
347     
348     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
349     {
350         int disp_pos;
351
352         if(locs->sib_position != -1)
353         {
354             disp_pos = locs->sib_position + 1;
355         }
356         else
357         {
358             disp_pos = locs->modrm_position + 1;
359         }
360         switch(locs->modrm_mod)
361         {
362             case 1:
363                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
364                         disp_pos)))));
365                 break;
366             case 2:
367                 if(0 && sizePrefixPresent)
368                 {
369                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
370                             disp_pos)))));
371                 }
372                 else
373                 {
374                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
375                             disp_pos)))));
376                 }
377                 break;
378             case 0:
379                 // In 16-bit mode, the word displacement is modrm r/m 6
380                 if(sizePrefixPresent && !ia32_is_mode_64())
381                 {
382                     if(locs->modrm_rm == 6)
383                     {
384                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
385                                            *((const dword_t*)(b.start + disp_pos)))));
386                     }
387                     // TODO FIXME; this was decoding wrong, but I'm not sure
388                     // why...
389                     else if (locs->modrm_rm == 5) {
390                         assert(b.start + disp_pos + 4 <= b.end);
391                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
392                                            *((const dword_t*)(b.start + disp_pos)))));
393                     } else {
394                         assert(b.start + disp_pos + 1 <= b.end);
395                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
396                     }
397                     break;
398                 }
399                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
400                 else
401                 {
402                     if(locs->modrm_rm == 5)
403                     {
404                         if (b.start + disp_pos + 4 <= b.end) 
405                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
406                                                *((const dword_t*)(b.start + disp_pos)))));
407                         else
408                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
409                     }
410                     else
411                     {
412                         if (b.start + disp_pos + 1 <= b.end)
413                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
414                         else
415                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
416                     }
417                     break;
418                 }
419             default:
420                 assert(b.start + disp_pos + 1 <= b.end);
421                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
422                 break;
423         }
424     }
425
426     enum intelRegBanks
427     {
428         b_8bitNoREX = 0,
429         b_16bit,
430         b_32bit,
431         b_segment,
432         b_64bit,
433         b_xmm,
434         b_xmmhigh,
435         b_mm,
436         b_cr,
437         b_dr,
438         b_tr,
439         b_amd64ext,
440         b_8bitWithREX,
441         b_fpstack,
442         amd64_ext_8,
443         amd64_ext_16,
444         amd64_ext_32,
445     };
446     static MachRegister IntelRegTable32[][8] = {
447         {
448             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
449         },
450         {
451             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
452         },
453         {
454             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
455         },
456         {
457            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
458         },
459         {
460             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
461         },
462         {
463             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
464         },
465         {
466             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
467         },
468         {
469             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
470         },
471         {
472             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
473         },
474         {
475             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
476         },
477         {
478             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
479         },
480         {
481             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
482         },
483         {
484             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
485         },
486         {
487             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
488         }
489
490     };
491     static MachRegister IntelRegTable64[][8] = {
492         {
493             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
494         },
495         {
496             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
497         },
498         {
499             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
500         },
501         {
502             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
503         },
504         {
505             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
506         },
507         {
508             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
509         },
510         {
511             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
512         },
513         {
514             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
515         },
516         {
517             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
518         },
519         {
520             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
521         },
522         {
523             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
524         },
525         {
526             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
527         },
528         {
529             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
530         },
531         {
532             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
533         },
534         {
535             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
536         },
537         {
538             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
539         },
540         {
541             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
542         }
543
544     };
545
546   /* Uses the appropriate lookup table based on the 
547      decoder architecture */
548   class IntelRegTable_access {
549     public:
550         inline MachRegister operator()(Architecture arch,
551                                        intelRegBanks bank,
552                                        int index)
553         {
554             assert(index >= 0 && index < 8);
555     
556             if(arch == Arch_x86_64)
557                 return IntelRegTable64[bank][index];
558             else if(arch == Arch_x86) 
559             {
560               if(bank > b_fpstack) return InvalidReg;
561               return IntelRegTable32[bank][index];
562             }
563             assert(0);
564             return InvalidReg;
565         }
566
567   };
568   static IntelRegTable_access IntelRegTable;
569
570       bool InstructionDecoder_x86::isDefault64Insn()
571       {
572         switch(m_Operation->getID())
573         {
574         case e_jmp:
575         case e_pop:
576         case e_push:
577         case e_call:
578           return true;
579         default:
580           return false;
581         }
582         
583       }
584       
585
586     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
587                                         bool isExtendedReg)
588     {
589         MachRegister retVal;
590         
591
592         if(isExtendedReg)
593         {
594             switch(opType)
595             {
596                 case op_q:  
597                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
598                     break;
599                 case op_d:
600                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
601                     break;
602                 case op_w:
603                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
604                     break;
605                 case op_b:
606                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
607                     break;
608                 case op_v:
609                     if (locs->rex_w || isDefault64Insn())
610                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
611                     else if (!sizePrefixPresent)
612                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
613                     //else
614                     //    retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
615                     break;      
616                 case op_p:
617                 case op_z:
618                     //              if (!sizePrefixPresent)
619                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
620                         //                  else
621                         //  retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
622                     break;
623             case op_f:
624             case op_dbl:
625                 // extended reg ignored on FP regs
626                 retVal = IntelRegTable(m_Arch, b_fpstack,intelReg);
627                 break;
628                 default:
629                     retVal = InvalidReg;
630             }
631         }
632         /* Promotion to 64-bit only applies to the operand types
633            that are varible (c,v,z). Ignoring c and z because they
634            do the right thing on 32- and 64-bit code.
635         else if(locs->rex_w)
636         {
637             // AMD64 with 64-bit operands
638             retVal = IntelRegTable[b_64bit][intelReg];
639         }
640         */
641         else
642         {
643             switch(opType)
644             {
645                 case op_v:
646                   if(locs->rex_w || isDefault64Insn())
647                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
648                     else
649                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
650                     break;
651                 case op_b:
652                     if (locs->rex_byte & 0x40) {
653                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
654                     } else {
655                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
656                     }
657                     break;
658                 case op_q:
659                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
660                     break;
661                 case op_w:
662                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
663                     break;
664                 case op_f:
665                 case op_dbl:
666                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
667                     break;
668                 case op_d:
669                 case op_si:
670                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
671                     break;
672                 default:
673                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
674                     break;
675             }
676         }
677
678         if (!ia32_is_mode_64()) {
679           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
680             assert(0);
681         }
682
683         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
684     }
685     
686     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
687     {
688         switch(opType)
689         {
690             case op_b:
691             case op_c:
692                 return u8;
693             case op_d:
694             case op_ss:
695             case op_allgprs:
696             case op_si:
697                 return u32;
698             case op_w:
699             case op_a:
700                 return u16;
701             case op_q:
702             case op_sd:
703                 return u64;
704             case op_v:
705             case op_lea:
706             case op_z:
707                 if (locs->rex_w) 
708                 {
709                     return u64;
710                 }
711                 //if(ia32_is_mode_64() || !sizePrefixPresent)
712                 //{
713                     return u32;
714                     //}
715                     //else
716                     //{
717                     //return u16;
718                     //}
719                 break;
720             case op_y:
721                 if(ia32_is_mode_64())
722                         return u64;
723                 else
724                         return u32;
725                 break;
726             case op_p:
727                 // book says operand size; arch-x86 says word + word * operand size
728                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
729                 {
730                     return u48;
731                 }
732                 else
733                 {
734                     return u32;
735                 }
736             case op_dq:
737             case op_qq:
738                 return u64;
739             case op_512:
740                 return m512;
741             case op_pi:
742             case op_ps:
743             case op_pd:
744                 return dbl128;
745             case op_s:
746                 return u48;
747             case op_f:
748                 return sp_float;
749             case op_dbl:
750                 return dp_float;
751             case op_14:
752                 return m14;
753             default:
754                 assert(!"Can't happen!");
755                 return u8;
756         }
757     }
758
759
760     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
761                                                   const ia32_operand& operand,
762                                                   int & imm_index, /* immediate operand index */
763                                                   const Instruction* insn_to_complete, 
764                                                   bool isRead, bool isWritten)
765     {
766        bool isCFT = false;
767       bool isCall = false;
768       bool isConditional = false;
769       InsnCategory cat = insn_to_complete->getCategory();
770       if(cat == c_BranchInsn || cat == c_CallInsn)
771         {
772           isCFT = true;
773           if(cat == c_CallInsn)
774             {
775               isCall = true;
776             }
777         }
778       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
779         isConditional = true;
780       }
781
782       unsigned int optype = operand.optype;
783       if (sizePrefixPresent && 
784           ((optype == op_v) ||
785            (optype == op_z)) &&
786           (operand.admet != am_J)) {
787         optype = op_w;
788       }
789       if(optype == op_y) {
790           if(ia32_is_mode_64() && locs->rex_w)
791                   optype = op_q;
792           else
793                   optype = op_d;
794       }
795                 switch(operand.admet)
796                 {
797                     case 0:
798                     // No operand
799                     {
800 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
801                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
802                             fprintf(stderr, "%x ", b.start[i]);
803                         }
804                         fprintf(stderr, "\n");*/
805                         assert(!"Mismatched number of operands--check tables");
806                         return false;
807                     }
808                     case am_A:
809                     {
810                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
811                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
812                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
813                     }
814                     break;
815                     case am_C:
816                     {
817                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
818                         insn_to_complete->appendOperand(op, isRead, isWritten);
819                     }
820                     break;
821                     case am_D:
822                     {
823                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
824                         insn_to_complete->appendOperand(op, isRead, isWritten);
825                     }
826                     break;
827                     case am_E:
828                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
829                     // mod of 0x03 specifies direct register access).
830                     case am_M:
831                     // am_R is the inverse of am_M; it should only have a mod of 3
832                     case am_R:
833                     // can be am_R or am_M      
834                     case am_RM: 
835                         if(isCFT)
836                         {
837                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
838                         }
839                         else
840                         {
841                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
842                         }
843                     break;
844                     case am_F:
845                     {
846                         Expression::Ptr op(makeRegisterExpression(x86::flags));
847                         insn_to_complete->appendOperand(op, isRead, isWritten);
848                     }
849                     break;
850                     case am_G:
851                     {
852                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
853                                 optype, locs->rex_r)));
854                         insn_to_complete->appendOperand(op, isRead, isWritten);
855                     }
856                     break;
857                     case am_I:
858                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
859                                                                         locs->imm_position[imm_index++]), 
860                                                         isRead, isWritten);
861                         break;
862                     case am_J:
863                     {
864                         Expression::Ptr Offset(decodeImmediate(optype, 
865                                                                b.start + locs->imm_position[imm_index++], 
866                                                                true));
867                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
868                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
869                             decodedInstruction->getSize()))));
870                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
871
872                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
873                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
874                         if (isConditional) 
875                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
876                     }
877                     break;
878                     case am_O:
879                     {
880                     // Address/offset width, which is *not* what's encoded by the optype...
881                     // The deref's width is what's actually encoded here.
882                         int pseudoOpType;
883                         switch(locs->address_size)
884                         {
885                             case 1:
886                                 pseudoOpType = op_b;
887                                 break;
888                             case 2:
889                                 pseudoOpType = op_w;
890                                 break;
891                             case 4:
892                                 pseudoOpType = op_d;
893                                 break;
894                             case 0:
895                                 if(m_Arch == Arch_x86_64) {
896                                     if(!addrSizePrefixPresent)
897                                         pseudoOpType = op_q;
898                                     else
899                                         pseudoOpType = op_d;
900                                 } else {
901                                     pseudoOpType = op_v;
902                                 }
903                                 break;
904                             default:
905                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
906                                 pseudoOpType = op_b;
907                                 break;
908                         }
909
910
911                         int offset_position = locs->opcode_position;
912                         if(locs->modrm_position > offset_position && locs->modrm_operand <
913                            (int)(insn_to_complete->m_Operands.size()))
914                         {
915                             offset_position = locs->modrm_position;
916                         }
917                         if(locs->sib_position > offset_position)
918                         {
919                             offset_position = locs->sib_position;
920                         }
921                         offset_position++;
922                         insn_to_complete->appendOperand(makeDereferenceExpression(
923                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
924                                                         isRead, isWritten);
925                     }
926                     break;
927                     case am_P:
928                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
929                                 isRead, isWritten);
930                         break;
931                     case am_Q:
932         
933                         switch(locs->modrm_mod)
934                         {
935                             // direct dereference
936                             case 0x00:
937                             case 0x01:
938                             case 0x02:
939                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
940                                 break;
941                             case 0x03:
942                                 // use of actual register
943                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
944                                                                isRead, isWritten);
945                                 break;
946                             default:
947                                 assert(!"2-bit value modrm_mod out of range");
948                                 break;
949                         };
950                         break;
951                     case am_S:
952                     // Segment register in modrm reg field.
953                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
954                                 isRead, isWritten);
955                         break;
956                     case am_T:
957                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
958                         // NOTE: this only appears in deprecated opcodes
959                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
960                                                        isRead, isWritten);
961                         break;
962                     case am_UM:
963                         switch(locs->modrm_mod)
964                         {
965                         // direct dereference
966                         case 0x00:
967                         case 0x01:
968                         case 0x02:
969                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
970                                                 isRead, isWritten);
971                                 break;
972                         case 0x03:
973                                 // use of actual register
974                                 {
975                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
976                                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
977                                                         isRead, isWritten);
978                                         break;
979                                 }
980                         default:
981                                 assert(!"2-bit value modrm_mod out of range");
982                                 break;
983                         };
984                         break;
985                     case am_V:
986                        
987                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
988                                 locs->rex_r ? b_xmmhigh : b_xmm,locs->modrm_reg)),
989                                     isRead, isWritten);
990                         break;
991                     case am_W:
992                         switch(locs->modrm_mod)
993                         {
994                             // direct dereference
995                             case 0x00:
996                             case 0x01:
997                             case 0x02:
998                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
999                                                                isRead, isWritten);
1000                                 break;
1001                             case 0x03:
1002                             // use of actual register
1003                             {
1004                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
1005                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
1006                                         isRead, isWritten);
1007                                 break;
1008                             }
1009                             default:
1010                                 assert(!"2-bit value modrm_mod out of range");
1011                                 break;
1012                         };
1013                         break;
1014                     case am_X:
1015                     {
1016                         MachRegister si_reg;
1017                         if(m_Arch == Arch_x86)
1018                         {
1019                                 if(addrSizePrefixPresent)
1020                                 {
1021                                         si_reg = x86::si;
1022                                 } else
1023                                 {
1024                                         si_reg = x86::esi;
1025                                 }
1026                         }
1027                         else
1028                         {
1029                                 if(addrSizePrefixPresent)
1030                                 {
1031                                         si_reg = x86_64::esi;
1032                                 } else
1033                                 {
1034                                         si_reg = x86_64::rsi;
1035                                 }
1036                         }
1037                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1038                         Expression::Ptr si(makeRegisterExpression(si_reg));
1039                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1040                                 Result(u32, 0x10))));
1041                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1042                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1043                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1044                                                        isRead, isWritten);
1045                     }
1046                     break;
1047                     case am_Y:
1048                     {
1049                         MachRegister di_reg;
1050                         if(m_Arch == Arch_x86)
1051                         {
1052                                 if(addrSizePrefixPresent)
1053                                 {
1054                                         di_reg = x86::di;
1055                                 } else
1056                                 {
1057                                         di_reg = x86::edi;
1058                                 }
1059                         }
1060                         else
1061                         {
1062                                 if(addrSizePrefixPresent)
1063                                 {
1064                                         di_reg = x86_64::edi;
1065                                 } else
1066                                 {
1067                                         di_reg = x86_64::rdi;
1068                                 }
1069                         }
1070                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1071                         Expression::Ptr di(makeRegisterExpression(di_reg));
1072                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1073                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1074                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1075                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1076                                                        isRead, isWritten);
1077                     }
1078                     break;
1079                     case am_tworeghack:
1080                     {
1081                         if(optype == op_edxeax)
1082                         {
1083                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1084                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1085                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1086                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1087                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1088                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1089                             insn_to_complete->appendOperand(op, isRead, isWritten);
1090                         }
1091                         else if (optype == op_ecxebx)
1092                         {
1093                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1094                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1095                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1096                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1097                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1098                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1099                             insn_to_complete->appendOperand(op, isRead, isWritten);
1100                         }
1101                     }
1102                     break;
1103                     
1104                     case am_reg:
1105                     {
1106                         MachRegister r(optype);
1107                         int size = r.size();
1108                         if((m_Arch == Arch_x86_64) && (r.regClass() == x86::GPR) && (size == 4))
1109                         {
1110                             int reg_size = isDefault64Insn() ? op_q : op_v;
1111                             if(sizePrefixPresent)
1112                             {
1113                                 reg_size = op_w;
1114                             }
1115                             // implicit regs are not extended
1116                             r = makeRegisterID((r.val() & 0xFF), reg_size, false);
1117                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1118                             if(locs->rex_b && insn_to_complete->m_Operands.empty() &&
1119                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0)))
1120                             {
1121                                 r = MachRegister((r.val()) | x86_64::r8.val());
1122                                 assert(r.name() != "<INVALID_REG>");
1123                             }
1124                         }
1125                         else 
1126                         {
1127                             r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1128                             
1129                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1130                             if(insn_to_complete->m_Operands.empty() && 
1131                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1132                             {
1133                                 unsigned int opcode_byte = *(b.start+locs->opcode_position);
1134                                 unsigned int reg_id = (opcode_byte & 0x07);
1135                                 if(locs->rex_b) 
1136                                 {
1137                                     // FP stack registers are not affected by the rex_b bit in AM_REG.
1138                                     if(r.regClass() == (unsigned) x86::GPR)
1139                                     {
1140                                         int reg_op_type = op_d;
1141                                         switch(size)
1142                                         {
1143                                         case 1:
1144                                             reg_op_type = op_b;
1145                                             break;
1146                                         case 2:
1147                                             reg_op_type = op_w;
1148                                             break;
1149                                         case 8:
1150                                             reg_op_type = op_q;
1151                                             break;
1152                                         default:
1153                                             break;
1154                                         }
1155                                         r = makeRegisterID(reg_id, reg_op_type, true);
1156                                         //                                      r = MachRegister((r.val()) | x86_64::r8.val());
1157                                         assert(r.name() != "<INVALID_REG>");
1158                                     }
1159                                 }
1160                                 else if((r.size() == 1) && (locs->rex_byte & 0x40))
1161                                 {
1162                                     r = makeRegisterID(reg_id, op_b, false);
1163                                     assert(r.name() != "<INVALID_REG>");
1164                                 }
1165                             }
1166                             if(sizePrefixPresent && (r.regClass() == x86::GPR) && r.size() >= 4)
1167                             {
1168                                 r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1169                                 assert(r.name() != "<INVALID_REG>");
1170                             }
1171                         }
1172                         Expression::Ptr op(makeRegisterExpression(r));
1173                         insn_to_complete->appendOperand(op, isRead, isWritten);
1174                     }
1175                     break;
1176                 case am_stackH:
1177                 case am_stackP:
1178                 // handled elsewhere
1179                     break;
1180                 case am_allgprs:
1181                 {
1182                     if(m_Arch == Arch_x86)
1183                     {
1184                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1185                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1186                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1187                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1188                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1189                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1190                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1191                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1192                     }
1193                     else
1194                     {
1195                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1196                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1197                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1198                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1199                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1200                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1201                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1202                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1203                     }
1204                 }
1205                     break;
1206                 case am_ImplImm: {
1207                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1208                   break;
1209                 }
1210
1211                 default:
1212                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1213                         break;
1214                 };
1215                 return true;
1216             }
1217
1218     extern ia32_entry invalid;
1219     
1220     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1221     {
1222         if(decodedInstruction == NULL)
1223         {
1224             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1225             assert(decodedInstruction);
1226         }
1227         if(locs == NULL)
1228         {
1229             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1230             assert(locs);
1231         }
1232         locs = new(locs) ia32_locations; //reinit();
1233         assert(locs->sib_position == -1);
1234         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1235         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1236         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1237         if (decodedInstruction->getPrefix()->rexW()) {
1238            // as per 2.2.1.2 - rex.w overrides 66h
1239            sizePrefixPresent = false;
1240         }
1241         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1242         static ia32_entry invalid = { e_No_Entry, 0, 0, false, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1243         if(decodedInstruction->getEntry()) {
1244             // check prefix validity
1245             // lock prefix only allowed on certain insns.
1246             // TODO: refine further to check memory written operand
1247             if(decodedInstruction->getPrefix()->getPrefix(0) == PREFIX_LOCK)
1248             {
1249                 switch(decodedInstruction->getEntry()->id)
1250                 {
1251                 case e_add:
1252                 case e_adc:
1253                 case e_and:
1254                 case e_btc:
1255                 case e_btr:
1256                 case e_bts:
1257                 case e_cmpxch:
1258                 case e_cmpxch8b:
1259                 case e_dec:
1260                 case e_inc:
1261                 case e_neg:
1262                 case e_not:
1263                 case e_or:
1264                 case e_sbb:
1265                 case e_sub:
1266                 case e_xor:
1267                 case e_xadd:
1268                 case e_xchg:
1269                     break;
1270                 default:
1271                     m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1272                                     decodedInstruction->getPrefix(), locs, m_Arch));
1273                     return;
1274                 }
1275             }
1276             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1277                                     decodedInstruction->getPrefix(), locs, m_Arch));
1278             
1279         }
1280         else
1281         {
1282                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1283                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1284                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1285                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1286                 // yell at the user.
1287             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1288                                     decodedInstruction->getPrefix(), locs, m_Arch));
1289         }
1290
1291     }
1292     
1293     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1294     {
1295         doIA32Decode(b);
1296         b.start += decodedInstruction->getSize();
1297     }
1298     
1299       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1300     {
1301        int imm_index = 0; // handle multiple immediate operands
1302         if(!decodedInstruction) return false;
1303         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1304         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1305
1306         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1307             decodedInstruction->getEntry()->getID() == e_ret_far) {
1308            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1309                                                                 ia32_is_mode_64() ? u64 : u32);
1310            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1311         }
1312
1313         for(unsigned i = 0; i < 3; i++)
1314         {
1315             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1316                decodedInstruction->getEntry()->operands[i].optype == 0)
1317                 return true;
1318             if(!decodeOneOperand(b,
1319                                  decodedInstruction->getEntry()->operands[i], 
1320                                  imm_index, 
1321                                  insn_to_complete, 
1322                                  readsOperand(opsema, i),
1323                                  writesOperand(opsema, i)))
1324             {
1325                 return false;
1326             }
1327         }
1328     
1329         return true;
1330     }
1331
1332     
1333       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1334     {
1335         return InstructionDecoderImpl::decode(b);
1336     }
1337     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1338     {
1339       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1340       //insn_to_complete->m_Operands.reserve(4);
1341       doIA32Decode(b);        
1342       decodeOperands(insn_to_complete);
1343     }
1344     
1345 };
1346 };
1347