Correctly decode 64-bit op_v operands
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
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30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/h/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/h/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/h/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3R: // shld/shrd
74                 case s1RW2RW3R: // [i]div, cmpxch8b
75                 case s1R2R3R:
76                     return i == 0 || i == 1 || i == 2;
77                     break;
78                 case sNONE:
79                 default:
80                     return false;
81             }
82       
83         }
84       
85         bool writesOperand(unsigned int opsema, unsigned int i)
86         {
87             switch(opsema) {
88                 case s1R2R:
89                 case s1R:
90                     return false;
91                 case s1RW:
92                 case s1W:
93                     case s1W2R:   // second operand read, first operand written (e.g. mov)
94                         case s1RW2R:  // two operands read, first written (e.g. add)
95                             case s1W2R3R: // e.g. imul
96                                 case s1RW2R3R: // shld/shrd
97                                     return i == 0;
98                 case s1R2RW:
99                     return i == 1;
100                 case s1W2RW:
101                     case s1RW2RW: // e.g. xchg
102                         case s1W2RW3R: // some mul
103                             case s1W2W3R: // e.g. les
104                                 case s1RW2RW3R: // [i]div, cmpxch8b
105                                     return i == 0 || i == 1;
106                                     case s1W2R3RW: // (stack) push & pop
107                                         return i == 0 || i == 2;
108                 case sNONE:
109                 default:
110                     return false;
111             }
112         }
113
114
115     
116     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
117       InstructionDecoderImpl(a),
118     locs(NULL),
119     decodedInstruction(NULL),
120     sizePrefixPresent(false)
121     {
122     }
123     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
124     {
125         if(decodedInstruction) decodedInstruction->~ia32_instruction();
126         free(decodedInstruction);
127         if(locs) locs->~ia32_locations();
128         free(locs);
129
130     }
131     static const unsigned char modrm_use_sib = 4;
132     
133     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
134     {
135         ia32_set_mode_64(is64);
136     }
137     
138       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
139     {
140         unsigned scale;
141         Register index;
142         Register base;
143         Result_Type registerType = ia32_is_mode_64() ? u32 : u64;
144
145         decode_SIB(locs->sib_byte, scale, index, base);
146
147         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
148         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
149                                     locs->rex_x))));
150         Expression::Ptr baseAST;
151         if(base == 0x05)
152         {
153             switch(locs->modrm_mod)
154             {
155                 case 0x00:
156                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
157                     break;
158                     case 0x01: {
159                         MachRegister reg;
160                         if (locs->rex_b)
161                             reg = x86_64::r13;
162                         else
163                           reg = MachRegister::getFramePointer(m_Arch);
164                         
165                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
166                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
167                                                     registerType);
168                         break;
169                     }
170                     case 0x02: {
171                         MachRegister reg;
172                         if (locs->rex_b)
173                             reg = x86_64::r13;
174                         else
175                             reg = MachRegister::getFramePointer(m_Arch);
176
177                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
178                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
179                                                     registerType);
180                         break;
181                     }
182                 case 0x03:
183                 default:
184                     assert(0);
185                     break;
186             };
187         }
188         else
189         {
190             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
191                                                                                                registerType,
192                                                                                                locs->rex_b)));
193         }
194         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
195         {
196             return baseAST;
197         }
198         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
199     }
200
201       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
202                                                                   unsigned int opType)
203     {
204        unsigned int regType = op_d;
205         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
206         if(ia32_is_mode_64())
207         {
208             regType = op_q;
209         }
210         Expression::Ptr e =
211             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
212         switch(locs->modrm_mod)
213         {
214             case 0:
215                 if(locs->modrm_rm == modrm_use_sib) {
216                     e = makeSIBExpression(b);
217                 }
218                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
219                 {
220                     assert(locs->opcode_position > -1);
221                     if(ia32_is_mode_64())
222                     {
223                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
224                                             getModRMDisplacement(b), aw);
225                     }
226                     else
227                     {
228                         e = getModRMDisplacement(b);
229                     }
230         
231                 }
232                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
233                 {
234                     e = getModRMDisplacement(b);
235                 }
236                 if(opType == op_lea)
237                 {
238                     return e;
239                 }
240                 return makeDereferenceExpression(e, makeSizeType(opType));
241                 assert(0);
242                 break;
243             case 1:
244             case 2:
245             {
246                 if(locs->modrm_rm == modrm_use_sib) {
247                     e = makeSIBExpression(b);
248                 }
249                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
250                 if(opType == op_lea)
251                 {
252                     return disp_e;
253                 }
254                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
255             }
256             assert(0);
257             break;
258             case 3:
259                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
260             default:
261                 return Expression::Ptr();
262         
263         };
264         // can't get here, but make the compiler happy...
265         assert(0);
266         return Expression::Ptr();
267     }
268
269     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
270                                                             bool isSigned)
271     {
272         switch(opType)
273         {
274             case op_b:
275                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
276                 break;
277             case op_d:
278                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
279             case op_w:
280                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
281                 break;
282             case op_q:
283                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
284                 break;
285             case op_v:
286             case op_z:
287         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
288         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
289               if (locs->rex_w) {
290                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
291               }
292               else if(!sizePrefixPresent)
293                 {
294                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
295                 }
296                 else
297                 {
298                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
299                 }
300         
301                 break;
302             case op_p:
303         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
304         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
305                 if(!sizePrefixPresent)
306                 {
307                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
308                 }
309                 else
310                 {
311                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
312                 }
313         
314                 break;
315             case op_a:
316             case op_dq:
317             case op_pd:
318             case op_ps:
319             case op_s:
320             case op_si:
321             case op_lea:
322             case op_allgprs:
323             case op_512:
324             case op_c:
325                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
326                 return Expression::Ptr();
327             default:
328                 assert(!"Can't happen: opType out of range");
329                 return Expression::Ptr();
330         }
331     }
332     
333     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
334     {
335         int disp_pos;
336
337         if(locs->sib_position != -1)
338         {
339             disp_pos = locs->sib_position + 1;
340         }
341         else
342         {
343             disp_pos = locs->modrm_position + 1;
344         }
345         switch(locs->modrm_mod)
346         {
347             case 1:
348                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
349                         disp_pos)))));
350                 break;
351             case 2:
352                 if(sizePrefixPresent)
353                 {
354                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
355                             disp_pos)))));
356                 }
357                 else
358                 {
359                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
360                             disp_pos)))));
361                 }
362                 break;
363             case 0:
364                 // In 16-bit mode, the word displacement is modrm r/m 6
365                 if(sizePrefixPresent)
366                 {
367                     if(locs->modrm_rm == 6)
368                     {
369                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
370                                            *((const dword_t*)(b.start + disp_pos)))));
371                     }
372                     // TODO FIXME; this was decoding wrong, but I'm not sure
373                     // why...
374                     else if (locs->modrm_rm == 5) {
375                         assert(b.start + disp_pos + 4 <= b.end);
376                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
377                                            *((const dword_t*)(b.start + disp_pos)))));
378                     } else {
379                         assert(b.start + disp_pos + 1 <= b.end);
380                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
381                     }
382                     break;
383                 }
384                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
385                 else
386                 {
387                     if(locs->modrm_rm == 5)
388                     {
389                         assert(b.start + disp_pos + 4 <= b.end);
390                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
391                                            *((const dword_t*)(b.start + disp_pos)))));
392                     }
393                     else
394                     {
395                         assert(b.start + disp_pos + 1 <= b.end);
396                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
397                     }
398                     break;
399                 }
400             default:
401                 assert(b.start + disp_pos + 1 <= b.end);
402                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
403                 break;
404         }
405     }
406
407     enum intelRegBanks
408     {
409         b_8bitNoREX = 0,
410         b_16bit,
411         b_32bit,
412         b_segment,
413         b_64bit,
414         b_xmm,
415         b_xmmhigh,
416         b_mm,
417         b_cr,
418         b_dr,
419         b_tr,
420         b_amd64ext,
421         b_8bitWithREX,
422         b_fpstack,
423         amd64_ext_8,
424         amd64_ext_16,
425         amd64_ext_32
426     };
427     static MachRegister IntelRegTable32[][8] = {
428         {
429             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
430         },
431         {
432             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
433         },
434         {
435             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
436         },
437         {
438            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
439         },
440         {
441             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
442         },
443         {
444             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
445         },
446         {
447             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
448         },
449         {
450             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
451         },
452         {
453             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
454         },
455         {
456             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
457         },
458         {
459             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
460         },
461         {
462             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
463         },
464         {
465             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
466         },
467         {
468             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
469         }
470
471     };
472     static MachRegister IntelRegTable64[][8] = {
473         {
474             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
475         },
476         {
477             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
478         },
479         {
480             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
481         },
482         {
483             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
484         },
485         {
486             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
487         },
488         {
489             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
490         },
491         {
492             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
493         },
494         {
495             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
496         },
497         {
498             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
499         },
500         {
501             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
502         },
503         {
504             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
505         },
506         {
507             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
508         },
509         {
510             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
511         },
512         {
513             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
514         },
515         {
516             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
517         },
518         {
519             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
520         },
521         {
522             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
523         }
524
525     };
526
527   /* Uses the appropriate lookup table based on the 
528      decoder architecture */
529   class IntelRegTable_access {
530     public:
531         inline MachRegister operator()(Architecture arch,
532                                        intelRegBanks bank,
533                                        int index)
534         {
535             assert(index >= 0 && index < 8);
536     
537             if(arch == Arch_x86_64)
538                 return IntelRegTable64[bank][index];
539             else if(arch == Arch_x86) 
540             {
541               assert(bank <= b_fpstack);
542               return IntelRegTable32[bank][index];
543             }
544             
545             else
546                 assert(0);
547             return IntelRegTable32[bank][index];
548         }
549
550   };
551   static IntelRegTable_access IntelRegTable;
552
553       bool InstructionDecoder_x86::isDefault64Insn()
554       {
555         switch(m_Operation->getID())
556         {
557         case e_jmp:
558         case e_pop:
559         case e_push:
560         case e_call:
561           return true;
562         default:
563           return false;
564         }
565         
566       }
567       
568
569     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
570                                         bool isExtendedReg)
571     {
572         MachRegister retVal;
573         
574
575         if(isExtendedReg)
576         {
577             switch(opType)
578             {
579                 case op_q:  
580                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
581                     break;
582                 case op_d:
583                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
584                     break;
585                 case op_w:
586                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
587                     break;
588                 case op_b:
589                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
590                     break;
591                 case op_v:
592                     if (locs->rex_w)
593                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
594                     else if (!sizePrefixPresent)
595                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
596                     else
597                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
598                     break;      
599                 case op_p:
600                 case op_z:
601                     if (!sizePrefixPresent)
602                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
603                     else
604                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
605                     break;
606                 default:
607                     fprintf(stderr, "%d\n", opType);
608                     fprintf(stderr, "%s\n",  decodedInstruction->getEntry()->name(locs));
609                     assert(0 && "opType=" && opType);
610             }
611         }
612         /* Promotion to 64-bit only applies to the operand types
613            that are varible (c,v,z). Ignoring c and z because they
614            do the right thing on 32- and 64-bit code.
615         else if(locs->rex_w)
616         {
617             // AMD64 with 64-bit operands
618             retVal = IntelRegTable[b_64bit][intelReg];
619         }
620         */
621         else
622         {
623             switch(opType)
624             {
625                 case op_v:
626                   if(locs->rex_w || isDefault64Insn())
627                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
628                     else
629                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
630                     break;
631                 case op_b:
632                     if (locs->rex_position == -1) {
633                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
634                     } else {
635                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
636                     }
637                     break;
638                 case op_q:
639                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
640                     break;
641                 case op_w:
642                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
643                     break;
644                 case op_f:
645                 case op_dbl:
646                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
647                     break;
648                 case op_d:
649                 case op_si:
650                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
651                     break;
652                 default:
653                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
654                     break;
655             }
656         }
657
658         if (!ia32_is_mode_64()) {
659           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
660             assert(0);
661         }
662
663         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
664     }
665     
666     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
667     {
668         switch(opType)
669         {
670             case op_b:
671             case op_c:
672                 return u8;
673             case op_d:
674             case op_ss:
675             case op_allgprs:
676             case op_si:
677                 return u32;
678             case op_w:
679             case op_a:
680                 return u16;
681             case op_q:
682             case op_sd:
683                 return u64;
684             case op_v:
685             case op_lea:
686             case op_z:
687               if(!ia32_is_mode_64() ^ sizePrefixPresent)
688                 {
689                     return u32;
690                 }
691                 else
692                 {
693                     return u16;
694                 }
695                 break;
696             case op_y:
697                 if(ia32_is_mode_64())
698                         return u64;
699                 else
700                         return u32;
701                 break;
702             case op_p:
703                 // book says operand size; arch-x86 says word + word * operand size
704                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
705                 {
706                     return u48;
707                 }
708                 else
709                 {
710                     return u32;
711                 }
712             case op_dq:
713                 return u64;
714             case op_512:
715                 return m512;
716             case op_pi:
717             case op_ps:
718             case op_pd:
719                 return dbl128;
720             case op_s:
721                 return u48;
722             case op_f:
723                 return sp_float;
724             case op_dbl:
725                 return dp_float;
726             case op_14:
727                 return m14;
728             default:
729                 assert(!"Can't happen!");
730                 return u8;
731         }
732     }
733
734
735     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
736                                                   const ia32_operand& operand,
737                                                   int & imm_index, /* immediate operand index */
738                                                   const Instruction* insn_to_complete, 
739                                                   bool isRead, bool isWritten)
740     {
741        bool isCFT = false;
742       bool isCall = false;
743       bool isConditional = false;
744       InsnCategory cat = insn_to_complete->getCategory();
745       if(cat == c_BranchInsn || cat == c_CallInsn)
746         {
747           isCFT = true;
748           if(cat == c_CallInsn)
749             {
750               isCall = true;
751             }
752         }
753       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
754         isConditional = true;
755       }
756
757       unsigned int optype = operand.optype;
758       if (sizePrefixPresent && 
759           ((optype == op_v) ||
760            (optype == op_z))) {
761         optype = op_w;
762       }
763       if(optype == op_y) {
764           if(ia32_is_mode_64() && locs->rex_w)
765                   optype = op_q;
766           else
767                   optype = op_d;
768       }
769                 switch(operand.admet)
770                 {
771                     case 0:
772                     // No operand
773                     {
774 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
775                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
776                             fprintf(stderr, "%x ", b.start[i]);
777                         }
778                         fprintf(stderr, "\n");*/
779                         assert(!"Mismatched number of operands--check tables");
780                         return false;
781                     }
782                     case am_A:
783                     {
784                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
785                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
786                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
787                     }
788                     break;
789                     case am_C:
790                     {
791                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
792                         insn_to_complete->appendOperand(op, isRead, isWritten);
793                     }
794                     break;
795                     case am_D:
796                     {
797                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
798                         insn_to_complete->appendOperand(op, isRead, isWritten);
799                     }
800                     break;
801                     case am_E:
802                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
803                     // mod of 0x03 specifies direct register access).
804                     case am_M:
805                     // am_R is the inverse of am_M; it should only have a mod of 3
806                     case am_R:
807                     // can be am_R or am_M      
808                     case am_RM: 
809                         if(isCFT)
810                         {
811                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
812                         }
813                         else
814                         {
815                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
816                         }
817                     break;
818                     case am_F:
819                     {
820                         Expression::Ptr op(makeRegisterExpression(x86::flags));
821                         insn_to_complete->appendOperand(op, isRead, isWritten);
822                     }
823                     break;
824                     case am_G:
825                     {
826                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
827                                 optype, locs->rex_r)));
828                         insn_to_complete->appendOperand(op, isRead, isWritten);
829                     }
830                     break;
831                     case am_I:
832                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
833                                                                         locs->imm_position[imm_index++]), 
834                                                         isRead, isWritten);
835                         break;
836                     case am_J:
837                     {
838                         Expression::Ptr Offset(decodeImmediate(optype, 
839                                                                b.start + locs->imm_position[imm_index++], 
840                                                                true));
841                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
842                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
843                             decodedInstruction->getSize()))));
844                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
845
846                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
847                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
848                         if (isConditional) 
849                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
850                     }
851                     break;
852                     case am_O:
853                     {
854                     // Address/offset width, which is *not* what's encoded by the optype...
855                     // The deref's width is what's actually encoded here.
856                         int pseudoOpType;
857                         switch(locs->address_size)
858                         {
859                             case 1:
860                                 pseudoOpType = op_b;
861                                 break;
862                             case 2:
863                                 pseudoOpType = op_w;
864                                 break;
865                             case 4:
866                                 pseudoOpType = op_d;
867                                 break;
868                             case 0:
869                                 // closest I can get to "will be address size by default"
870                                 pseudoOpType = op_v;
871                                 break;
872                             default:
873                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
874                                 pseudoOpType = op_b;
875                                 break;
876                         }
877
878
879                         int offset_position = locs->opcode_position;
880                         if(locs->modrm_position > offset_position && locs->modrm_operand <
881                            (int)(insn_to_complete->m_Operands.size()))
882                         {
883                             offset_position = locs->modrm_position;
884                         }
885                         if(locs->sib_position > offset_position)
886                         {
887                             offset_position = locs->sib_position;
888                         }
889                         offset_position++;
890                         insn_to_complete->appendOperand(makeDereferenceExpression(
891                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
892                                                         isRead, isWritten);
893                     }
894                     break;
895                     case am_P:
896                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
897                                 isRead, isWritten);
898                         break;
899                     case am_Q:
900         
901                         switch(locs->modrm_mod)
902                         {
903                             // direct dereference
904                             case 0x00:
905                             case 0x01:
906                             case 0x02:
907                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
908                                 break;
909                             case 0x03:
910                                 // use of actual register
911                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
912                                                                isRead, isWritten);
913                                 break;
914                             default:
915                                 assert(!"2-bit value modrm_mod out of range");
916                                 break;
917                         };
918                         break;
919                     case am_S:
920                     // Segment register in modrm reg field.
921                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
922                                 isRead, isWritten);
923                         break;
924                     case am_T:
925                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
926                         // NOTE: this only appears in deprecated opcodes
927                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
928                                                        isRead, isWritten);
929                         break;
930                     case am_UM:
931                         switch(locs->modrm_mod)
932                         {
933                         // direct dereference
934                         case 0x00:
935                         case 0x01:
936                         case 0x02:
937                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
938                                                 isRead, isWritten);
939                                 break;
940                         case 0x03:
941                                 // use of actual register
942                                 {
943                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
944                                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
945                                                         isRead, isWritten);
946                                         break;
947                                 }
948                         default:
949                                 assert(!"2-bit value modrm_mod out of range");
950                                 break;
951                         };
952                         break;
953                     case am_V:
954                        
955                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
956                                 (locs->rex_r == 1 )? b_xmmhigh : b_xmm,locs->modrm_reg)),
957                                     isRead, isWritten);
958                         break;
959                     case am_W:
960                         switch(locs->modrm_mod)
961                         {
962                             // direct dereference
963                             case 0x00:
964                             case 0x01:
965                             case 0x02:
966                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
967                                                                isRead, isWritten);
968                                 break;
969                             case 0x03:
970                             // use of actual register
971                             {
972                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
973                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
974                                         isRead, isWritten);
975                                 break;
976                             }
977                             default:
978                                 assert(!"2-bit value modrm_mod out of range");
979                                 break;
980                         };
981                         break;
982                     case am_X:
983                     {
984                         MachRegister si_reg;
985                         if(m_Arch == Arch_x86)
986                         {
987                                 if(addrSizePrefixPresent)
988                                 {
989                                         si_reg = x86::si;
990                                 } else
991                                 {
992                                         si_reg = x86::esi;
993                                 }
994                         }
995                         else
996                         {
997                                 if(addrSizePrefixPresent)
998                                 {
999                                         si_reg = x86_64::esi;
1000                                 } else
1001                                 {
1002                                         si_reg = x86_64::rsi;
1003                                 }
1004                         }
1005                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1006                         Expression::Ptr si(makeRegisterExpression(si_reg));
1007                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1008                                 Result(u32, 0x10))));
1009                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1010                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1011                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1012                                                        isRead, isWritten);
1013                     }
1014                     break;
1015                     case am_Y:
1016                     {
1017                         MachRegister di_reg;
1018                         if(m_Arch == Arch_x86)
1019                         {
1020                                 if(addrSizePrefixPresent)
1021                                 {
1022                                         di_reg = x86::di;
1023                                 } else
1024                                 {
1025                                         di_reg = x86::edi;
1026                                 }
1027                         }
1028                         else
1029                         {
1030                                 if(addrSizePrefixPresent)
1031                                 {
1032                                         di_reg = x86_64::edi;
1033                                 } else
1034                                 {
1035                                         di_reg = x86_64::rdi;
1036                                 }
1037                         }
1038                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1039                         Expression::Ptr di(makeRegisterExpression(di_reg));
1040                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1041                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1042                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1043                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1044                                                        isRead, isWritten);
1045                     }
1046                     break;
1047                     case am_tworeghack:
1048                     {
1049                         if(optype == op_edxeax)
1050                         {
1051                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1052                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1053                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1054                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1055                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1056                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1057                             insn_to_complete->appendOperand(op, isRead, isWritten);
1058                         }
1059                         else if (optype == op_ecxebx)
1060                         {
1061                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1062                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1063                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1064                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1065                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1066                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1067                             insn_to_complete->appendOperand(op, isRead, isWritten);
1068                         }
1069                     }
1070                     break;
1071                     
1072                     case am_reg:
1073                     {
1074                         MachRegister r(optype);
1075                         r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1076                         entryID entryid = decodedInstruction->getEntry()->getID(locs);
1077                         if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1078                             (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1079                         {
1080                             // FP stack registers are not affected by the rex_b bit in AM_REG.
1081                            if(r.regClass() != (unsigned) x86::MMX)
1082                             {
1083                                 r = MachRegister((r.val()) | x86_64::r8.val());
1084                             }
1085                         }
1086                         if(sizePrefixPresent)
1087                         {
1088                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1089                         }
1090                         Expression::Ptr op(makeRegisterExpression(r));
1091                         insn_to_complete->appendOperand(op, isRead, isWritten);
1092                     }
1093                     break;
1094                 case am_stackH:
1095                 case am_stackP:
1096                 // handled elsewhere
1097                     break;
1098                 case am_allgprs:
1099                 {
1100                     if(m_Arch == Arch_x86)
1101                     {
1102                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1103                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1104                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1105                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1106                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1107                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1108                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1109                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1110                     }
1111                     else
1112                     {
1113                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1114                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1115                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1116                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1117                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1118                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1119                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1120                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1121                     }
1122                 }
1123                     break;
1124                 case am_ImplImm: {
1125                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1126                   break;
1127                 }
1128
1129                 default:
1130                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1131                         break;
1132                 };
1133                 return true;
1134             }
1135
1136     extern ia32_entry invalid;
1137     
1138     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1139     {
1140         if(decodedInstruction == NULL)
1141         {
1142             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1143             assert(decodedInstruction);
1144         }
1145         if(locs == NULL)
1146         {
1147             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1148             assert(locs);
1149         }
1150         locs = new(locs) ia32_locations; //reinit();
1151         assert(locs->sib_position == -1);
1152         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1153         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1154         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1155         if (decodedInstruction->getPrefix()->rexW()) {
1156            // as per 2.2.1.2 - rex.w overrides 66h
1157            sizePrefixPresent = false;
1158         }
1159         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1160     }
1161     
1162     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1163     {
1164         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1165         doIA32Decode(b);
1166         if(decodedInstruction->getEntry()) {
1167             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1168                                     decodedInstruction->getPrefix(), locs, m_Arch));
1169             
1170         }
1171         else
1172         {
1173                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1174                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1175                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1176                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1177                 // yell at the user.
1178             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1179                                     decodedInstruction->getPrefix(), locs, m_Arch));
1180         }
1181         b.start += decodedInstruction->getSize();
1182     }
1183     
1184       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1185     {
1186        int imm_index = 0; // handle multiple immediate operands
1187         if(!decodedInstruction) return false;
1188         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1189         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1190
1191         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1192             decodedInstruction->getEntry()->getID() == e_ret_far) {
1193            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1194                                                                 ia32_is_mode_64() ? u64 : u32);
1195            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1196         }
1197
1198         for(unsigned i = 0; i < 3; i++)
1199         {
1200             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1201                decodedInstruction->getEntry()->operands[i].optype == 0)
1202                 return true;
1203             if(!decodeOneOperand(b,
1204                                  decodedInstruction->getEntry()->operands[i], 
1205                                  imm_index, 
1206                                  insn_to_complete, 
1207                                  readsOperand(opsema, i),
1208                                  writesOperand(opsema, i)))
1209             {
1210                 return false;
1211             }
1212         }
1213     
1214         return true;
1215     }
1216
1217     
1218       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1219     {
1220         return InstructionDecoderImpl::decode(b);
1221     }
1222     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1223     {
1224       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1225       //insn_to_complete->m_Operands.reserve(4);
1226       doIA32Decode(b);        
1227       decodeOperands(insn_to_complete);
1228     }
1229     
1230 };
1231 };
1232