Structural changes to VEX decodings
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
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30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 #define VEX_DEBUG
44
45 using namespace std;
46 using namespace NS_x86;
47 namespace Dyninst
48 {
49     namespace InstructionAPI
50     {
51     
52         bool readsOperand(unsigned int opsema, unsigned int i)
53         {
54             switch(opsema) {
55                 case s1R2R:
56                     return (i == 0 || i == 1);
57                 case s1R:
58                 case s1RW:
59                     return i == 0;
60                 case s1W:
61                     return false;
62                 case s1W2RW:
63                 case s1W2R:   // second operand read, first operand written (e.g. mov)
64                     return i == 1;
65                 case s1RW2R:  // two operands read, first written (e.g. add)
66                 case s1RW2RW: // e.g. xchg
67                 case s1R2RW:
68                     return i == 0 || i == 1;
69                 case s1W2R3R: // e.g. imul
70                 case s1W2RW3R: // some mul
71                 case s1W2R3RW: // (stack) push & pop
72                     return i == 1 || i == 2;
73                 case s1W2W3R: // e.g. les
74                     return i == 2;
75                 case s1RW2R3RW:
76                 case s1RW2R3R: // shld/shrd
77                 case s1RW2RW3R: // [i]div, cmpxch8b
78                 case s1R2R3R:
79                     return i == 0 || i == 1 || i == 2;
80                 case s1W2R3R4R:
81                     return i == 1 || i == 2 || i == 3;
82                 case s1RW2R3R4R:
83                     return i == 0 || i == 1 || i == 2 || i == 3;
84                 case sNONE:
85                 default:
86                     return false;
87             }
88       
89         }
90       
91         bool writesOperand(unsigned int opsema, unsigned int i)
92         {
93             switch(opsema) {
94                 case s1R2R:
95                 case s1R:
96                     return false;
97                 case s1RW:
98                 case s1W:
99                 case s1W2R:   // second operand read, first operand written (e.g. mov)
100                 case s1RW2R:  // two operands read, first written (e.g. add)
101                 case s1W2R3R: // e.g. imul
102                 case s1RW2R3R: // shld/shrd
103                 case s1RW2R3R4R:
104                   return i == 0;
105                 case s1R2RW:
106                   return i == 1;
107                 case s1W2RW:
108                 case s1RW2RW: // e.g. xchg
109                 case s1W2RW3R: // some mul
110                 case s1W2W3R: // e.g. les
111                 case s1RW2RW3R: // [i]div, cmpxch8b
112                   return i == 0 || i == 1;
113                 case s1W2R3RW: // (stack) push & pop
114                   return i == 0 || i == 2;
115                 case s1RW2R3RW:
116                   return i == 0 || i == 2;
117                 case sNONE:
118                 default:
119                     return false;
120             }
121         }
122
123
124     
125     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
126       InstructionDecoderImpl(a),
127     locs(NULL),
128     decodedInstruction(NULL),
129     sizePrefixPresent(false),
130     addrSizePrefixPresent(false)
131     {
132       if(a == Arch_x86_64) setMode(true);
133       
134     }
135     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
136     {
137         if(decodedInstruction) decodedInstruction->~ia32_instruction();
138         free(decodedInstruction);
139         if(locs) locs->~ia32_locations();
140         free(locs);
141
142     }
143     static const unsigned char modrm_use_sib = 4;
144     
145     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
146     {
147         ia32_set_mode_64(is64);
148     }
149     
150       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
151     {
152         unsigned scale;
153         Register index;
154         Register base;
155         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
156
157         decode_SIB(locs->sib_byte, scale, index, base);
158
159         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
160         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
161                                     locs->rex_x))));
162         Expression::Ptr baseAST;
163         if(base == 0x05)
164         {
165             switch(locs->modrm_mod)
166             {
167                 case 0x00:
168                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1, true);
169                     break;
170                 case 0x01: 
171                 case 0x02: 
172                     baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
173                                                                                                registerType,
174                                                                                                locs->rex_b)));
175                     break;
176                 case 0x03:
177                 default:
178                     assert(0);
179                     break;
180             };
181         }
182         else
183         {
184             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
185                                                                                                registerType,
186                                                                                                locs->rex_b)));
187         }
188
189         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
190         {
191             return baseAST;
192         }
193         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
194     }
195
196       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
197                                                                   unsigned int opType)
198     {
199        unsigned int regType = op_d;
200        Result_Type aw;
201        if(ia32_is_mode_64())
202        {
203            if(addrSizePrefixPresent) {
204                aw = u32;
205            } else {
206                aw = u64;
207                regType = op_q;
208            }
209        }
210        else
211        {
212            if(!addrSizePrefixPresent) {
213                aw = u32;
214            } else {
215                aw = u16;
216                regType = op_w;
217            }
218        }
219         if (opType == op_lea) {
220             // For an LEA, aw (address width) is insufficient, use makeSizeType
221             aw = makeSizeType(opType);
222         }
223         Expression::Ptr e =
224             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, locs->rex_b));
225         switch(locs->modrm_mod)
226         {
227             case 0:
228                 if(locs->modrm_rm == modrm_use_sib) {
229                     e = makeSIBExpression(b);
230                 }
231                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
232                 {
233                     assert(locs->opcode_position > -1);
234                     if(ia32_is_mode_64())
235                     {
236                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
237                                             getModRMDisplacement(b), aw);
238                     }
239                     else
240                     {
241                         e = getModRMDisplacement(b);
242                     }
243         
244                 }
245                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
246                 {
247                     e = getModRMDisplacement(b);
248                 }
249                 if(opType == op_lea)
250                 {
251                     return e;
252                 }
253                 return makeDereferenceExpression(e, makeSizeType(opType));
254                 assert(0);
255                 break;
256             case 1:
257             case 2:
258             {
259                 if(locs->modrm_rm == modrm_use_sib) {
260                     e = makeSIBExpression(b);
261                 }
262                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
263                 if(opType == op_lea)
264                 {
265                     return disp_e;
266                 }
267                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
268             }
269             assert(0);
270             break;
271             case 3:
272                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, locs->rex_b));
273             default:
274                 return Expression::Ptr();
275         
276         };
277         // can't get here, but make the compiler happy...
278         assert(0);
279         return Expression::Ptr();
280     }
281
282     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
283                                                             bool isSigned)
284     {
285         // rex_w indicates we need to sign-extend also.
286         isSigned = isSigned || locs->rex_w;
287         
288         switch(opType)
289         {
290             case op_b:
291                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
292                 break;
293             case op_d:
294                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
295             case op_w:
296                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
297                 break;
298             case op_q:
299                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
300                 break;
301             case op_v:
302                 if (locs->rex_w || isDefault64Insn()) {
303                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
304                 }
305                 //if(!sizePrefixPresent)
306                 //{
307                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
308                     //}
309                     //else
310                     //{
311                     //return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
312                     //}
313                 break;
314             case op_z:
315                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
316                 // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
317                 //if(!addrSizePrefixPresent)
318                 //{
319                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
320                     //}
321                     //else
322                     //{
323                     //return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
324                     //}
325                 break;
326             case op_p:
327                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
328                 // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
329                 if(!sizePrefixPresent)
330                 {
331                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
332                 }
333                 else
334                 {
335                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
336                 }
337
338                 break;
339             case op_a:
340             case op_dq:
341             case op_pd:
342             case op_ps:
343             case op_s:
344             case op_si:
345             case op_lea:
346             case op_allgprs:
347             case op_512:
348             case op_c:
349                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
350                 return Expression::Ptr();
351             default:
352                 assert(!"Can't happen: opType out of range");
353                 return Expression::Ptr();
354         }
355     }
356     
357     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
358     {
359         int disp_pos;
360
361         if(locs->sib_position != -1)
362         {
363             disp_pos = locs->sib_position + 1;
364         }
365         else
366         {
367             disp_pos = locs->modrm_position + 1;
368         }
369         switch(locs->modrm_mod)
370         {
371             case 1:
372                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
373                         disp_pos)))));
374                 break;
375             case 2:
376                 if(0 && sizePrefixPresent)
377                 {
378                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
379                             disp_pos)))));
380                 }
381                 else
382                 {
383                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
384                             disp_pos)))));
385                 }
386                 break;
387             case 0:
388                 // In 16-bit mode, the word displacement is modrm r/m 6
389                 if(sizePrefixPresent && !ia32_is_mode_64())
390                 {
391                     if(locs->modrm_rm == 6)
392                     {
393                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
394                                            *((const dword_t*)(b.start + disp_pos)))));
395                     }
396                     // TODO FIXME; this was decoding wrong, but I'm not sure
397                     // why...
398                     else if (locs->modrm_rm == 5) {
399                         assert(b.start + disp_pos + 4 <= b.end);
400                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
401                                            *((const dword_t*)(b.start + disp_pos)))));
402                     } else {
403                         assert(b.start + disp_pos + 1 <= b.end);
404                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
405                     }
406                     break;
407                 }
408                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
409                 else
410                 {
411                     if(locs->modrm_rm == 5)
412                     {
413                         if (b.start + disp_pos + 4 <= b.end) 
414                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
415                                                *((const dword_t*)(b.start + disp_pos)))));
416                         else
417                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
418                     }
419                     else
420                     {
421                         if (b.start + disp_pos + 1 <= b.end)
422                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
423                         else
424                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
425                     }
426                     break;
427                 }
428             default:
429                 assert(b.start + disp_pos + 1 <= b.end);
430                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
431                 break;
432         }
433     }
434
435     enum intelRegBanks
436     {
437         b_8bitNoREX = 0,
438         b_16bit,
439         b_32bit,
440         b_segment,
441         b_64bit,
442         b_xmm_set0, /* XMM0 -> XMM 7 */
443         b_xmm_set1, /* XMM8 -> XMM 15 */
444         b_xmm_set2, /* XMM16 -> XMM 23 */
445         b_xmm_set3, /* XMM24 -> XMM 31 */
446         b_ymm_set0, /* YMM0 -> YMM 7 */
447         b_ymm_set1, /* YMM8 -> YMM 15 */
448         b_ymm_set2, /* YMM16 -> YMM 23 */
449         b_ymm_set3, /* YMM24 -> YMM 31 */
450         b_zmm_set0, /* ZMM0 -> ZMM 7 */
451         b_zmm_set1, /* ZMM8 -> ZMM 15 */
452         b_zmm_set2, /* ZMM16 -> ZMM 23 */
453         b_zmm_set3, /* ZMM24 -> ZMM 31 */
454         b_mm,
455         b_cr,
456         b_dr,
457         b_tr,
458         b_amd64ext,
459         b_8bitWithREX,
460         b_fpstack,
461         amd64_ext_8,
462         amd64_ext_16,
463         amd64_ext_32,
464
465         b_invalid /* should remain the final entry */
466     };
467
468     static MachRegister IntelRegTable32[][8] = {
469         { x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh }, /* b_8bitNoREX */
470         { x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di }, /* b_16bit */
471         { x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi }, /* b_32bit */
472         { x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg }, /* b_segment */
473         { x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi }, /* b_64bit */
474         { x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7 }, /* b_xmm_set0 */
475         { x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15 }, /* b_xmm_set1 */
476         { x86_64::xmm16, x86_64::xmm17, x86_64::xmm18, x86_64::xmm19, x86_64::xmm20, x86_64::xmm21, x86_64::xmm22, x86_64::xmm23 }, /* b_xmm_set2 */
477         { x86_64::xmm24, x86_64::xmm25, x86_64::xmm26, x86_64::xmm27, x86_64::xmm28, x86_64::xmm29, x86_64::xmm30, x86_64::xmm31 }, /* b_xmm_set3 */
478         { x86_64::ymm0, x86_64::ymm1, x86_64::ymm2, x86_64::ymm3, x86_64::ymm4, x86_64::ymm5, x86_64::ymm6, x86_64::ymm7 }, /* b_ymm_set0 */
479         { x86_64::ymm8, x86_64::ymm9, x86_64::ymm10, x86_64::ymm11, x86_64::ymm12, x86_64::ymm13, x86_64::ymm14, x86_64::ymm15 }, /* b_ymm_set1 */
480         { x86_64::ymm16, x86_64::ymm17, x86_64::ymm18, x86_64::ymm19, x86_64::ymm20, x86_64::ymm21, x86_64::ymm22, x86_64::ymm23 }, /* b_ymm_set2 */
481         { x86_64::ymm24, x86_64::ymm25, x86_64::ymm26, x86_64::ymm27, x86_64::ymm28, x86_64::ymm29, x86_64::ymm30, x86_64::ymm31 }, /* b_ymm_set3 */
482         { x86_64::zmm0, x86_64::zmm1, x86_64::zmm2, x86_64::zmm3, x86_64::zmm4, x86_64::zmm5, x86_64::zmm6, x86_64::zmm7 }, /* b_zmm_set0 */
483         { x86_64::zmm8, x86_64::zmm9, x86_64::zmm10, x86_64::zmm11, x86_64::zmm12, x86_64::zmm13, x86_64::zmm14, x86_64::zmm15 }, /* b_zmm_set1 */
484         { x86_64::zmm16, x86_64::zmm17, x86_64::zmm18, x86_64::zmm19, x86_64::zmm20, x86_64::zmm21, x86_64::zmm22, x86_64::zmm23 }, /* b_zmm_set2 */
485         { x86_64::zmm24, x86_64::zmm25, x86_64::zmm26, x86_64::zmm27, x86_64::zmm28, x86_64::zmm29, x86_64::zmm30, x86_64::zmm31 }, /* b_zmm_set3 */
486         { x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7 },
487         { x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7 },
488         { x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7 },
489         { x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7 },
490         { x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15 },
491         { x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil },
492         { x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7 }
493     };
494
495     static MachRegister IntelRegTable64[][8] = {
496         { x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh },
497         { x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di },
498         { x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi },
499         { x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg },
500         { x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi },
501         { x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7 }, /* b_xmm_set0 */
502         { x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15 }, /* b_xmm_set1 */
503         { x86_64::xmm16, x86_64::xmm17, x86_64::xmm18, x86_64::xmm19, x86_64::xmm20, x86_64::xmm21, x86_64::xmm22, x86_64::xmm23 }, /* b_xmm_set2 */
504         { x86_64::xmm24, x86_64::xmm25, x86_64::xmm26, x86_64::xmm27, x86_64::xmm28, x86_64::xmm29, x86_64::xmm30, x86_64::xmm31 }, /* b_xmm_set3 */
505         { x86_64::ymm0, x86_64::ymm1, x86_64::ymm2, x86_64::ymm3, x86_64::ymm4, x86_64::ymm5, x86_64::ymm6, x86_64::ymm7 }, /* b_ymm_set0 */
506         { x86_64::ymm8, x86_64::ymm9, x86_64::ymm10, x86_64::ymm11, x86_64::ymm12, x86_64::ymm13, x86_64::ymm14, x86_64::ymm15 }, /* b_ymm_set1 */
507         { x86_64::ymm16, x86_64::ymm17, x86_64::ymm18, x86_64::ymm19, x86_64::ymm20, x86_64::ymm21, x86_64::ymm22, x86_64::ymm23 }, /* b_ymm_set2 */
508         { x86_64::ymm24, x86_64::ymm25, x86_64::ymm26, x86_64::ymm27, x86_64::ymm28, x86_64::ymm29, x86_64::ymm30, x86_64::ymm31 }, /* b_ymm_set3 */
509         { x86_64::zmm0, x86_64::zmm1, x86_64::zmm2, x86_64::zmm3, x86_64::zmm4, x86_64::zmm5, x86_64::zmm6, x86_64::zmm7 }, /* b_zmm_set0 */
510         { x86_64::zmm8, x86_64::zmm9, x86_64::zmm10, x86_64::zmm11, x86_64::zmm12, x86_64::zmm13, x86_64::zmm14, x86_64::zmm15 }, /* b_zmm_set1 */
511         { x86_64::zmm16, x86_64::zmm17, x86_64::zmm18, x86_64::zmm19, x86_64::zmm20, x86_64::zmm21, x86_64::zmm22, x86_64::zmm23 }, /* b_zmm_set2 */
512         { x86_64::zmm24, x86_64::zmm25, x86_64::zmm26, x86_64::zmm27, x86_64::zmm28, x86_64::zmm29, x86_64::zmm30, x86_64::zmm31 }, /* b_zmm_set3 */
513         { x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7 },
514         { x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7 },
515         { x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7 },
516         { x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7 },
517         { x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15 },
518         { x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil },
519         { x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7 },
520             { x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b },
521             { x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w },
522             { x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d },
523     };
524
525   /* Uses the appropriate lookup table based on the 
526      decoder architecture */
527   class IntelRegTable_access {
528     public:
529         inline MachRegister operator()(Architecture arch,
530                                        intelRegBanks bank,
531                                        int index)
532         {
533             assert(index >= 0 && index < 8);
534     
535             if(arch == Arch_x86_64)
536                 return IntelRegTable64[bank][index];
537             else if(arch == Arch_x86) 
538             {
539               if(bank > b_fpstack) return InvalidReg;
540               return IntelRegTable32[bank][index];
541             }
542             assert(0);
543             return InvalidReg;
544         }
545
546   };
547   static IntelRegTable_access IntelRegTable;
548
549       bool InstructionDecoder_x86::isDefault64Insn()
550       {
551         switch(m_Operation->getID())
552         {
553         case e_jmp:
554         case e_pop:
555         case e_push:
556         case e_call:
557           return true;
558         default:
559           return false;
560         }
561         
562       }
563       
564
565     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
566                                         bool isExtendedReg)
567     {
568         MachRegister retVal;
569         
570
571         if(isExtendedReg)
572         {
573             switch(opType)
574             {
575                 case op_q:  
576                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
577                     break;
578                 case op_d:
579                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
580                     break;
581                 case op_w:
582                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
583                     break;
584                 case op_b:
585                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
586                     break;
587                 case op_v:
588                     if (locs->rex_w || isDefault64Insn())
589                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
590                     else if (!sizePrefixPresent)
591                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
592                     //else
593                     //    retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
594                     break;      
595                 case op_p:
596                 case op_z:
597                     //              if (!sizePrefixPresent)
598                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
599                         //                  else
600                         //  retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
601                     break;
602             case op_f:
603             case op_dbl:
604                 // extended reg ignored on FP regs
605                 retVal = IntelRegTable(m_Arch, b_fpstack,intelReg);
606                 break;
607                 default:
608                     retVal = InvalidReg;
609             }
610         }
611         /* Promotion to 64-bit only applies to the operand types
612            that are varible (c,v,z). Ignoring c and z because they
613            do the right thing on 32- and 64-bit code.
614         else if(locs->rex_w)
615         {
616             // AMD64 with 64-bit operands
617             retVal = IntelRegTable[b_64bit][intelReg];
618         }
619         */
620         else
621         {
622             switch(opType)
623             {
624                 case op_v:
625                   if(locs->rex_w || isDefault64Insn())
626                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
627                     else
628                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
629                     break;
630                 case op_b:
631                     if (locs->rex_byte & 0x40) {
632                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
633                     } else {
634                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
635                     }
636                     break;
637                 case op_q:
638                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
639                     break;
640                 case op_w:
641                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
642                     break;
643                 case op_f:
644                 case op_dbl:
645                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
646                     break;
647                 case op_d:
648                 case op_si:
649                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
650                     break;
651                 default:
652                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
653                     break;
654             }
655         }
656
657         if (!ia32_is_mode_64()) {
658           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
659             assert(0);
660         }
661
662         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
663     }
664     
665     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
666     {
667         switch(opType)
668         {
669             case op_b:
670             case op_c:
671                 return u8;
672             case op_d:
673             case op_ss:
674             case op_allgprs:
675             case op_si:
676                 return u32;
677             case op_w:
678             case op_a:
679                 return u16;
680             case op_q:
681             case op_sd:
682                 return u64;
683             case op_v:
684             case op_lea:
685             case op_z:
686                 if (locs->rex_w) 
687                 {
688                     return u64;
689                 }
690                 //if(ia32_is_mode_64() || !sizePrefixPresent)
691                 //{
692                     return u32;
693                     //}
694                     //else
695                     //{
696                     //return u16;
697                     //}
698                 break;
699             case op_y:
700                 if(ia32_is_mode_64())
701                         return u64;
702                 else
703                         return u32;
704                 break;
705             case op_p:
706                 // book says operand size; arch-x86 says word + word * operand size
707                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
708                 {
709                     return u48;
710                 }
711                 else
712                 {
713                     return u32;
714                 }
715             case op_dq:
716             case op_qq:
717                 return u64;
718             case op_512:
719                 return m512;
720             case op_pi:
721             case op_ps:
722             case op_pd:
723                 return dbl128;
724             case op_s:
725                 return u48;
726             case op_f:
727                 return sp_float;
728             case op_dbl:
729                 return dp_float;
730             case op_14:
731                 return m14;
732             default:
733                 assert(!"Can't happen!");
734                 return u8;
735         }
736     }
737
738     enum AVX_Regtype { AVX_XMM = 0, AVX_YMM, AVX_ZMM, AVX_NONE };
739     #define AVX_TYPE_OKAY(type) ((type) >= AVX_XMM && (type) <= AVX_ZMM)
740     /** 
741      * Decode an avx register based on the type of prefix. Returns true if the
742      * given configuration is invalid and should be rejected.
743      */
744     bool decodeAVX(intelRegBanks& bank, int* bank_index, int regnum, AVX_Regtype type)
745     {
746 #ifdef VEX_DEBUG
747         printf("VEX OPERAND:  REGNUM: %d  ", regnum);
748 #endif
749
750         /* Check to see if this is just a normal MMX register access */
751         if(type >= AVX_NONE || type < 0)
752         {
753 #ifdef VEX_DEBUG
754             printf("REG_TYPE: AVX_NONE (%d)\n", type);
755 #endif
756             /* Only registers XMM0 - XMM15 are usable */
757
758             /* The register must be valid */
759             if(regnum < 0) 
760                 return true;
761
762             if(regnum < 8)
763             {
764                 bank = b_xmm_set0;
765                 *bank_index = regnum;
766             } else if(regnum < 16)
767             {
768                 bank = b_xmm_set1;
769                 *bank_index = regnum - 8;
770             } else {
771                 /* Value is out of the valid range */
772                 return true;
773             }
774
775             /* Return success */
776             return false;
777         }
778
779         /* Operand is potentially XMM, YMM or ZMM */
780         int setnum = 0;
781         if(regnum < 8)
782         {
783             setnum = 0;
784             *bank_index = regnum;
785         } else if(regnum < 16)
786         {
787             setnum = 1;
788             *bank_index = regnum - 8;
789         } else if(regnum < 24)
790         {
791             setnum = 2;
792             *bank_index = regnum - 16;
793         } else if(regnum < 32){
794             setnum = 3;
795             *bank_index = regnum - 24;
796         } else {
797 #ifdef VEX_DEBUG
798             printf("AVX REGISTER NUMBER:   %d   is invalid!!\n", regnum);
799 #endif
800             return false;
801         }
802
803         switch(type)
804         {
805             case AVX_XMM:
806                 if(setnum == 0)
807                     bank = b_xmm_set0;
808                 else if(setnum == 1)
809                     bank = b_xmm_set1;
810                 else if(setnum == 2)
811                     bank = b_xmm_set2;
812                 else if(setnum == 3)
813                     bank = b_xmm_set3;
814                 else return true;
815                 break;
816             case AVX_YMM:
817                 if(setnum == 0)
818                     bank = b_ymm_set0;
819                 else if(setnum == 1)
820                     bank = b_ymm_set1;
821                 else if(setnum == 2)
822                     bank = b_ymm_set2;
823                 else if(setnum == 3)
824                     bank = b_ymm_set3;
825                 else return true;
826                 break;
827             case AVX_ZMM:
828                 if(setnum == 0)
829                     bank = b_zmm_set0;
830                 else if(setnum == 1)
831                     bank = b_zmm_set1;
832                 else if(setnum == 2)
833                     bank = b_zmm_set2;
834                 else if(setnum == 3)
835                     bank = b_zmm_set3;
836                 else return true;
837                 break;
838             default:
839                 return true;
840         }
841
842         /* Return Success */
843         return false;
844     }
845
846     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
847                                                   const ia32_operand& operand,
848                                                   int & imm_index, /* immediate operand index */
849                                                   const Instruction* insn_to_complete, bool isRead, bool isWritten)
850     {
851         bool isCFT = false;
852         bool isCall = false;
853         bool isConditional = false;
854         InsnCategory cat = insn_to_complete->getCategory();
855
856         if(cat == c_BranchInsn || cat == c_CallInsn)
857             {
858             isCFT = true;
859             if(cat == c_CallInsn)
860             {
861                 isCall = true;
862             }
863             }
864
865         if(cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) 
866         {
867                 isConditional = true;
868         }
869
870         unsigned int optype = operand.optype;
871         int vex_vvvv = 0; /* The register selected by the VEX prefix (1111 if unused) */
872         bool has_vex = false; /* Whether any sort of VEX prefix is present */
873         AVX_Regtype avx_type = AVX_NONE; /* The AVX register type (if VEX prefixed) */
874         intelRegBanks bank = b_invalid; /* Specifies an AVX bank to use for register decoding */
875         int bank_index = -1; /* Specifies a bank index for an AVX register */
876
877         if(decodedInstruction && decodedInstruction->getPrefix()->vex_prefix[0])
878         {
879             has_vex = true;
880
881             /* Get the AVX type from the prefix */
882             avx_type = (AVX_Regtype)decodedInstruction->getPrefix()->vex_ll;
883
884             if(decodedInstruction->getPrefix()->vex_prefix[2]) /* AVX512 (EVEX) */
885             {
886                 vex_vvvv = (unsigned char)EVEXGET_VVVV(decodedInstruction->getPrefix()->vex_prefix[1]);
887
888                 /* The last 5 bits must be flipped to be used for EVEX */
889                 vex_vvvv = (unsigned char)((~vex_vvvv) & 0x0F);
890             } else if(decodedInstruction->getPrefix()->vex_prefix[1]){ /* AVX2 (VEX3) */
891                 vex_vvvv = (unsigned char)VEXGET_VVVV(decodedInstruction->getPrefix()->vex_prefix[1]);
892
893                 /* The last 4 bits must be flipped to be used for VEX3 */
894                 vex_vvvv = (unsigned char)((~vex_vvvv) & 0x0F);
895             } else { /* AVX (VEX2) */
896                 vex_vvvv = (unsigned char)VEXGET_VVVV(decodedInstruction->getPrefix()->vex_prefix[0]);
897
898                 /* The last 4 bits must be flipped to be used for VEX2*/
899                 vex_vvvv = (unsigned char)((~vex_vvvv) & 0x0F);
900             }
901       }
902
903       if (sizePrefixPresent 
904         && ((optype == op_v) || (optype == op_z)) 
905         && (operand.admet != am_J)) 
906       {
907                 optype = op_w;
908       }
909
910         if(optype == op_y) 
911         {
912           if(ia32_is_mode_64() && locs->rex_w)
913             {
914                   optype = op_q;
915             } else {
916                   optype = op_d;
917       }
918         }
919      
920                 switch(operand.admet)
921                 {
922                     case 0:
923                     // No operand
924                         assert(!"Mismatched number of operands--check tables");
925                         return false;
926                     case am_A:
927                     {
928                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
929                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
930                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
931                     }
932                     break;
933                     case am_C:
934                     {
935                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
936                         insn_to_complete->appendOperand(op, isRead, isWritten);
937                     }
938                     break;
939                     case am_D:
940                     {
941                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
942                         insn_to_complete->appendOperand(op, isRead, isWritten);
943                     }
944                     break;
945                     case am_E:
946                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
947                     // mod of 0x03 specifies direct register access).
948                     case am_M:
949                     // am_R is the inverse of am_M; it should only have a mod of 3
950                     case am_R:
951                     // can be am_R or am_M      
952                     case am_RM: 
953                         if(isCFT)
954                         {
955                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
956                 } else {
957                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
958                         }
959                     break;
960                     case am_F:
961                     {
962                         Expression::Ptr op(makeRegisterExpression(x86::flags));
963                         insn_to_complete->appendOperand(op, isRead, isWritten);
964                     }
965                     break;
966                     case am_G:
967                     {
968                     Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg, optype, locs->rex_r)));
969                         insn_to_complete->appendOperand(op, isRead, isWritten);
970                     }
971                     break;
972             case am_H: /* Could be XMM, YMM or ZMM */
973                 /* Make sure this register class is valid for VEX */
974                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
975                     return false;
976
977                 /* Grab the correct bank and bank index for this type of register */
978                 if(decodeAVX(bank, &bank_index, vex_vvvv, avx_type))
979                     return false;
980
981                 /* Append the operand */
982                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
983                 break;
984             case am_XH: /* Must be XMM */
985                 /* Make sure we are using a valid VEX register class */
986                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
987                     return false;
988
989                 /* Constrain register type to only the XMM banks */
990                 avx_type = AVX_XMM;
991
992                 /* Grab the correct bank and bank index for this type of register */
993                 if(decodeAVX(bank, &bank_index, vex_vvvv, avx_type))
994                     return false;
995                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
996                 break;
997             case am_YH: /* Could be XMM or YMM */
998                 /* Make sure we are using a valid VEX register class */
999                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1000                     return false;
1001
1002                 /* Constrain to only XMM or YMM registers */
1003                 if(avx_type != AVX_XMM && avx_type != AVX_YMM)
1004                     avx_type = AVX_YMM;
1005
1006                 /* Grab the correct bank and bank index for this type of register */
1007                 if(decodeAVX(bank, &bank_index, vex_vvvv, avx_type))
1008                     return false;
1009
1010                 /* Append the operand */
1011                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1012                       break;
1013                     case am_I:
1014                 insn_to_complete->appendOperand(decodeImmediate(optype, b.start + locs->imm_position[imm_index++]), isRead, isWritten);
1015                         break;
1016                     case am_J:
1017                     {
1018                     Expression::Ptr Offset(decodeImmediate(optype, b.start + locs->imm_position[imm_index++], true));
1019                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
1020                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
1021                             decodedInstruction->getSize()))));
1022                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
1023
1024                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
1025                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
1026                         if (isConditional) 
1027                     {
1028                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
1029                     }
1030                 }
1031                     break;
1032                     case am_O:
1033                     {
1034                     // Address/offset width, which is *not* what's encoded by the optype...
1035                     // The deref's width is what's actually encoded here.
1036                         int pseudoOpType;
1037                         switch(locs->address_size)
1038                         {
1039                             case 1:
1040                                 pseudoOpType = op_b;
1041                                 break;
1042                             case 2:
1043                                 pseudoOpType = op_w;
1044                                 break;
1045                             case 4:
1046                                 pseudoOpType = op_d;
1047                                 break;
1048                             case 0:
1049                                 if(m_Arch == Arch_x86_64) {
1050                                     if(!addrSizePrefixPresent)
1051                                 {
1052                                         pseudoOpType = op_q;
1053                                 } else {
1054                                         pseudoOpType = op_d;
1055                                 }
1056                                 } else {
1057                                     pseudoOpType = op_v;
1058                                 }
1059                                 break;
1060                             default:
1061                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
1062                                 pseudoOpType = op_b;
1063                                 break;
1064                         }
1065
1066                         int offset_position = locs->opcode_position;
1067                     if(locs->modrm_position > offset_position && locs->modrm_operand < (int)(insn_to_complete->m_Operands.size()))
1068                         {
1069                             offset_position = locs->modrm_position;
1070                         }
1071                         if(locs->sib_position > offset_position)
1072                         {
1073                             offset_position = locs->sib_position;
1074                         }
1075                         offset_position++;
1076                         insn_to_complete->appendOperand(makeDereferenceExpression(
1077                     decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), isRead, isWritten);
1078                     }
1079                     break;
1080                     case am_P:
1081                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)), isRead, isWritten);
1082                         break;
1083                     case am_Q:
1084                         switch(locs->modrm_mod)
1085                         {
1086                             // direct dereference
1087                             case 0x00:
1088                             case 0x01:
1089                             case 0x02:
1090                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
1091                                 break;
1092                             case 0x03:
1093                                 // use of actual register
1094                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)), isRead, isWritten);
1095                                 break;
1096                             default:
1097                                 assert(!"2-bit value modrm_mod out of range");
1098                                 break;
1099                 }
1100                         break;
1101                     case am_S:
1102                     // Segment register in modrm reg field.
1103                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)), isRead, isWritten);
1104                         break;
1105                     case am_T:
1106                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
1107                         // NOTE: this only appears in deprecated opcodes
1108                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)), isRead, isWritten);
1109                         break;
1110                     case am_UM:
1111                         switch(locs->modrm_mod)
1112                         {
1113                         // direct dereference
1114                         case 0x00:
1115                         case 0x01:
1116                         case 0x02:
1117                         insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)), isRead, isWritten);
1118                                 break;
1119                         case 0x03:
1120                                 // use of actual register
1121                         decodeAVX(bank, &bank_index, locs->modrm_rm, AVX_XMM);
1122                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1123                                         break;
1124                         default:
1125                                 assert(!"2-bit value modrm_mod out of range");
1126                                 break;
1127                 }
1128           
1129                         break;
1130             case am_V: /* Could be XMM, YMM or ZMM (possibly non VEX)*/
1131                 /* Is this a vex prefixed instruction? */  
1132                 if(has_vex)
1133                 {
1134                     if(!AVX_TYPE_OKAY(avx_type))
1135                         return false;
1136                 }
1137
1138                 /* Get the register bank and the index */
1139                 if(decodeAVX(bank, &bank_index, locs->modrm_reg, avx_type))
1140                     return false;
1141     
1142                 /* Append the operand */
1143                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1144                 break;
1145             case am_XV: /* Must be XMM (must be VEX) */
1146                 
1147                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1148                     return false;
1149
1150                 /* Get the register bank and the index */
1151                 if(decodeAVX(bank, &bank_index, locs->modrm_reg, avx_type))
1152                     return false;
1153   
1154                 /* Append the operand */
1155                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1156                 break;
1157             case am_YV: /* Must be XMM or YMM (must be VEX) */
1158                 /* Make sure this register class is valid */
1159                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1160                     return false;
1161
1162                 /* Constrain to either XMM or YMM registers */
1163                 if(avx_type != AVX_XMM && avx_type != AVX_YMM)
1164                     avx_type = AVX_YMM;
1165
1166                 /* Get the register bank and index */
1167                 if(decodeAVX(bank, &bank_index, locs->modrm_reg, avx_type))
1168                     return false;
1169                        
1170                 /* Append the operand */
1171                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1172                         break;
1173             case am_U: /* Could be XMM, YMM, or ZMM (or possibly non VEX)*/
1174
1175                 /* Is this a vex prefixed instruction? */  
1176                 if(has_vex)
1177                 {
1178                     if(!AVX_TYPE_OKAY(avx_type))
1179                         return false;
1180                 }
1181
1182                 /* Grab the register bank and index */
1183                 if(decodeAVX(bank, &bank_index, locs->modrm_rm, AVX_XMM))
1184                     return false;
1185
1186                 /* Append the operand */
1187                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1188                 break;
1189             case am_XU: /* Must be XMM (must be VEX) */
1190                 /* Make sure this register class is valid */
1191                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1192                     return false;
1193   
1194                 /* Constrain register to XMM banks only */        
1195                 avx_type = AVX_XMM;
1196
1197                 /* Get the register bank and index for this register */
1198                 if(decodeAVX(bank, &bank_index, locs->modrm_rm, avx_type))
1199                     return false;
1200
1201                 /* Append the operand */
1202                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1203                 break;
1204             case am_YU: /* Must be XMM or YMM (must be VEX) */
1205                 /* Make sure this register class is valid */
1206                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1207                     return false;
1208
1209                 /* Constrain to either XMM or YMM registers */
1210                 if(avx_type != AVX_XMM && avx_type != AVX_YMM)
1211                     avx_type = AVX_YMM;
1212
1213                 /* Get the register bank and index */
1214                 if(decodeAVX(bank, &bank_index, locs->modrm_rm, avx_type))
1215                     return false;
1216
1217                 /* Append the operand */
1218                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1219                 break;
1220             case am_W: /* Could be XMM, YMM, or ZMM (or possibly not VEX) */
1221
1222                 if(has_vex)
1223                 {
1224                     if(!AVX_TYPE_OKAY(avx_type))
1225                         return false;
1226                 }
1227
1228                         switch(locs->modrm_mod)
1229                         {
1230                     /* Direct dereference */
1231                             case 0x00:
1232                             case 0x01:
1233                             case 0x02:
1234                                     insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)), isRead, isWritten);
1235                                 break;
1236                             case 0x03:
1237                         /* Just the register is used */
1238                         if(decodeAVX(bank, &bank_index, locs->modrm_rm, avx_type))
1239                             return false;
1240                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1241                         break;
1242                     default:
1243                         assert(!"2-bit value modrm_mod out of range");
1244                         break;
1245                 }
1246                 break;
1247             case am_XW: /* Must be XMM (must be VEX) */
1248
1249                 /* Make sure this vex is okay */
1250                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1251                     return false;
1252          
1253                 /* Constrain to the XMM banks */ 
1254                 avx_type = AVX_XMM;
1255
1256                 switch(locs->modrm_mod)
1257                             {
1258                     /* Direct dereference */
1259                     case 0x00:
1260                     case 0x01:
1261                     case 0x02:
1262                         insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)), isRead, isWritten);
1263                         break;
1264                     case 0x03:
1265                         /* Just the register is used */
1266                         if(decodeAVX(bank, &bank_index, locs->modrm_rm, avx_type))
1267                             return false;
1268                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1269                         break;
1270                     default:
1271                         assert(!"2-bit value modrm_mod out of range");
1272                                 break;
1273                             }
1274                 break;
1275             case am_YW: /* Must be either YMM or XMM (must be VEX) */
1276
1277                 /* Make sure the register class is okay and we have a vex prefix */
1278                 if(!AVX_TYPE_OKAY(avx_type) || !has_vex)
1279                     return false;
1280
1281                 /* Constrain to either XMM or YMM registers */
1282                 if(avx_type != AVX_XMM && avx_type != AVX_YMM)
1283                     avx_type = AVX_YMM;
1284
1285                 switch(locs->modrm_mod)
1286                 {
1287                     /* Direct dereference */
1288                     case 0x00:
1289                     case 0x01:
1290                     case 0x02:
1291                         insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)), isRead, isWritten);
1292                         break;
1293                     case 0x03:
1294                         /* Just the register is used */
1295                         if(decodeAVX(bank, &bank_index, locs->modrm_rm, avx_type))
1296                             return false;
1297
1298                         /* Append the operand */
1299                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch, bank, bank_index)), isRead, isWritten);
1300                         break;
1301                             default:
1302                                 assert(!"2-bit value modrm_mod out of range");
1303                                 break;
1304                 }
1305                         break;
1306                     case am_X:
1307                     {
1308                         MachRegister si_reg;
1309                         if(m_Arch == Arch_x86)
1310                         {
1311                                 if(addrSizePrefixPresent)
1312                                 {
1313                                         si_reg = x86::si;
1314                         } else {
1315                                         si_reg = x86::esi;
1316                                 }
1317                     } else {
1318                                 if(addrSizePrefixPresent)
1319                                 {
1320                                         si_reg = x86_64::esi;
1321                         } else {
1322                                         si_reg = x86_64::rsi;
1323                                 }
1324                         }
1325
1326                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1327                         Expression::Ptr si(makeRegisterExpression(si_reg));
1328                     Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))));
1329                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1330                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1331                     insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)), isRead, isWritten);
1332                     }
1333                     break;
1334                     case am_Y:
1335                     {
1336                         MachRegister di_reg;
1337                         if(m_Arch == Arch_x86)
1338                         {
1339                                 if(addrSizePrefixPresent)
1340                                 {
1341                                         di_reg = x86::di;
1342                         } else {
1343                                         di_reg = x86::edi;
1344                                 }
1345                     } else {
1346                                 if(addrSizePrefixPresent)
1347                                 {
1348                                         di_reg = x86_64::edi;
1349                         } else {
1350                                         di_reg = x86_64::rdi;
1351                                 }
1352                         }
1353                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1354                         Expression::Ptr di(makeRegisterExpression(di_reg));
1355                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1356                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1357                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1358                     insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)), isRead, isWritten);
1359                     }
1360                     break;
1361                     case am_tworeghack:
1362                         if(optype == op_edxeax)
1363                         {
1364                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1365                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1366                     Expression::Ptr highAddr = makeMultiplyExpression(edx, Immediate::makeImmediate(Result(u64, 2^32)), u64);
1367                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1368                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1369                             insn_to_complete->appendOperand(op, isRead, isWritten);
1370                 } else if (optype == op_ecxebx)
1371                         {
1372                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1373                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1374                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1375                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1376                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1377                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1378                             insn_to_complete->appendOperand(op, isRead, isWritten);
1379                         }
1380                     break;
1381                     
1382                     case am_reg:
1383                     {
1384                         MachRegister r(optype);
1385                         int size = r.size();
1386                     if((m_Arch == Arch_x86_64) && (r.regClass() == (unsigned int)x86::GPR) && (size == 4))
1387                         {
1388                             int reg_size = isDefault64Insn() ? op_q : op_v;
1389                             if(sizePrefixPresent)
1390                             {
1391                                 reg_size = op_w;
1392                             }
1393                             // implicit regs are not extended
1394                             r = makeRegisterID((r.val() & 0xFF), reg_size, false);
1395                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1396                             if(locs->rex_b && insn_to_complete->m_Operands.empty() &&
1397                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0)))
1398                             {
1399                                 r = MachRegister((r.val()) | x86_64::r8.val());
1400                                 assert(r.name() != "<INVALID_REG>");
1401                             }
1402                     } else {
1403                             r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1404                             
1405                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1406                             if(insn_to_complete->m_Operands.empty() && 
1407                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1408                             {
1409                                 unsigned int opcode_byte = *(b.start+locs->opcode_position);
1410                                 unsigned int reg_id = (opcode_byte & 0x07);
1411                                 if(locs->rex_b) 
1412                                 {
1413                                     // FP stack registers are not affected by the rex_b bit in AM_REG.
1414                                     if(r.regClass() == (unsigned) x86::GPR)
1415                                     {
1416                                         int reg_op_type = op_d;
1417                                         switch(size)
1418                                         {
1419                                         case 1:
1420                                             reg_op_type = op_b;
1421                                             break;
1422                                         case 2:
1423                                             reg_op_type = op_w;
1424                                             break;
1425                                         case 8:
1426                                             reg_op_type = op_q;
1427                                             break;
1428                                         default:
1429                                             break;
1430                                         }
1431
1432                                         r = makeRegisterID(reg_id, reg_op_type, true);
1433                                         assert(r.name() != "<INVALID_REG>");
1434                                     }
1435                             } else if((r.size() == 1) && (locs->rex_byte & 0x40))
1436                                 {
1437                                     r = makeRegisterID(reg_id, op_b, false);
1438                                     assert(r.name() != "<INVALID_REG>");
1439                                 }
1440                             }
1441
1442                         if(sizePrefixPresent && (r.regClass() == (unsigned int)x86::GPR) && r.size() >= 4)
1443                             {
1444                                 r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1445                                 assert(r.name() != "<INVALID_REG>");
1446                             }
1447                         }
1448                         Expression::Ptr op(makeRegisterExpression(r));
1449                         insn_to_complete->appendOperand(op, isRead, isWritten);
1450                     }
1451                     break;
1452                 case am_stackH:
1453                 case am_stackP:
1454                 // handled elsewhere
1455                     break;
1456                 case am_allgprs:
1457                     if(m_Arch == Arch_x86)
1458                     {
1459                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1460                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1461                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1462                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1463                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1464                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1465                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1466                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1467                 } else {
1468                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1469                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1470                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1471                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1472                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1473                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1474                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1475                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1476                     }
1477                     break;
1478             case am_ImplImm:
1479                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1480                   break;
1481                 default:
1482                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1483                     // assert(0);
1484                 return false;
1485         }
1486       
1487                 return true;
1488             }
1489
1490     extern ia32_entry invalid;
1491     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1492     {
1493         if(decodedInstruction == NULL)
1494         {
1495             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1496             assert(decodedInstruction);
1497         }
1498         if(locs == NULL)
1499         {
1500             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1501             assert(locs);
1502         }
1503         locs = new(locs) ia32_locations; //reinit();
1504         assert(locs->sib_position == -1);
1505         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1506         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1507         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1508         if (decodedInstruction->getPrefix()->rexW()) {
1509            // as per 2.2.1.2 - rex.w overrides 66h
1510            sizePrefixPresent = false;
1511         }
1512         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1513         static ia32_entry invalid = { e_No_Entry, 0, 0, false, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1514         if(decodedInstruction->getEntry()) {
1515             // check prefix validity
1516             // lock prefix only allowed on certain insns.
1517             // TODO: refine further to check memory written operand
1518             if(decodedInstruction->getPrefix()->getPrefix(0) == PREFIX_LOCK)
1519             {
1520                 switch(decodedInstruction->getEntry()->id)
1521                 {
1522                 case e_add:
1523                 case e_adc:
1524                 case e_and:
1525                 case e_btc:
1526                 case e_btr:
1527                 case e_bts:
1528                 case e_cmpxch:
1529                 case e_cmpxch8b:
1530                 case e_dec:
1531                 case e_inc:
1532                 case e_neg:
1533                 case e_not:
1534                 case e_or:
1535                 case e_sbb:
1536                 case e_sub:
1537                 case e_xor:
1538                 case e_xadd:
1539                 case e_xchg:
1540                     break;
1541                 default:
1542                     m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1543                                     decodedInstruction->getPrefix(), locs, m_Arch));
1544                     return;
1545                 }
1546             }
1547             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1548                                     decodedInstruction->getPrefix(), locs, m_Arch));
1549             
1550       } else {
1551                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1552                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1553                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1554                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1555                 // yell at the user.
1556             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1557                                     decodedInstruction->getPrefix(), locs, m_Arch));
1558         }
1559
1560     }
1561     
1562     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1563     {
1564         doIA32Decode(b);
1565         b.start += decodedInstruction->getSize();
1566     }
1567     
1568       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1569     {
1570        int imm_index = 0; // handle multiple immediate operands
1571         if(!decodedInstruction) return false;
1572         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1573         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1574
1575         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1576             decodedInstruction->getEntry()->getID() == e_ret_far) {
1577            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1578                                                                 ia32_is_mode_64() ? u64 : u32);
1579            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1580         }
1581
1582         for(int i = 0; i < 3; i++)
1583         {
1584             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1585                decodedInstruction->getEntry()->operands[i].optype == 0)
1586                 return true;
1587             if(!decodeOneOperand(b,
1588                                  decodedInstruction->getEntry()->operands[i], 
1589                                  imm_index, 
1590                                  insn_to_complete, 
1591                                  readsOperand(opsema, i),
1592                                  writesOperand(opsema, i)))
1593             {
1594                 return false;
1595             }
1596         }
1597
1598         /* Does this instruction have a 4th operand? */
1599         if((decodedInstruction->getEntry()->opsema & 0xFFFF) >= s4OP)
1600         {
1601           if(!decodeOneOperand(b,
1602             {am_I, op_b}, /* This is always an IMM8 */
1603             imm_index,
1604             insn_to_complete,
1605             readsOperand(opsema, 3),
1606             writesOperand(opsema, 3)))
1607             {
1608                 return false;
1609             }
1610         }
1611     
1612         return true;
1613     }
1614
1615     
1616       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1617     {
1618         return InstructionDecoderImpl::decode(b);
1619     }
1620     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1621     {
1622       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1623       //insn_to_complete->m_Operands.reserve(4);
1624       doIA32Decode(b);        
1625       decodeOperands(insn_to_complete);
1626     }
1627     
1628 };
1629 };
1630