Move dynutil/h to common/h; move common/h to common/src. Update CMakeLists.txt
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
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3  * 
4  * We provide the Paradyn Tools (below described as "Paradyn")
5  * on an AS IS basis, and do not warrant its validity or performance.
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20  * 
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22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
24  * Lesser General Public License for more details.
25  * 
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28  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
29  */
30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3R: // shld/shrd
74                 case s1RW2RW3R: // [i]div, cmpxch8b
75                 case s1R2R3R:
76                     return i == 0 || i == 1 || i == 2;
77                     break;
78                 case sNONE:
79                 default:
80                     return false;
81             }
82       
83         }
84       
85         bool writesOperand(unsigned int opsema, unsigned int i)
86         {
87             switch(opsema) {
88                 case s1R2R:
89                 case s1R:
90                     return false;
91                 case s1RW:
92                 case s1W:
93                     case s1W2R:   // second operand read, first operand written (e.g. mov)
94                         case s1RW2R:  // two operands read, first written (e.g. add)
95                             case s1W2R3R: // e.g. imul
96                                 case s1RW2R3R: // shld/shrd
97                                     return i == 0;
98                 case s1R2RW:
99                     return i == 1;
100                 case s1W2RW:
101                     case s1RW2RW: // e.g. xchg
102                         case s1W2RW3R: // some mul
103                             case s1W2W3R: // e.g. les
104                                 case s1RW2RW3R: // [i]div, cmpxch8b
105                                     return i == 0 || i == 1;
106                                     case s1W2R3RW: // (stack) push & pop
107                                         return i == 0 || i == 2;
108                 case sNONE:
109                 default:
110                     return false;
111             }
112         }
113
114
115     
116     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
117       InstructionDecoderImpl(a),
118     locs(NULL),
119     decodedInstruction(NULL),
120     sizePrefixPresent(false)
121     {
122       if(a == Arch_x86_64) setMode(true);
123       
124     }
125     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
126     {
127         if(decodedInstruction) decodedInstruction->~ia32_instruction();
128         free(decodedInstruction);
129         if(locs) locs->~ia32_locations();
130         free(locs);
131
132     }
133     static const unsigned char modrm_use_sib = 4;
134     
135     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
136     {
137         ia32_set_mode_64(is64);
138     }
139     
140       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
141     {
142         unsigned scale;
143         Register index;
144         Register base;
145         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
146
147         decode_SIB(locs->sib_byte, scale, index, base);
148
149         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
150         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
151                                     locs->rex_x))));
152         Expression::Ptr baseAST;
153         if(base == 0x05)
154         {
155             switch(locs->modrm_mod)
156             {
157                 case 0x00:
158                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
159                     break;
160                     case 0x01: {
161                         MachRegister reg;
162                         if (locs->rex_b)
163                             reg = x86_64::r13;
164                         else
165                           reg = MachRegister::getFramePointer(m_Arch);
166                         
167                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
168                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
169                                                     registerType);
170                         break;
171                     }
172                     case 0x02: {
173                         MachRegister reg;
174                         if (locs->rex_b)
175                             reg = x86_64::r13;
176                         else
177                             reg = MachRegister::getFramePointer(m_Arch);
178
179                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
180                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
181                                                     registerType);
182                         break;
183                     }
184                 case 0x03:
185                 default:
186                     assert(0);
187                     break;
188             };
189         }
190         else
191         {
192             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
193                                                                                                registerType,
194                                                                                                locs->rex_b)));
195         }
196         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
197         {
198             return baseAST;
199         }
200         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
201     }
202
203       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
204                                                                   unsigned int opType)
205     {
206        unsigned int regType = op_d;
207         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
208         if(ia32_is_mode_64())
209         {
210             regType = op_q;
211         }
212         Expression::Ptr e =
213             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
214         switch(locs->modrm_mod)
215         {
216             case 0:
217                 if(locs->modrm_rm == modrm_use_sib) {
218                     e = makeSIBExpression(b);
219                 }
220                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
221                 {
222                     assert(locs->opcode_position > -1);
223                     if(ia32_is_mode_64())
224                     {
225                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
226                                             getModRMDisplacement(b), aw);
227                     }
228                     else
229                     {
230                         e = getModRMDisplacement(b);
231                     }
232         
233                 }
234                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
235                 {
236                     e = getModRMDisplacement(b);
237                 }
238                 if(opType == op_lea)
239                 {
240                     return e;
241                 }
242                 return makeDereferenceExpression(e, makeSizeType(opType));
243                 assert(0);
244                 break;
245             case 1:
246             case 2:
247             {
248                 if(locs->modrm_rm == modrm_use_sib) {
249                     e = makeSIBExpression(b);
250                 }
251                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
252                 if(opType == op_lea)
253                 {
254                     return disp_e;
255                 }
256                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
257             }
258             assert(0);
259             break;
260             case 3:
261                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
262             default:
263                 return Expression::Ptr();
264         
265         };
266         // can't get here, but make the compiler happy...
267         assert(0);
268         return Expression::Ptr();
269     }
270
271     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
272                                                             bool isSigned)
273     {
274         switch(opType)
275         {
276             case op_b:
277                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
278                 break;
279             case op_d:
280                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
281             case op_w:
282                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
283                 break;
284             case op_q:
285                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
286                 break;
287             case op_v:
288               if (locs->rex_w) {
289                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
290               }
291             case op_z:
292         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
293         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
294               if(!sizePrefixPresent)
295               {
296                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
297               }
298               else
299               {
300                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
301               }
302               break;
303             case op_p:
304         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
305         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
306                 if(!sizePrefixPresent)
307                 {
308                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
309                 }
310                 else
311                 {
312                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
313                 }
314         
315                 break;
316             case op_a:
317             case op_dq:
318             case op_pd:
319             case op_ps:
320             case op_s:
321             case op_si:
322             case op_lea:
323             case op_allgprs:
324             case op_512:
325             case op_c:
326                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
327                 return Expression::Ptr();
328             default:
329                 assert(!"Can't happen: opType out of range");
330                 return Expression::Ptr();
331         }
332     }
333     
334     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
335     {
336         int disp_pos;
337
338         if(locs->sib_position != -1)
339         {
340             disp_pos = locs->sib_position + 1;
341         }
342         else
343         {
344             disp_pos = locs->modrm_position + 1;
345         }
346         switch(locs->modrm_mod)
347         {
348             case 1:
349                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
350                         disp_pos)))));
351                 break;
352             case 2:
353                 if(sizePrefixPresent)
354                 {
355                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
356                             disp_pos)))));
357                 }
358                 else
359                 {
360                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
361                             disp_pos)))));
362                 }
363                 break;
364             case 0:
365                 // In 16-bit mode, the word displacement is modrm r/m 6
366                 if(sizePrefixPresent)
367                 {
368                     if(locs->modrm_rm == 6)
369                     {
370                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
371                                            *((const dword_t*)(b.start + disp_pos)))));
372                     }
373                     // TODO FIXME; this was decoding wrong, but I'm not sure
374                     // why...
375                     else if (locs->modrm_rm == 5) {
376                         assert(b.start + disp_pos + 4 <= b.end);
377                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
378                                            *((const dword_t*)(b.start + disp_pos)))));
379                     } else {
380                         assert(b.start + disp_pos + 1 <= b.end);
381                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
382                     }
383                     break;
384                 }
385                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
386                 else
387                 {
388                     if(locs->modrm_rm == 5)
389                     {
390                         assert(b.start + disp_pos + 4 <= b.end);
391                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
392                                            *((const dword_t*)(b.start + disp_pos)))));
393                     }
394                     else
395                     {
396                         assert(b.start + disp_pos + 1 <= b.end);
397                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
398                     }
399                     break;
400                 }
401             default:
402                 assert(b.start + disp_pos + 1 <= b.end);
403                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
404                 break;
405         }
406     }
407
408     enum intelRegBanks
409     {
410         b_8bitNoREX = 0,
411         b_16bit,
412         b_32bit,
413         b_segment,
414         b_64bit,
415         b_xmm,
416         b_xmmhigh,
417         b_mm,
418         b_cr,
419         b_dr,
420         b_tr,
421         b_amd64ext,
422         b_8bitWithREX,
423         b_fpstack,
424         amd64_ext_8,
425         amd64_ext_16,
426         amd64_ext_32
427     };
428     static MachRegister IntelRegTable32[][8] = {
429         {
430             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
431         },
432         {
433             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
434         },
435         {
436             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
437         },
438         {
439            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
440         },
441         {
442             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
443         },
444         {
445             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
446         },
447         {
448             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
449         },
450         {
451             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
452         },
453         {
454             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
455         },
456         {
457             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
458         },
459         {
460             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
461         },
462         {
463             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
464         },
465         {
466             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
467         },
468         {
469             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
470         }
471
472     };
473     static MachRegister IntelRegTable64[][8] = {
474         {
475             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
476         },
477         {
478             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
479         },
480         {
481             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
482         },
483         {
484             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
485         },
486         {
487             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
488         },
489         {
490             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
491         },
492         {
493             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
494         },
495         {
496             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
497         },
498         {
499             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
500         },
501         {
502             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
503         },
504         {
505             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
506         },
507         {
508             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
509         },
510         {
511             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
512         },
513         {
514             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
515         },
516         {
517             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
518         },
519         {
520             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
521         },
522         {
523             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
524         }
525
526     };
527
528   /* Uses the appropriate lookup table based on the 
529      decoder architecture */
530   class IntelRegTable_access {
531     public:
532         inline MachRegister operator()(Architecture arch,
533                                        intelRegBanks bank,
534                                        int index)
535         {
536             assert(index >= 0 && index < 8);
537     
538             if(arch == Arch_x86_64)
539                 return IntelRegTable64[bank][index];
540             else if(arch == Arch_x86) 
541             {
542               assert(bank <= b_fpstack);
543               return IntelRegTable32[bank][index];
544             }
545             
546             else
547                 assert(0);
548             return IntelRegTable32[bank][index];
549         }
550
551   };
552   static IntelRegTable_access IntelRegTable;
553
554       bool InstructionDecoder_x86::isDefault64Insn()
555       {
556         switch(m_Operation->getID())
557         {
558         case e_jmp:
559         case e_pop:
560         case e_push:
561         case e_call:
562           return true;
563         default:
564           return false;
565         }
566         
567       }
568       
569
570     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
571                                         bool isExtendedReg)
572     {
573         MachRegister retVal;
574         
575
576         if(isExtendedReg)
577         {
578             switch(opType)
579             {
580                 case op_q:  
581                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
582                     break;
583                 case op_d:
584                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
585                     break;
586                 case op_w:
587                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
588                     break;
589                 case op_b:
590                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
591                     break;
592                 case op_v:
593                     if (locs->rex_w)
594                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
595                     else if (!sizePrefixPresent)
596                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
597                     else
598                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
599                     break;      
600                 case op_p:
601                 case op_z:
602                     if (!sizePrefixPresent)
603                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
604                     else
605                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
606                     break;
607                 default:
608                     fprintf(stderr, "%d\n", opType);
609                     fprintf(stderr, "%s\n",  decodedInstruction->getEntry()->name(locs));
610                     assert(0 && "opType=" && opType);
611             }
612         }
613         /* Promotion to 64-bit only applies to the operand types
614            that are varible (c,v,z). Ignoring c and z because they
615            do the right thing on 32- and 64-bit code.
616         else if(locs->rex_w)
617         {
618             // AMD64 with 64-bit operands
619             retVal = IntelRegTable[b_64bit][intelReg];
620         }
621         */
622         else
623         {
624             switch(opType)
625             {
626                 case op_v:
627                   if(locs->rex_w || isDefault64Insn())
628                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
629                     else
630                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
631                     break;
632                 case op_b:
633                     if (locs->rex_position == -1) {
634                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
635                     } else {
636                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
637                     }
638                     break;
639                 case op_q:
640                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
641                     break;
642                 case op_w:
643                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
644                     break;
645                 case op_f:
646                 case op_dbl:
647                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
648                     break;
649                 case op_d:
650                 case op_si:
651                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
652                     break;
653                 default:
654                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
655                     break;
656             }
657         }
658
659         if (!ia32_is_mode_64()) {
660           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
661             assert(0);
662         }
663
664         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
665     }
666     
667     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
668     {
669         switch(opType)
670         {
671             case op_b:
672             case op_c:
673                 return u8;
674             case op_d:
675             case op_ss:
676             case op_allgprs:
677             case op_si:
678                 return u32;
679             case op_w:
680             case op_a:
681                 return u16;
682             case op_q:
683             case op_sd:
684                 return u64;
685             case op_v:
686             case op_lea:
687             case op_z:
688               if(!ia32_is_mode_64() ^ sizePrefixPresent)
689                 {
690                     return u32;
691                 }
692                 else
693                 {
694                     return u16;
695                 }
696                 break;
697             case op_y:
698                 if(ia32_is_mode_64())
699                         return u64;
700                 else
701                         return u32;
702                 break;
703             case op_p:
704                 // book says operand size; arch-x86 says word + word * operand size
705                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
706                 {
707                     return u48;
708                 }
709                 else
710                 {
711                     return u32;
712                 }
713             case op_dq:
714                 return u64;
715             case op_512:
716                 return m512;
717             case op_pi:
718             case op_ps:
719             case op_pd:
720                 return dbl128;
721             case op_s:
722                 return u48;
723             case op_f:
724                 return sp_float;
725             case op_dbl:
726                 return dp_float;
727             case op_14:
728                 return m14;
729             default:
730                 assert(!"Can't happen!");
731                 return u8;
732         }
733     }
734
735
736     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
737                                                   const ia32_operand& operand,
738                                                   int & imm_index, /* immediate operand index */
739                                                   const Instruction* insn_to_complete, 
740                                                   bool isRead, bool isWritten)
741     {
742        bool isCFT = false;
743       bool isCall = false;
744       bool isConditional = false;
745       InsnCategory cat = insn_to_complete->getCategory();
746       if(cat == c_BranchInsn || cat == c_CallInsn)
747         {
748           isCFT = true;
749           if(cat == c_CallInsn)
750             {
751               isCall = true;
752             }
753         }
754       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
755         isConditional = true;
756       }
757
758       unsigned int optype = operand.optype;
759       if (sizePrefixPresent && 
760           ((optype == op_v) ||
761            (optype == op_z))) {
762         optype = op_w;
763       }
764       if(optype == op_y) {
765           if(ia32_is_mode_64() && locs->rex_w)
766                   optype = op_q;
767           else
768                   optype = op_d;
769       }
770                 switch(operand.admet)
771                 {
772                     case 0:
773                     // No operand
774                     {
775 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
776                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
777                             fprintf(stderr, "%x ", b.start[i]);
778                         }
779                         fprintf(stderr, "\n");*/
780                         assert(!"Mismatched number of operands--check tables");
781                         return false;
782                     }
783                     case am_A:
784                     {
785                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
786                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
787                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
788                     }
789                     break;
790                     case am_C:
791                     {
792                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
793                         insn_to_complete->appendOperand(op, isRead, isWritten);
794                     }
795                     break;
796                     case am_D:
797                     {
798                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
799                         insn_to_complete->appendOperand(op, isRead, isWritten);
800                     }
801                     break;
802                     case am_E:
803                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
804                     // mod of 0x03 specifies direct register access).
805                     case am_M:
806                     // am_R is the inverse of am_M; it should only have a mod of 3
807                     case am_R:
808                     // can be am_R or am_M      
809                     case am_RM: 
810                         if(isCFT)
811                         {
812                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
813                         }
814                         else
815                         {
816                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
817                         }
818                     break;
819                     case am_F:
820                     {
821                         Expression::Ptr op(makeRegisterExpression(x86::flags));
822                         insn_to_complete->appendOperand(op, isRead, isWritten);
823                     }
824                     break;
825                     case am_G:
826                     {
827                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
828                                 optype, locs->rex_r)));
829                         insn_to_complete->appendOperand(op, isRead, isWritten);
830                     }
831                     break;
832                     case am_I:
833                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
834                                                                         locs->imm_position[imm_index++]), 
835                                                         isRead, isWritten);
836                         break;
837                     case am_J:
838                     {
839                         Expression::Ptr Offset(decodeImmediate(optype, 
840                                                                b.start + locs->imm_position[imm_index++], 
841                                                                true));
842                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
843                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
844                             decodedInstruction->getSize()))));
845                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
846
847                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
848                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
849                         if (isConditional) 
850                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
851                     }
852                     break;
853                     case am_O:
854                     {
855                     // Address/offset width, which is *not* what's encoded by the optype...
856                     // The deref's width is what's actually encoded here.
857                         int pseudoOpType;
858                         switch(locs->address_size)
859                         {
860                             case 1:
861                                 pseudoOpType = op_b;
862                                 break;
863                             case 2:
864                                 pseudoOpType = op_w;
865                                 break;
866                             case 4:
867                                 pseudoOpType = op_d;
868                                 break;
869                             case 0:
870                                 // closest I can get to "will be address size by default"
871                                 pseudoOpType = op_v;
872                                 break;
873                             default:
874                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
875                                 pseudoOpType = op_b;
876                                 break;
877                         }
878
879
880                         int offset_position = locs->opcode_position;
881                         if(locs->modrm_position > offset_position && locs->modrm_operand <
882                            (int)(insn_to_complete->m_Operands.size()))
883                         {
884                             offset_position = locs->modrm_position;
885                         }
886                         if(locs->sib_position > offset_position)
887                         {
888                             offset_position = locs->sib_position;
889                         }
890                         offset_position++;
891                         insn_to_complete->appendOperand(makeDereferenceExpression(
892                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
893                                                         isRead, isWritten);
894                     }
895                     break;
896                     case am_P:
897                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
898                                 isRead, isWritten);
899                         break;
900                     case am_Q:
901         
902                         switch(locs->modrm_mod)
903                         {
904                             // direct dereference
905                             case 0x00:
906                             case 0x01:
907                             case 0x02:
908                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
909                                 break;
910                             case 0x03:
911                                 // use of actual register
912                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
913                                                                isRead, isWritten);
914                                 break;
915                             default:
916                                 assert(!"2-bit value modrm_mod out of range");
917                                 break;
918                         };
919                         break;
920                     case am_S:
921                     // Segment register in modrm reg field.
922                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
923                                 isRead, isWritten);
924                         break;
925                     case am_T:
926                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
927                         // NOTE: this only appears in deprecated opcodes
928                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
929                                                        isRead, isWritten);
930                         break;
931                     case am_UM:
932                         switch(locs->modrm_mod)
933                         {
934                         // direct dereference
935                         case 0x00:
936                         case 0x01:
937                         case 0x02:
938                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
939                                                 isRead, isWritten);
940                                 break;
941                         case 0x03:
942                                 // use of actual register
943                                 {
944                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
945                                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
946                                                         isRead, isWritten);
947                                         break;
948                                 }
949                         default:
950                                 assert(!"2-bit value modrm_mod out of range");
951                                 break;
952                         };
953                         break;
954                     case am_V:
955                        
956                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
957                                 (locs->rex_r == 1 )? b_xmmhigh : b_xmm,locs->modrm_reg)),
958                                     isRead, isWritten);
959                         break;
960                     case am_W:
961                         switch(locs->modrm_mod)
962                         {
963                             // direct dereference
964                             case 0x00:
965                             case 0x01:
966                             case 0x02:
967                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
968                                                                isRead, isWritten);
969                                 break;
970                             case 0x03:
971                             // use of actual register
972                             {
973                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
974                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
975                                         isRead, isWritten);
976                                 break;
977                             }
978                             default:
979                                 assert(!"2-bit value modrm_mod out of range");
980                                 break;
981                         };
982                         break;
983                     case am_X:
984                     {
985                         MachRegister si_reg;
986                         if(m_Arch == Arch_x86)
987                         {
988                                 if(addrSizePrefixPresent)
989                                 {
990                                         si_reg = x86::si;
991                                 } else
992                                 {
993                                         si_reg = x86::esi;
994                                 }
995                         }
996                         else
997                         {
998                                 if(addrSizePrefixPresent)
999                                 {
1000                                         si_reg = x86_64::esi;
1001                                 } else
1002                                 {
1003                                         si_reg = x86_64::rsi;
1004                                 }
1005                         }
1006                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1007                         Expression::Ptr si(makeRegisterExpression(si_reg));
1008                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1009                                 Result(u32, 0x10))));
1010                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1011                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1012                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1013                                                        isRead, isWritten);
1014                     }
1015                     break;
1016                     case am_Y:
1017                     {
1018                         MachRegister di_reg;
1019                         if(m_Arch == Arch_x86)
1020                         {
1021                                 if(addrSizePrefixPresent)
1022                                 {
1023                                         di_reg = x86::di;
1024                                 } else
1025                                 {
1026                                         di_reg = x86::edi;
1027                                 }
1028                         }
1029                         else
1030                         {
1031                                 if(addrSizePrefixPresent)
1032                                 {
1033                                         di_reg = x86_64::edi;
1034                                 } else
1035                                 {
1036                                         di_reg = x86_64::rdi;
1037                                 }
1038                         }
1039                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1040                         Expression::Ptr di(makeRegisterExpression(di_reg));
1041                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1042                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1043                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1044                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1045                                                        isRead, isWritten);
1046                     }
1047                     break;
1048                     case am_tworeghack:
1049                     {
1050                         if(optype == op_edxeax)
1051                         {
1052                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1053                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1054                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1055                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1056                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1057                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1058                             insn_to_complete->appendOperand(op, isRead, isWritten);
1059                         }
1060                         else if (optype == op_ecxebx)
1061                         {
1062                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1063                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1064                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1065                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1066                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1067                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1068                             insn_to_complete->appendOperand(op, isRead, isWritten);
1069                         }
1070                     }
1071                     break;
1072                     
1073                     case am_reg:
1074                     {
1075                         MachRegister r(optype);
1076                         r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1077                         entryID entryid = decodedInstruction->getEntry()->getID(locs);
1078                         if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1079                             (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1080                         {
1081                             // FP stack registers are not affected by the rex_b bit in AM_REG.
1082                            if(r.regClass() != (unsigned) x86::MMX)
1083                             {
1084                                 r = MachRegister((r.val()) | x86_64::r8.val());
1085                             }
1086                         }
1087                         if(sizePrefixPresent)
1088                         {
1089                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1090                         }
1091                         Expression::Ptr op(makeRegisterExpression(r));
1092                         insn_to_complete->appendOperand(op, isRead, isWritten);
1093                     }
1094                     break;
1095                 case am_stackH:
1096                 case am_stackP:
1097                 // handled elsewhere
1098                     break;
1099                 case am_allgprs:
1100                 {
1101                     if(m_Arch == Arch_x86)
1102                     {
1103                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1104                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1105                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1106                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1107                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1108                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1109                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1110                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1111                     }
1112                     else
1113                     {
1114                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1115                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1116                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1117                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1118                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1119                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1120                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1121                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1122                     }
1123                 }
1124                     break;
1125                 case am_ImplImm: {
1126                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1127                   break;
1128                 }
1129
1130                 default:
1131                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1132                         break;
1133                 };
1134                 return true;
1135             }
1136
1137     extern ia32_entry invalid;
1138     
1139     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1140     {
1141         if(decodedInstruction == NULL)
1142         {
1143             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1144             assert(decodedInstruction);
1145         }
1146         if(locs == NULL)
1147         {
1148             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1149             assert(locs);
1150         }
1151         locs = new(locs) ia32_locations; //reinit();
1152         assert(locs->sib_position == -1);
1153         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1154         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1155         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1156         if (decodedInstruction->getPrefix()->rexW()) {
1157            // as per 2.2.1.2 - rex.w overrides 66h
1158            sizePrefixPresent = false;
1159         }
1160         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1161     }
1162     
1163     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1164     {
1165         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1166         doIA32Decode(b);
1167         if(decodedInstruction->getEntry()) {
1168             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1169                                     decodedInstruction->getPrefix(), locs, m_Arch));
1170             
1171         }
1172         else
1173         {
1174                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1175                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1176                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1177                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1178                 // yell at the user.
1179             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1180                                     decodedInstruction->getPrefix(), locs, m_Arch));
1181         }
1182         b.start += decodedInstruction->getSize();
1183     }
1184     
1185       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1186     {
1187        int imm_index = 0; // handle multiple immediate operands
1188         if(!decodedInstruction) return false;
1189         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1190         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1191
1192         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1193             decodedInstruction->getEntry()->getID() == e_ret_far) {
1194            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1195                                                                 ia32_is_mode_64() ? u64 : u32);
1196            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1197         }
1198
1199         for(unsigned i = 0; i < 3; i++)
1200         {
1201             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1202                decodedInstruction->getEntry()->operands[i].optype == 0)
1203                 return true;
1204             if(!decodeOneOperand(b,
1205                                  decodedInstruction->getEntry()->operands[i], 
1206                                  imm_index, 
1207                                  insn_to_complete, 
1208                                  readsOperand(opsema, i),
1209                                  writesOperand(opsema, i)))
1210             {
1211                 return false;
1212             }
1213         }
1214     
1215         return true;
1216     }
1217
1218     
1219       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1220     {
1221         return InstructionDecoderImpl::decode(b);
1222     }
1223     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1224     {
1225       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1226       //insn_to_complete->m_Operands.reserve(4);
1227       doIA32Decode(b);        
1228       decodeOperands(insn_to_complete);
1229     }
1230     
1231 };
1232 };
1233