Warning cleanup from compiling with gcc 4.4-3 on new CHAOS systems
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
2  * Copyright (c) 1996-2011 Barton P. Miller
3  * 
4  * We provide the Paradyn Parallel Performance Tools (below
5  * described as "Paradyn") on an AS IS basis, and do not warrant its
6  * validity or performance.  We reserve the right to update, modify,
7  * or discontinue this software at any time.  We shall have no
8  * obligation to supply such updates or modifications or any other
9  * form of support to you.
10  * 
11  * By your use of Paradyn, you understand and agree that we (or any
12  * other person or entity with proprietary rights in Paradyn) are
13  * under no obligation to provide either maintenance services,
14  * update services, notices of latent defects, or correction of
15  * defects for Paradyn.
16  * 
17  * This library is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU Lesser General Public
19  * License as published by the Free Software Foundation; either
20  * version 2.1 of the License, or (at your option) any later version.
21  * 
22  * This library is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
25  * Lesser General Public License for more details.
26  * 
27  * You should have received a copy of the GNU Lesser General Public
28  * License along with this library; if not, write to the Free Software
29  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
30  */
31
32 #define INSIDE_INSTRUCTION_API
33
34 #include "common/h/Types.h"
35 #include "InstructionDecoder-x86.h"
36 #include "Expression.h"
37 #include "common/h/arch-x86.h"
38 #include "Register.h"
39 #include "Dereference.h"
40 #include "Immediate.h" 
41 #include "BinaryFunction.h"
42 #include "common/h/singleton_object_pool.h"
43
44 using namespace std;
45 using namespace NS_x86;
46 namespace Dyninst
47 {
48     namespace InstructionAPI
49     {
50     
51         bool readsOperand(unsigned int opsema, unsigned int i)
52         {
53             switch(opsema) {
54                 case s1R2R:
55                     return (i == 0 || i == 1);
56                 case s1R:
57                 case s1RW:
58                     return i == 0;
59                 case s1W:
60                     return false;
61                 case s1W2RW:
62                 case s1W2R:   // second operand read, first operand written (e.g. mov)
63                     return i == 1;
64                 case s1RW2R:  // two operands read, first written (e.g. add)
65                 case s1RW2RW: // e.g. xchg
66                 case s1R2RW:
67                     return i == 0 || i == 1;
68                 case s1W2R3R: // e.g. imul
69                 case s1W2RW3R: // some mul
70                 case s1W2R3RW: // (stack) push & pop
71                     return i == 1 || i == 2;
72                 case s1W2W3R: // e.g. les
73                     return i == 2;
74                 case s1RW2R3R: // shld/shrd
75                 case s1RW2RW3R: // [i]div, cmpxch8b
76                 case s1R2R3R:
77                     return i == 0 || i == 1 || i == 2;
78                     break;
79                 case sNONE:
80                 default:
81                     return false;
82             }
83       
84         }
85       
86         bool writesOperand(unsigned int opsema, unsigned int i)
87         {
88             switch(opsema) {
89                 case s1R2R:
90                 case s1R:
91                     return false;
92                 case s1RW:
93                 case s1W:
94                     case s1W2R:   // second operand read, first operand written (e.g. mov)
95                         case s1RW2R:  // two operands read, first written (e.g. add)
96                             case s1W2R3R: // e.g. imul
97                                 case s1RW2R3R: // shld/shrd
98                                     return i == 0;
99                 case s1R2RW:
100                     return i == 1;
101                 case s1W2RW:
102                     case s1RW2RW: // e.g. xchg
103                         case s1W2RW3R: // some mul
104                             case s1W2W3R: // e.g. les
105                                 case s1RW2RW3R: // [i]div, cmpxch8b
106                                     return i == 0 || i == 1;
107                                     case s1W2R3RW: // (stack) push & pop
108                                         return i == 0 || i == 2;
109                 case sNONE:
110                 default:
111                     return false;
112             }
113         }
114
115
116     
117     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
118       InstructionDecoderImpl(a),
119     locs(NULL),
120     decodedInstruction(NULL),
121     sizePrefixPresent(false)
122     {
123     }
124     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
125     {
126         if(decodedInstruction) decodedInstruction->~ia32_instruction();
127         free(decodedInstruction);
128         if(locs) locs->~ia32_locations();
129         free(locs);
130
131     }
132     static const unsigned char modrm_use_sib = 4;
133     
134     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
135     {
136         ia32_set_mode_64(is64);
137     }
138     
139       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
140     {
141         unsigned scale;
142         Register index;
143         Register base;
144         Result_Type registerType = ia32_is_mode_64() ? u32 : u64;
145
146         decode_SIB(locs->sib_byte, scale, index, base);
147
148         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
149         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
150                                     locs->rex_x))));
151         Expression::Ptr baseAST;
152         if(base == 0x05)
153         {
154             switch(locs->modrm_mod)
155             {
156                 case 0x00:
157                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1);
158                     break;
159                     case 0x01: {
160                         MachRegister reg;
161                         if (locs->rex_b)
162                             reg = x86_64::r13;
163                         else
164                           reg = MachRegister::getFramePointer(m_Arch);
165                         
166                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)),
167                                                     decodeImmediate(op_b, b.start + locs->sib_position + 1),
168                                                     registerType);
169                         break;
170                     }
171                     case 0x02: {
172                         MachRegister reg;
173                         if (locs->rex_b)
174                             reg = x86_64::r13;
175                         else
176                             reg = MachRegister::getFramePointer(m_Arch);
177
178                         baseAST = makeAddExpression(make_shared(singleton_object_pool<RegisterAST>::construct(reg)), 
179                                                     decodeImmediate(op_d, b.start + locs->sib_position + 1),
180                                                     registerType);
181                         break;
182                     }
183                 case 0x03:
184                 default:
185                     assert(0);
186                     break;
187             };
188         }
189         else
190         {
191             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
192                                                                                                registerType,
193                                                                                                locs->rex_b)));
194         }
195         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
196         {
197             return baseAST;
198         }
199         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
200     }
201
202       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
203                                                                   unsigned int opType)
204     {
205        unsigned int regType = op_d;
206         Result_Type aw = ia32_is_mode_64() ? u32 : u64;
207         if(ia32_is_mode_64())
208         {
209             regType = op_q;
210         }
211         Expression::Ptr e =
212             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, (locs->rex_b == 1)));
213         switch(locs->modrm_mod)
214         {
215             case 0:
216                 if(locs->modrm_rm == modrm_use_sib) {
217                     e = makeSIBExpression(b);
218                 }
219                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
220                 {
221                     assert(locs->opcode_position > -1);
222                     if(ia32_is_mode_64())
223                     {
224                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
225                                             getModRMDisplacement(b), aw);
226                     }
227                     else
228                     {
229                         e = getModRMDisplacement(b);
230                     }
231         
232                 }
233                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
234                 {
235                     e = getModRMDisplacement(b);
236                 }
237                 if(opType == op_lea)
238                 {
239                     return e;
240                 }
241                 return makeDereferenceExpression(e, makeSizeType(opType));
242                 assert(0);
243                 break;
244             case 1:
245             case 2:
246             {
247                 if(locs->modrm_rm == modrm_use_sib) {
248                     e = makeSIBExpression(b);
249                 }
250                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
251                 if(opType == op_lea)
252                 {
253                     return disp_e;
254                 }
255                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
256             }
257             assert(0);
258             break;
259             case 3:
260                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, (locs->rex_b == 1)));
261             default:
262                 return Expression::Ptr();
263         
264         };
265         // can't get here, but make the compiler happy...
266         assert(0);
267         return Expression::Ptr();
268     }
269
270     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
271                                                             bool isSigned)
272     {
273         switch(opType)
274         {
275             case op_b:
276                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
277                 break;
278             case op_d:
279                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
280             case op_w:
281                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
282                 break;
283             case op_q:
284                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
285                 break;
286             case op_v:
287             case op_z:
288         // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
289         // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
290                 if(!sizePrefixPresent)
291                 {
292                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
293                 }
294                 else
295                 {
296                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
297                 }
298         
299                 break;
300             case op_p:
301         // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
302         // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
303                 if(!sizePrefixPresent)
304                 {
305                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
306                 }
307                 else
308                 {
309                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
310                 }
311         
312                 break;
313             case op_a:
314             case op_dq:
315             case op_pd:
316             case op_ps:
317             case op_s:
318             case op_si:
319             case op_lea:
320             case op_allgprs:
321             case op_512:
322             case op_c:
323                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
324                 return Expression::Ptr();
325             default:
326                 assert(!"Can't happen: opType out of range");
327                 return Expression::Ptr();
328         }
329     }
330     
331     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
332     {
333         int disp_pos;
334
335         if(locs->sib_position != -1)
336         {
337             disp_pos = locs->sib_position + 1;
338         }
339         else
340         {
341             disp_pos = locs->modrm_position + 1;
342         }
343         switch(locs->modrm_mod)
344         {
345             case 1:
346                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
347                         disp_pos)))));
348                 break;
349             case 2:
350                 if(sizePrefixPresent)
351                 {
352                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
353                             disp_pos)))));
354                 }
355                 else
356                 {
357                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
358                             disp_pos)))));
359                 }
360                 break;
361             case 0:
362                 // In 16-bit mode, the word displacement is modrm r/m 6
363                 if(sizePrefixPresent)
364                 {
365                     if(locs->modrm_rm == 6)
366                     {
367                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
368                                            *((const dword_t*)(b.start + disp_pos)))));
369                     }
370                     // TODO FIXME; this was decoding wrong, but I'm not sure
371                     // why...
372                     else if (locs->modrm_rm == 5) {
373                         assert(b.start + disp_pos + 4 <= b.end);
374                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
375                                            *((const dword_t*)(b.start + disp_pos)))));
376                     } else {
377                         assert(b.start + disp_pos + 1 <= b.end);
378                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
379                     }
380                     break;
381                 }
382                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
383                 else
384                 {
385                     if(locs->modrm_rm == 5)
386                     {
387                         assert(b.start + disp_pos + 4 <= b.end);
388                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
389                                            *((const dword_t*)(b.start + disp_pos)))));
390                     }
391                     else
392                     {
393                         assert(b.start + disp_pos + 1 <= b.end);
394                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
395                     }
396                     break;
397                 }
398             default:
399                 assert(b.start + disp_pos + 1 <= b.end);
400                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
401                 break;
402         }
403     }
404
405     enum intelRegBanks
406     {
407         b_8bitNoREX = 0,
408         b_16bit,
409         b_32bit,
410         b_segment,
411         b_64bit,
412         b_xmm,
413         b_xmmhigh,
414         b_mm,
415         b_cr,
416         b_dr,
417         b_tr,
418         b_amd64ext,
419         b_8bitWithREX,
420         b_fpstack
421     };
422     static MachRegister IntelRegTable32[][8] = {
423         {
424             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
425         },
426         {
427             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
428         },
429         {
430             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
431         },
432         {
433            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
434         },
435         {
436             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
437         },
438         {
439             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
440         },
441         {
442             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
443         },
444         {
445             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
446         },
447         {
448             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
449         },
450         {
451             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
452         },
453         {
454             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
455         },
456         {
457             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
458         },
459         {
460             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
461         },
462         {
463             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
464         }
465
466     };
467     static MachRegister IntelRegTable64[][8] = {
468         {
469             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
470         },
471         {
472             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
473         },
474         {
475             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
476         },
477         {
478             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
479         },
480         {
481             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
482         },
483         {
484             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
485         },
486         {
487             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
488         },
489         {
490             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
491         },
492         {
493             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
494         },
495         {
496             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
497         },
498         {
499             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
500         },
501         {
502             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
503         },
504         {
505             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
506         },
507         {
508             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
509         }
510
511     };
512
513   /* Uses the appropriate lookup table based on the 
514      decoder architecture */
515   class IntelRegTable_access {
516     public:
517         inline MachRegister operator()(Architecture arch,
518                                        intelRegBanks bank,
519                                        int index)
520         {
521             assert(index >= 0 && index < 8);
522     
523             if(arch == Arch_x86_64)
524                 return IntelRegTable64[bank][index];
525             else if(arch == Arch_x86)
526                 return IntelRegTable32[bank][index];
527             else
528                 assert(0);
529             return IntelRegTable32[bank][index];
530         }
531
532   };
533   static IntelRegTable_access IntelRegTable;
534
535     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
536                                         bool isExtendedReg)
537     {
538         MachRegister retVal;
539
540         if(isExtendedReg)
541         {
542             retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
543         }
544         /* Promotion to 64-bit only applies to the operand types
545            that are varible (c,v,z). Ignoring c and z because they
546            do the right thing on 32- and 64-bit code.
547         else if(locs->rex_w)
548         {
549             // AMD64 with 64-bit operands
550             retVal = IntelRegTable[b_64bit][intelReg];
551         }
552         */
553         else
554         {
555             switch(opType)
556             {
557                 case op_v:
558                     if(locs->rex_w)
559                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
560                     else
561                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
562                     break;
563                 case op_b:
564                     if (locs->rex_position == -1) {
565                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
566                     } else {
567                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
568                     }
569                     break;
570                 case op_q:
571                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
572                     break;
573                 case op_w:
574                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
575                     break;
576                 case op_f:
577                 case op_dbl:
578                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
579                     break;
580                 case op_d:
581                 case op_si:
582                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
583                     break;
584                 default:
585                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
586                     break;
587             }
588         }
589
590         if (!ia32_is_mode_64()) {
591           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
592             assert(0);
593         }
594
595         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
596     }
597     
598     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
599     {
600         switch(opType)
601         {
602             case op_b:
603             case op_c:
604                 return u8;
605             case op_d:
606             case op_ss:
607             case op_allgprs:
608             case op_si:
609                 return u32;
610             case op_w:
611             case op_a:
612                 return u16;
613             case op_q:
614             case op_sd:
615                 return u64;
616             case op_v:
617             case op_lea:
618             case op_z:
619               if(!ia32_is_mode_64() ^ sizePrefixPresent)
620                 {
621                     return u32;
622                 }
623                 else
624                 {
625                     return u16;
626                 }
627                 break;
628             case op_p:
629                 // book says operand size; arch-x86 says word + word * operand size
630                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
631                 {
632                     return u48;
633                 }
634                 else
635                 {
636                     return u32;
637                 }
638             case op_dq:
639                 return u64;
640             case op_512:
641                 return m512;
642             case op_pi:
643             case op_ps:
644             case op_pd:
645                 return dbl128;
646             case op_s:
647                 return u48;
648             case op_f:
649                 return sp_float;
650             case op_dbl:
651                 return dp_float;
652             case op_14:
653                 return m14;
654             default:
655                 assert(!"Can't happen!");
656                 return u8;
657         }
658     }
659
660
661     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
662                                                   const ia32_operand& operand,
663                                                   int & imm_index, /* immediate operand index */
664                                                   const Instruction* insn_to_complete, 
665                                                   bool isRead, bool isWritten)
666     {
667        bool isCFT = false;
668       bool isCall = false;
669       bool isConditional = false;
670       InsnCategory cat = insn_to_complete->getCategory();
671       if(cat == c_BranchInsn || cat == c_CallInsn)
672         {
673           isCFT = true;
674           if(cat == c_CallInsn)
675             {
676               isCall = true;
677             }
678         }
679       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
680         isConditional = true;
681       }
682
683       unsigned int optype = operand.optype;
684       if (sizePrefixPresent && 
685           ((optype == op_v) ||
686            (optype == op_z))) {
687         optype = op_w;
688       }
689                 switch(operand.admet)
690                 {
691                     case 0:
692                     // No operand
693                     {
694 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
695                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
696                             fprintf(stderr, "%x ", b.start[i]);
697                         }
698                         fprintf(stderr, "\n");*/
699                         assert(!"Mismatched number of operands--check tables");
700                         return false;
701                     }
702                     case am_A:
703                     {
704                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
705                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
706                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
707                     }
708                     break;
709                     case am_C:
710                     {
711                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
712                         insn_to_complete->appendOperand(op, isRead, isWritten);
713                     }
714                     break;
715                     case am_D:
716                     {
717                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
718                         insn_to_complete->appendOperand(op, isRead, isWritten);
719                     }
720                     break;
721                     case am_E:
722                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
723                     // mod of 0x03 specifies direct register access).
724                     case am_M:
725                     // am_R is the inverse of am_M; it should only have a mod of 3
726                     case am_R:
727                         if(isCFT)
728                         {
729                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
730                         }
731                         else
732                         {
733                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
734                         }
735                     break;
736                     case am_F:
737                     {
738                         Expression::Ptr op(makeRegisterExpression(x86::flags));
739                         insn_to_complete->appendOperand(op, isRead, isWritten);
740                     }
741                     break;
742                     case am_G:
743                     {
744                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
745                                 optype, locs->rex_r)));
746                         insn_to_complete->appendOperand(op, isRead, isWritten);
747                     }
748                     break;
749                     case am_I:
750                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
751                                                                         locs->imm_position[imm_index++]), 
752                                                         isRead, isWritten);
753                         break;
754                     case am_J:
755                     {
756                         Expression::Ptr Offset(decodeImmediate(optype, 
757                                                                b.start + locs->imm_position[imm_index++], 
758                                                                true));
759                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
760                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
761                             decodedInstruction->getSize()))));
762                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
763
764                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
765                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
766                         if (isConditional) 
767                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
768                     }
769                     break;
770                     case am_O:
771                     {
772                     // Address/offset width, which is *not* what's encoded by the optype...
773                     // The deref's width is what's actually encoded here.
774                         int pseudoOpType;
775                         switch(locs->address_size)
776                         {
777                             case 1:
778                                 pseudoOpType = op_b;
779                                 break;
780                             case 2:
781                                 pseudoOpType = op_w;
782                                 break;
783                             case 4:
784                                 pseudoOpType = op_d;
785                                 break;
786                             case 0:
787                                 // closest I can get to "will be address size by default"
788                                 pseudoOpType = op_v;
789                                 break;
790                             default:
791                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
792                                 pseudoOpType = op_b;
793                                 break;
794                         }
795
796
797                         int offset_position = locs->opcode_position;
798                         if(locs->modrm_position > offset_position && locs->modrm_operand <
799                            (int)(insn_to_complete->m_Operands.size()))
800                         {
801                             offset_position = locs->modrm_position;
802                         }
803                         if(locs->sib_position > offset_position)
804                         {
805                             offset_position = locs->sib_position;
806                         }
807                         offset_position++;
808                         insn_to_complete->appendOperand(makeDereferenceExpression(
809                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
810                                                         isRead, isWritten);
811                     }
812                     break;
813                     case am_P:
814                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
815                                 isRead, isWritten);
816                         break;
817                     case am_Q:
818         
819                         switch(locs->modrm_mod)
820                         {
821                             // direct dereference
822                             case 0x00:
823                             case 0x01:
824                             case 0x02:
825                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
826                                 break;
827                             case 0x03:
828                                 // use of actual register
829                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
830                                                                isRead, isWritten);
831                                 break;
832                             default:
833                                 assert(!"2-bit value modrm_mod out of range");
834                                 break;
835                         };
836                         break;
837                     case am_S:
838                     // Segment register in modrm reg field.
839                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
840                                 isRead, isWritten);
841                         break;
842                     case am_T:
843                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
844                         // NOTE: this only appears in deprecated opcodes
845                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
846                                                        isRead, isWritten);
847                         break;
848                     case am_V:
849                        
850                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
851                                 (locs->rex_r == 1 )? b_xmmhigh : b_xmm,locs->modrm_reg)),
852                                     isRead, isWritten);
853                         break;
854                     case am_W:
855                         switch(locs->modrm_mod)
856                         {
857                             // direct dereference
858                             case 0x00:
859                             case 0x01:
860                             case 0x02:
861                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
862                                                                isRead, isWritten);
863                                 break;
864                             case 0x03:
865                             // use of actual register
866                             {
867                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
868                                         (locs->rex_b == 1) ? b_xmmhigh : b_xmm, locs->modrm_rm)),
869                                         isRead, isWritten);
870                                 break;
871                             }
872                             default:
873                                 assert(!"2-bit value modrm_mod out of range");
874                                 break;
875                         };
876                         break;
877                     case am_X:
878                     {
879                         MachRegister si_reg;
880                         if(m_Arch == Arch_x86)
881                         {
882                                 if(addrSizePrefixPresent)
883                                 {
884                                         si_reg = x86::si;
885                                 } else
886                                 {
887                                         si_reg = x86::esi;
888                                 }
889                         }
890                         else
891                         {
892                                 if(addrSizePrefixPresent)
893                                 {
894                                         si_reg = x86_64::esi;
895                                 } else
896                                 {
897                                         si_reg = x86_64::rsi;
898                                 }
899                         }
900                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
901                         Expression::Ptr si(makeRegisterExpression(si_reg));
902                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
903                                 Result(u32, 0x10))));
904                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
905                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
906                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
907                                                        isRead, isWritten);
908                     }
909                     break;
910                     case am_Y:
911                     {
912                         MachRegister di_reg;
913                         if(m_Arch == Arch_x86)
914                         {
915                                 if(addrSizePrefixPresent)
916                                 {
917                                         di_reg = x86::di;
918                                 } else
919                                 {
920                                         di_reg = x86::edi;
921                                 }
922                         }
923                         else
924                         {
925                                 if(addrSizePrefixPresent)
926                                 {
927                                         di_reg = x86_64::edi;
928                                 } else
929                                 {
930                                         di_reg = x86_64::rdi;
931                                 }
932                         }
933                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
934                         Expression::Ptr di(makeRegisterExpression(di_reg));
935                         Expression::Ptr es_segment = makeMultiplyExpression(es,
936                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
937                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
938                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
939                                                        isRead, isWritten);
940                     }
941                     break;
942                     case am_tworeghack:
943                     {
944                         if(optype == op_edxeax)
945                         {
946                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
947                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
948                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
949                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
950                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
951                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
952                             insn_to_complete->appendOperand(op, isRead, isWritten);
953                         }
954                         else if (optype == op_ecxebx)
955                         {
956                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
957                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
958                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
959                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
960                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
961                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
962                             insn_to_complete->appendOperand(op, isRead, isWritten);
963                         }
964                     }
965                     break;
966                     
967                     case am_reg:
968                     {
969                         MachRegister r(optype);
970                         r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
971                         if(locs->rex_b && insn_to_complete->m_Operands.empty())
972                         {
973                             // FP stack registers are not affected by the rex_b bit in AM_REG.
974                            if((signed int) r.regClass() != x86::MMX)
975                             {
976                                 r = MachRegister((r.val()) | x86_64::r8.val());
977                             }
978                         }
979                         if(sizePrefixPresent)
980                         {
981                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
982                         }
983                         Expression::Ptr op(makeRegisterExpression(r));
984                         insn_to_complete->appendOperand(op, isRead, isWritten);
985                     }
986                     break;
987                 case am_stackH:
988                 case am_stackP:
989                 // handled elsewhere
990                     break;
991                 case am_allgprs:
992                 {
993                     if(m_Arch == Arch_x86)
994                     {
995                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
996                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
997                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
998                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
999                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1000                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1001                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1002                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1003                     }
1004                     else
1005                     {
1006                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1007                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1008                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1009                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1010                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1011                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1012                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1013                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1014                     }
1015                 }
1016                     break;
1017                 case am_ImplImm: {
1018                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1019                   break;
1020                 }
1021
1022                 default:
1023                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1024                         break;
1025                 };
1026                 return true;
1027             }
1028
1029     extern ia32_entry invalid;
1030     
1031     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1032     {
1033         if(decodedInstruction == NULL)
1034         {
1035             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1036             assert(decodedInstruction);
1037         }
1038         if(locs == NULL)
1039         {
1040             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1041             assert(locs);
1042         }
1043         locs = new(locs) ia32_locations; //reinit();
1044         assert(locs->sib_position == -1);
1045         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1046         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1047         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1048         if (decodedInstruction->getPrefix()->rexW()) {
1049            // as per 2.2.1.2 - rex.w overrides 66h
1050            sizePrefixPresent = false;
1051         }
1052         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1053     }
1054     
1055     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1056     {
1057         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1058         doIA32Decode(b);
1059         if(decodedInstruction->getEntry()) {
1060             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1061                                     decodedInstruction->getPrefix(), locs, m_Arch));
1062         }
1063         else
1064         {
1065                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1066                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1067                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1068                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1069                 // yell at the user.
1070             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1071                                     decodedInstruction->getPrefix(), locs, m_Arch));
1072         }
1073         b.start += decodedInstruction->getSize();
1074     }
1075     
1076       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1077     {
1078        int imm_index = 0; // handle multiple immediate operands
1079         if(!decodedInstruction) return false;
1080         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1081         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1082         
1083         for(unsigned i = 0; i < 3; i++)
1084         {
1085             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1086                decodedInstruction->getEntry()->operands[i].optype == 0)
1087                 return true;
1088             if(!decodeOneOperand(b,
1089                                  decodedInstruction->getEntry()->operands[i], 
1090                                  imm_index, 
1091                                  insn_to_complete, 
1092                                  readsOperand(opsema, i),
1093                                  writesOperand(opsema, i)))
1094             {
1095                 return false;
1096             }
1097         }
1098     
1099         return true;
1100     }
1101
1102     
1103       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1104     {
1105         return InstructionDecoderImpl::decode(b);
1106     }
1107     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1108     {
1109       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1110       //insn_to_complete->m_Operands.reserve(4);
1111       doIA32Decode(b);        
1112       decodeOperands(insn_to_complete);
1113     }
1114     
1115 };
1116 };
1117