Dyninst can now use am_H addressing mode
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
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3  * 
4  * We provide the Paradyn Tools (below described as "Paradyn")
5  * on an AS IS basis, and do not warrant its validity or performance.
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13  * update services, notices of latent defects, or correction of
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19  * version 2.1 of the License, or (at your option) any later version.
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23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
24  * Lesser General Public License for more details.
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29  */
30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3R: // shld/shrd
74                 case s1RW2RW3R: // [i]div, cmpxch8b
75                 case s1R2R3R:
76                     return i == 0 || i == 1 || i == 2;
77                     break;
78                 case sNONE:
79                 default:
80                     return false;
81             }
82       
83         }
84       
85         bool writesOperand(unsigned int opsema, unsigned int i)
86         {
87             switch(opsema) {
88                 case s1R2R:
89                 case s1R:
90                     return false;
91                 case s1RW:
92                 case s1W:
93                     case s1W2R:   // second operand read, first operand written (e.g. mov)
94                         case s1RW2R:  // two operands read, first written (e.g. add)
95                             case s1W2R3R: // e.g. imul
96                                 case s1RW2R3R: // shld/shrd
97                                     return i == 0;
98                 case s1R2RW:
99                     return i == 1;
100                 case s1W2RW:
101                     case s1RW2RW: // e.g. xchg
102                         case s1W2RW3R: // some mul
103                             case s1W2W3R: // e.g. les
104                                 case s1RW2RW3R: // [i]div, cmpxch8b
105                                     return i == 0 || i == 1;
106                                     case s1W2R3RW: // (stack) push & pop
107                                         return i == 0 || i == 2;
108                 case sNONE:
109                 default:
110                     return false;
111             }
112         }
113
114
115     
116     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
117       InstructionDecoderImpl(a),
118     locs(NULL),
119     decodedInstruction(NULL),
120     sizePrefixPresent(false),
121     addrSizePrefixPresent(false)
122     {
123       if(a == Arch_x86_64) setMode(true);
124       
125     }
126     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
127     {
128         if(decodedInstruction) decodedInstruction->~ia32_instruction();
129         free(decodedInstruction);
130         if(locs) locs->~ia32_locations();
131         free(locs);
132
133     }
134     static const unsigned char modrm_use_sib = 4;
135     
136     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
137     {
138         ia32_set_mode_64(is64);
139     }
140     
141       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
142     {
143         unsigned scale;
144         Register index;
145         Register base;
146         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
147
148         decode_SIB(locs->sib_byte, scale, index, base);
149
150         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
151         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
152                                     locs->rex_x))));
153         Expression::Ptr baseAST;
154         if(base == 0x05)
155         {
156             switch(locs->modrm_mod)
157             {
158                 case 0x00:
159                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1, true);
160                     break;
161                 case 0x01: 
162                 case 0x02: 
163                     baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
164                                                                                                registerType,
165                                                                                                locs->rex_b)));
166                     break;
167                 case 0x03:
168                 default:
169                     assert(0);
170                     break;
171             };
172         }
173         else
174         {
175             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
176                                                                                                registerType,
177                                                                                                locs->rex_b)));
178         }
179
180         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
181         {
182             return baseAST;
183         }
184         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
185     }
186
187       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
188                                                                   unsigned int opType)
189     {
190        unsigned int regType = op_d;
191         Result_Type aw = ia32_is_mode_64() ? u64 : u32;
192         if (opType == op_lea) {
193             // For an LEA, aw (address width) is insufficient, use makeSizeType
194             aw = makeSizeType(opType);
195         }
196         if(ia32_is_mode_64())
197         {
198             regType = op_q;
199         }
200         Expression::Ptr e =
201             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, locs->rex_b));
202         switch(locs->modrm_mod)
203         {
204             case 0:
205                 if(locs->modrm_rm == modrm_use_sib) {
206                     e = makeSIBExpression(b);
207                 }
208                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
209                 {
210                     assert(locs->opcode_position > -1);
211                     if(ia32_is_mode_64())
212                     {
213                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
214                                             getModRMDisplacement(b), aw);
215                     }
216                     else
217                     {
218                         e = getModRMDisplacement(b);
219                     }
220         
221                 }
222                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
223                 {
224                     e = getModRMDisplacement(b);
225                 }
226                 if(opType == op_lea)
227                 {
228                     return e;
229                 }
230                 return makeDereferenceExpression(e, makeSizeType(opType));
231                 assert(0);
232                 break;
233             case 1:
234             case 2:
235             {
236                 if(locs->modrm_rm == modrm_use_sib) {
237                     e = makeSIBExpression(b);
238                 }
239                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
240                 if(opType == op_lea)
241                 {
242                     return disp_e;
243                 }
244                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
245             }
246             assert(0);
247             break;
248             case 3:
249                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, locs->rex_b));
250             default:
251                 return Expression::Ptr();
252         
253         };
254         // can't get here, but make the compiler happy...
255         assert(0);
256         return Expression::Ptr();
257     }
258
259     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
260                                                             bool isSigned)
261     {
262         // rex_w indicates we need to sign-extend also.
263         isSigned = isSigned || locs->rex_w;
264
265         switch(opType)
266         {
267             case op_b:
268                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
269                 break;
270             case op_d:
271                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
272             case op_w:
273                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
274                 break;
275             case op_q:
276                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
277                 break;
278             case op_v:
279                 if (locs->rex_w) {
280                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
281                 }
282                 //FALLTHROUGH
283             case op_z:
284                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
285                 // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
286                 if(!sizePrefixPresent)
287                 {
288                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
289                 }
290                 else
291                 {
292                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
293                 }
294                 break;
295             case op_p:
296                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
297                 // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
298                 if(!sizePrefixPresent)
299                 {
300                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
301                 }
302                 else
303                 {
304                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
305                 }
306
307                 break;
308             case op_a:
309             case op_dq:
310             case op_pd:
311             case op_ps:
312             case op_s:
313             case op_si:
314             case op_lea:
315             case op_allgprs:
316             case op_512:
317             case op_c:
318                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
319                 return Expression::Ptr();
320             default:
321                 assert(!"Can't happen: opType out of range");
322                 return Expression::Ptr();
323         }
324     }
325     
326     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
327     {
328         int disp_pos;
329
330         if(locs->sib_position != -1)
331         {
332             disp_pos = locs->sib_position + 1;
333         }
334         else
335         {
336             disp_pos = locs->modrm_position + 1;
337         }
338         switch(locs->modrm_mod)
339         {
340             case 1:
341                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
342                         disp_pos)))));
343                 break;
344             case 2:
345                 if(sizePrefixPresent)
346                 {
347                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
348                             disp_pos)))));
349                 }
350                 else
351                 {
352                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
353                             disp_pos)))));
354                 }
355                 break;
356             case 0:
357                 // In 16-bit mode, the word displacement is modrm r/m 6
358                 if(sizePrefixPresent)
359                 {
360                     if(locs->modrm_rm == 6)
361                     {
362                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
363                                            *((const dword_t*)(b.start + disp_pos)))));
364                     }
365                     // TODO FIXME; this was decoding wrong, but I'm not sure
366                     // why...
367                     else if (locs->modrm_rm == 5) {
368                         assert(b.start + disp_pos + 4 <= b.end);
369                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
370                                            *((const dword_t*)(b.start + disp_pos)))));
371                     } else {
372                         assert(b.start + disp_pos + 1 <= b.end);
373                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
374                     }
375                     break;
376                 }
377                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
378                 else
379                 {
380                     if(locs->modrm_rm == 5)
381                     {
382                         if (b.start + disp_pos + 4 <= b.end) 
383                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
384                                                *((const dword_t*)(b.start + disp_pos)))));
385                         else
386                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
387                     }
388                     else
389                     {
390                         if (b.start + disp_pos + 1 <= b.end)
391                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
392                         else
393                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
394                     }
395                     break;
396                 }
397             default:
398                 assert(b.start + disp_pos + 1 <= b.end);
399                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
400                 break;
401         }
402     }
403
404     enum intelRegBanks
405     {
406         b_8bitNoREX = 0,
407         b_16bit,
408         b_32bit,
409         b_segment,
410         b_64bit,
411         b_xmm,
412         b_xmmhigh,
413         b_mm,
414         b_cr,
415         b_dr,
416         b_tr,
417         b_amd64ext,
418         b_8bitWithREX,
419         b_fpstack,
420         amd64_ext_8,
421         amd64_ext_16,
422         amd64_ext_32
423     };
424     static MachRegister IntelRegTable32[][8] = {
425         {
426             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
427         },
428         {
429             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
430         },
431         {
432             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
433         },
434         {
435            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
436         },
437         {
438             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
439         },
440         {
441             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
442         },
443         {
444             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
445         },
446         {
447             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
448         },
449         {
450             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
451         },
452         {
453             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
454         },
455         {
456             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
457         },
458         {
459             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
460         },
461         {
462             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
463         },
464         {
465             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
466         }
467
468     };
469     static MachRegister IntelRegTable64[][8] = {
470         {
471             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
472         },
473         {
474             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
475         },
476         {
477             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
478         },
479         {
480             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
481         },
482         {
483             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
484         },
485         {
486             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
487         },
488         {
489             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
490         },
491         {
492             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
493         },
494         {
495             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
496         },
497         {
498             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
499         },
500         {
501             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
502         },
503         {
504             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
505         },
506         {
507             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
508         },
509         {
510             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
511         },
512         {
513             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
514         },
515         {
516             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
517         },
518         {
519             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
520         },
521   {
522     x86_64::ymm0, x86_64::ymm1, x86_64::ymm2, x86_64::ymm3, x86_64::ymm4, x86_64::ymm5, x86_64::ymm6, x86_64::ymm7
523   },
524   {
525     x86_64::ymm8, x86_64::ymm9, x86_64::ymm10, x86_64::ymm11, x86_64::ymm12, x86_64::ymm13, x86_64::ymm14, x86_64::ymm15
526   }
527
528     };
529
530   /* Uses the appropriate lookup table based on the 
531      decoder architecture */
532   class IntelRegTable_access {
533     public:
534         inline MachRegister operator()(Architecture arch,
535                                        intelRegBanks bank,
536                                        int index)
537         {
538             assert(index >= 0 && index < 8);
539     
540             if(arch == Arch_x86_64)
541                 return IntelRegTable64[bank][index];
542             else if(arch == Arch_x86) 
543             {
544               if(bank > b_fpstack) return InvalidReg;
545               return IntelRegTable32[bank][index];
546             }
547             assert(0);
548             return InvalidReg;
549         }
550
551   };
552   static IntelRegTable_access IntelRegTable;
553
554       bool InstructionDecoder_x86::isDefault64Insn()
555       {
556         switch(m_Operation->getID())
557         {
558         case e_jmp:
559         case e_pop:
560         case e_push:
561         case e_call:
562           return true;
563         default:
564           return false;
565         }
566         
567       }
568       
569
570     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
571                                         bool isExtendedReg)
572     {
573         MachRegister retVal;
574         
575
576         if(isExtendedReg)
577         {
578             switch(opType)
579             {
580                 case op_q:  
581                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
582                     break;
583                 case op_d:
584                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
585                     break;
586                 case op_w:
587                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
588                     break;
589                 case op_b:
590                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
591                     break;
592                 case op_v:
593                     if (locs->rex_w || isDefault64Insn())
594                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
595                     else if (!sizePrefixPresent)
596                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
597                     else
598                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
599                     break;      
600                 case op_p:
601                 case op_z:
602                     if (!sizePrefixPresent)
603                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
604                     else
605                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
606                     break;
607                 default:
608                     retVal = InvalidReg;
609             }
610         }
611         /* Promotion to 64-bit only applies to the operand types
612            that are varible (c,v,z). Ignoring c and z because they
613            do the right thing on 32- and 64-bit code.
614         else if(locs->rex_w)
615         {
616             // AMD64 with 64-bit operands
617             retVal = IntelRegTable[b_64bit][intelReg];
618         }
619         */
620         else
621         {
622             switch(opType)
623             {
624                 case op_v:
625                   if(locs->rex_w || isDefault64Insn())
626                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
627                     else
628                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
629                     break;
630                 case op_b:
631                     if (locs->rex_position == -1) {
632                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
633                     } else {
634                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
635                     }
636                     break;
637                 case op_q:
638                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
639                     break;
640                 case op_w:
641                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
642                     break;
643                 case op_f:
644                 case op_dbl:
645                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
646                     break;
647                 case op_d:
648                 case op_si:
649                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
650                     break;
651                 default:
652                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
653                     break;
654             }
655         }
656
657         if (!ia32_is_mode_64()) {
658           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
659             assert(0);
660         }
661
662         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
663     }
664     
665     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
666     {
667         switch(opType)
668         {
669             case op_b:
670             case op_c:
671                 return u8;
672             case op_d:
673             case op_ss:
674             case op_allgprs:
675             case op_si:
676                 return u32;
677             case op_w:
678             case op_a:
679                 return u16;
680             case op_q:
681             case op_sd:
682                 return u64;
683             case op_v:
684             case op_lea:
685             case op_z:
686                 if (locs->rex_w) 
687                 {
688                     return u64;
689                 }
690               if(ia32_is_mode_64() || !sizePrefixPresent)
691                 {
692                     return u32;
693                 }
694                 else
695                 {
696                     return u16;
697                 }
698                 break;
699             case op_y:
700                 if(ia32_is_mode_64())
701                         return u64;
702                 else
703                         return u32;
704                 break;
705             case op_p:
706                 // book says operand size; arch-x86 says word + word * operand size
707                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
708                 {
709                     return u48;
710                 }
711                 else
712                 {
713                     return u32;
714                 }
715             case op_dq:
716             case op_qq:
717                 return u64;
718             case op_512:
719                 return m512;
720             case op_pi:
721             case op_ps:
722             case op_pd:
723                 return dbl128;
724             case op_s:
725                 return u48;
726             case op_f:
727                 return sp_float;
728             case op_dbl:
729                 return dp_float;
730             case op_14:
731                 return m14;
732             default:
733                 assert(!"Can't happen!");
734                 return u8;
735         }
736     }
737
738
739     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
740                                                   const ia32_operand& operand,
741                                                   int & imm_index, /* immediate operand index */
742                                                   const Instruction* insn_to_complete, 
743                                                   bool isRead, bool isWritten)
744     {
745        bool isCFT = false;
746       bool isCall = false;
747       bool isConditional = false;
748       InsnCategory cat = insn_to_complete->getCategory();
749       if(cat == c_BranchInsn || cat == c_CallInsn)
750         {
751           isCFT = true;
752           if(cat == c_CallInsn)
753             {
754               isCall = true;
755             }
756         }
757       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
758         isConditional = true;
759       }
760
761       unsigned int optype = operand.optype;
762       int vex_vvvv = 0;
763       // int vex_l = 0;
764     if(decodedInstruction && decodedInstruction->getPrefix()->vex_prefix[0])
765     {
766       /* The vvvv bits are bits 3, 4, 5, 6 and are in 1's complement */
767       if(decodedInstruction->getPrefix()->vex_prefix[1])
768       {
769         // vex_l = decodedInstruction->getPrefix()->vex_prefix[1] & VEX3_L;
770         vex_vvvv = GETVEX_VVVV(decodedInstruction->getPrefix()->vex_prefix[1]);
771       } else {
772         // vex_l = decodedInstruction->getPrefix()->vex_prefix[0] & VEX2_L;
773         vex_vvvv = GETVEX_VVVV(decodedInstruction->getPrefix()->vex_prefix[0]);
774       }
775     }
776       if (sizePrefixPresent && 
777           ((optype == op_v) ||
778            (optype == op_z))) {
779         optype = op_w;
780       }
781       if(optype == op_y) {
782           if(ia32_is_mode_64() && locs->rex_w)
783                   optype = op_q;
784           else
785                   optype = op_d;
786       }
787                 switch(operand.admet)
788                 {
789                     case 0:
790                     // No operand
791                     {
792 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
793                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
794                             fprintf(stderr, "%x ", b.start[i]);
795                         }
796                         fprintf(stderr, "\n");*/
797                         assert(!"Mismatched number of operands--check tables");
798                         return false;
799                     }
800                     case am_A:
801                     {
802                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
803                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
804                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
805                     }
806                     break;
807                     case am_C:
808                     {
809                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
810                         insn_to_complete->appendOperand(op, isRead, isWritten);
811                     }
812                     break;
813                     case am_D:
814                     {
815                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
816                         insn_to_complete->appendOperand(op, isRead, isWritten);
817                     }
818                     break;
819                     case am_E:
820                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
821                     // mod of 0x03 specifies direct register access).
822                     case am_M:
823                     // am_R is the inverse of am_M; it should only have a mod of 3
824                     case am_R:
825                     // can be am_R or am_M      
826                     case am_RM: 
827                         if(isCFT)
828                         {
829                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
830                         }
831                         else
832                         {
833                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
834                         }
835                     break;
836                     case am_F:
837                     {
838                         Expression::Ptr op(makeRegisterExpression(x86::flags));
839                         insn_to_complete->appendOperand(op, isRead, isWritten);
840                     }
841                     break;
842                     case am_G:
843                     {
844                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
845                                 optype, locs->rex_r)));
846                         insn_to_complete->appendOperand(op, isRead, isWritten);
847                     }
848                     break;
849                     case am_H:
850                       {
851                           /* Operand comes from the VEX.vvvv bits */
852                          insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
853                               vex_vvvv <= 7 ? b_xmm : b_xmmhigh, vex_vvvv <= 7 ? vex_vvvv : vex_vvvv - 8)),
854                               isRead, isWritten);
855                       }
856                       break;
857                     case am_I:
858                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
859                                                                         locs->imm_position[imm_index++]), 
860                                                         isRead, isWritten);
861                         break;
862                     case am_J:
863                     {
864                         Expression::Ptr Offset(decodeImmediate(optype, 
865                                                                b.start + locs->imm_position[imm_index++], 
866                                                                true));
867                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
868                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
869                             decodedInstruction->getSize()))));
870                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
871
872                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
873                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
874                         if (isConditional) 
875                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
876                     }
877                     break;
878                     case am_O:
879                     {
880                     // Address/offset width, which is *not* what's encoded by the optype...
881                     // The deref's width is what's actually encoded here.
882                         int pseudoOpType;
883                         switch(locs->address_size)
884                         {
885                             case 1:
886                                 pseudoOpType = op_b;
887                                 break;
888                             case 2:
889                                 pseudoOpType = op_w;
890                                 break;
891                             case 4:
892                                 pseudoOpType = op_d;
893                                 break;
894                             case 0:
895                                 // closest I can get to "will be address size by default"
896                                 pseudoOpType = op_v;
897                                 break;
898                             default:
899                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
900                                 pseudoOpType = op_b;
901                                 break;
902                         }
903
904
905                         int offset_position = locs->opcode_position;
906                         if(locs->modrm_position > offset_position && locs->modrm_operand <
907                            (int)(insn_to_complete->m_Operands.size()))
908                         {
909                             offset_position = locs->modrm_position;
910                         }
911                         if(locs->sib_position > offset_position)
912                         {
913                             offset_position = locs->sib_position;
914                         }
915                         offset_position++;
916                         insn_to_complete->appendOperand(makeDereferenceExpression(
917                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
918                                                         isRead, isWritten);
919                     }
920                     break;
921                     case am_P:
922                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
923                                 isRead, isWritten);
924                         break;
925                     case am_Q:
926         
927                         switch(locs->modrm_mod)
928                         {
929                             // direct dereference
930                             case 0x00:
931                             case 0x01:
932                             case 0x02:
933                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
934                                 break;
935                             case 0x03:
936                                 // use of actual register
937                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
938                                                                isRead, isWritten);
939                                 break;
940                             default:
941                                 assert(!"2-bit value modrm_mod out of range");
942                                 break;
943                         };
944                         break;
945                     case am_S:
946                     // Segment register in modrm reg field.
947                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
948                                 isRead, isWritten);
949                         break;
950                     case am_T:
951                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
952                         // NOTE: this only appears in deprecated opcodes
953                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
954                                                        isRead, isWritten);
955                         break;
956                     case am_UM:
957                         switch(locs->modrm_mod)
958                         {
959                         // direct dereference
960                         case 0x00:
961                         case 0x01:
962                         case 0x02:
963                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
964                                                 isRead, isWritten);
965                                 break;
966                         case 0x03:
967                                 // use of actual register
968                                 {
969                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
970                                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
971                                                         isRead, isWritten);
972                                         break;
973                                 }
974                         default:
975                                 assert(!"2-bit value modrm_mod out of range");
976                                 break;
977                         };
978                         break;
979                     case am_V:
980                        
981                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
982                                 locs->rex_r ? b_xmmhigh : b_xmm,locs->modrm_reg)),
983                                     isRead, isWritten);
984                         break;
985                     case am_W:
986                         switch(locs->modrm_mod)
987                         {
988                             // direct dereference
989                             case 0x00:
990                             case 0x01:
991                             case 0x02:
992                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
993                                                                isRead, isWritten);
994                                 break;
995                             case 0x03:
996                             // use of actual register
997                             {
998                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
999                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
1000                                         isRead, isWritten);
1001                                 break;
1002                             }
1003                             default:
1004                                 assert(!"2-bit value modrm_mod out of range");
1005                                 break;
1006                         };
1007                         break;
1008                     case am_X:
1009                     {
1010                         MachRegister si_reg;
1011                         if(m_Arch == Arch_x86)
1012                         {
1013                                 if(addrSizePrefixPresent)
1014                                 {
1015                                         si_reg = x86::si;
1016                                 } else
1017                                 {
1018                                         si_reg = x86::esi;
1019                                 }
1020                         }
1021                         else
1022                         {
1023                                 if(addrSizePrefixPresent)
1024                                 {
1025                                         si_reg = x86_64::esi;
1026                                 } else
1027                                 {
1028                                         si_reg = x86_64::rsi;
1029                                 }
1030                         }
1031                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1032                         Expression::Ptr si(makeRegisterExpression(si_reg));
1033                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1034                                 Result(u32, 0x10))));
1035                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1036                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1037                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1038                                                        isRead, isWritten);
1039                     }
1040                     break;
1041                     case am_Y:
1042                     {
1043                         MachRegister di_reg;
1044                         if(m_Arch == Arch_x86)
1045                         {
1046                                 if(addrSizePrefixPresent)
1047                                 {
1048                                         di_reg = x86::di;
1049                                 } else
1050                                 {
1051                                         di_reg = x86::edi;
1052                                 }
1053                         }
1054                         else
1055                         {
1056                                 if(addrSizePrefixPresent)
1057                                 {
1058                                         di_reg = x86_64::edi;
1059                                 } else
1060                                 {
1061                                         di_reg = x86_64::rdi;
1062                                 }
1063                         }
1064                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1065                         Expression::Ptr di(makeRegisterExpression(di_reg));
1066                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1067                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1068                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1069                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1070                                                        isRead, isWritten);
1071                     }
1072                     break;
1073                     case am_tworeghack:
1074                     {
1075                         if(optype == op_edxeax)
1076                         {
1077                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1078                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1079                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1080                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1081                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1082                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1083                             insn_to_complete->appendOperand(op, isRead, isWritten);
1084                         }
1085                         else if (optype == op_ecxebx)
1086                         {
1087                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1088                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1089                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1090                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1091                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1092                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1093                             insn_to_complete->appendOperand(op, isRead, isWritten);
1094                         }
1095                     }
1096                     break;
1097                     
1098                     case am_reg:
1099                     {
1100                         MachRegister r(optype);
1101                         r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1102                         entryID entryid = decodedInstruction->getEntry()->getID(locs);
1103                         if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1104                             (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1105                         {
1106                             // FP stack registers are not affected by the rex_b bit in AM_REG.
1107                            if(r.regClass() != (unsigned) x86::MMX)
1108                             {
1109                                 r = MachRegister((r.val()) | x86_64::r8.val());
1110                             }
1111                         }
1112                         if(sizePrefixPresent)
1113                         {
1114                             r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1115                         }
1116                         Expression::Ptr op(makeRegisterExpression(r));
1117                         insn_to_complete->appendOperand(op, isRead, isWritten);
1118                     }
1119                     break;
1120                 case am_stackH:
1121                 case am_stackP:
1122                 // handled elsewhere
1123                     break;
1124                 case am_allgprs:
1125                 {
1126                     if(m_Arch == Arch_x86)
1127                     {
1128                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1129                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1130                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1131                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1132                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1133                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1134                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1135                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1136                     }
1137                     else
1138                     {
1139                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1140                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1141                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1142                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1143                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1144                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1145                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1146                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1147                     }
1148                 }
1149                     break;
1150                 case am_ImplImm: {
1151                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1152                   break;
1153                 }
1154
1155                 default:
1156                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1157                         break;
1158                 };
1159                 return true;
1160             }
1161
1162     extern ia32_entry invalid;
1163     
1164     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1165     {
1166         if(decodedInstruction == NULL)
1167         {
1168             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1169             assert(decodedInstruction);
1170         }
1171         if(locs == NULL)
1172         {
1173             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1174             assert(locs);
1175         }
1176         locs = new(locs) ia32_locations; //reinit();
1177         assert(locs->sib_position == -1);
1178         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1179         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1180         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1181         if (decodedInstruction->getPrefix()->rexW()) {
1182            // as per 2.2.1.2 - rex.w overrides 66h
1183            sizePrefixPresent = false;
1184         }
1185         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1186         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1187         if(decodedInstruction->getEntry()) {
1188             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1189                                     decodedInstruction->getPrefix(), locs, m_Arch));
1190             
1191         }
1192         else
1193         {
1194                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1195                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1196                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1197                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1198                 // yell at the user.
1199             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1200                                     decodedInstruction->getPrefix(), locs, m_Arch));
1201         }
1202
1203     }
1204     
1205     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1206     {
1207         doIA32Decode(b);
1208         b.start += decodedInstruction->getSize();
1209     }
1210     
1211       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1212     {
1213        int imm_index = 0; // handle multiple immediate operands
1214         if(!decodedInstruction) return false;
1215         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1216         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1217
1218         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1219             decodedInstruction->getEntry()->getID() == e_ret_far) {
1220            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1221                                                                 ia32_is_mode_64() ? u64 : u32);
1222            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1223         }
1224
1225         for(unsigned i = 0; i < 3; i++)
1226         {
1227             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1228                decodedInstruction->getEntry()->operands[i].optype == 0)
1229                 return true;
1230             if(!decodeOneOperand(b,
1231                                  decodedInstruction->getEntry()->operands[i], 
1232                                  imm_index, 
1233                                  insn_to_complete, 
1234                                  readsOperand(opsema, i),
1235                                  writesOperand(opsema, i)))
1236             {
1237                 return false;
1238             }
1239         }
1240     
1241         return true;
1242     }
1243
1244     
1245       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1246     {
1247         return InstructionDecoderImpl::decode(b);
1248     }
1249     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1250     {
1251       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1252       //insn_to_complete->m_Operands.reserve(4);
1253       doIA32Decode(b);        
1254       decodeOperands(insn_to_complete);
1255     }
1256     
1257 };
1258 };
1259