Further decoding fixes.
[dyninst.git] / instructionAPI / src / InstructionDecoder-x86.C
1 /*
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30
31 #define INSIDE_INSTRUCTION_API
32
33 #include "common/src/Types.h"
34 #include "InstructionDecoder-x86.h"
35 #include "Expression.h"
36 #include "common/src/arch-x86.h"
37 #include "Register.h"
38 #include "Dereference.h"
39 #include "Immediate.h" 
40 #include "BinaryFunction.h"
41 #include "common/src/singleton_object_pool.h"
42
43 using namespace std;
44 using namespace NS_x86;
45 namespace Dyninst
46 {
47     namespace InstructionAPI
48     {
49     
50         bool readsOperand(unsigned int opsema, unsigned int i)
51         {
52             switch(opsema) {
53                 case s1R2R:
54                     return (i == 0 || i == 1);
55                 case s1R:
56                 case s1RW:
57                     return i == 0;
58                 case s1W:
59                     return false;
60                 case s1W2RW:
61                 case s1W2R:   // second operand read, first operand written (e.g. mov)
62                     return i == 1;
63                 case s1RW2R:  // two operands read, first written (e.g. add)
64                 case s1RW2RW: // e.g. xchg
65                 case s1R2RW:
66                     return i == 0 || i == 1;
67                 case s1W2R3R: // e.g. imul
68                 case s1W2RW3R: // some mul
69                 case s1W2R3RW: // (stack) push & pop
70                     return i == 1 || i == 2;
71                 case s1W2W3R: // e.g. les
72                     return i == 2;
73                 case s1RW2R3R: // shld/shrd
74                 case s1RW2RW3R: // [i]div, cmpxch8b
75                 case s1R2R3R:
76                     return i == 0 || i == 1 || i == 2;
77                     break;
78                 case sNONE:
79                 default:
80                     return false;
81             }
82       
83         }
84       
85         bool writesOperand(unsigned int opsema, unsigned int i)
86         {
87             switch(opsema) {
88                 case s1R2R:
89                 case s1R:
90                     return false;
91                 case s1RW:
92                 case s1W:
93                     case s1W2R:   // second operand read, first operand written (e.g. mov)
94                         case s1RW2R:  // two operands read, first written (e.g. add)
95                             case s1W2R3R: // e.g. imul
96                                 case s1RW2R3R: // shld/shrd
97                                     return i == 0;
98                 case s1R2RW:
99                     return i == 1;
100                 case s1W2RW:
101                     case s1RW2RW: // e.g. xchg
102                         case s1W2RW3R: // some mul
103                             case s1W2W3R: // e.g. les
104                                 case s1RW2RW3R: // [i]div, cmpxch8b
105                                     return i == 0 || i == 1;
106                                     case s1W2R3RW: // (stack) push & pop
107                                         return i == 0 || i == 2;
108                 case sNONE:
109                 default:
110                     return false;
111             }
112         }
113
114
115     
116     INSTRUCTION_EXPORT InstructionDecoder_x86::InstructionDecoder_x86(Architecture a) :
117       InstructionDecoderImpl(a),
118     locs(NULL),
119     decodedInstruction(NULL),
120     sizePrefixPresent(false),
121     addrSizePrefixPresent(false)
122     {
123       if(a == Arch_x86_64) setMode(true);
124       
125     }
126     INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86()
127     {
128         if(decodedInstruction) decodedInstruction->~ia32_instruction();
129         free(decodedInstruction);
130         if(locs) locs->~ia32_locations();
131         free(locs);
132
133     }
134     static const unsigned char modrm_use_sib = 4;
135     
136     INSTRUCTION_EXPORT void InstructionDecoder_x86::setMode(bool is64)
137     {
138         ia32_set_mode_64(is64);
139     }
140     
141       Expression::Ptr InstructionDecoder_x86::makeSIBExpression(const InstructionDecoder::buffer& b)
142     {
143         unsigned scale;
144         Register index;
145         Register base;
146         Result_Type registerType = ia32_is_mode_64() ? u64 : u32;
147
148         decode_SIB(locs->sib_byte, scale, index, base);
149
150         Expression::Ptr scaleAST(make_shared(singleton_object_pool<Immediate>::construct(Result(u8, dword_t(scale)))));
151         Expression::Ptr indexAST(make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(index, registerType,
152                                     locs->rex_x))));
153         Expression::Ptr baseAST;
154         if(base == 0x05)
155         {
156             switch(locs->modrm_mod)
157             {
158                 case 0x00:
159                     baseAST = decodeImmediate(op_d, b.start + locs->sib_position + 1, true);
160                     break;
161                 case 0x01: 
162                 case 0x02: 
163                     baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
164                                                                                                registerType,
165                                                                                                locs->rex_b)));
166                     break;
167                 case 0x03:
168                 default:
169                     assert(0);
170                     break;
171             };
172         }
173         else
174         {
175             baseAST = make_shared(singleton_object_pool<RegisterAST>::construct(makeRegisterID(base, 
176                                                                                                registerType,
177                                                                                                locs->rex_b)));
178         }
179
180         if(index == 0x04 && (!(ia32_is_mode_64()) || !(locs->rex_x)))
181         {
182             return baseAST;
183         }
184         return makeAddExpression(baseAST, makeMultiplyExpression(indexAST, scaleAST, registerType), registerType);
185     }
186
187       Expression::Ptr InstructionDecoder_x86::makeModRMExpression(const InstructionDecoder::buffer& b,
188                                                                   unsigned int opType)
189     {
190        unsigned int regType = op_d;
191         Result_Type aw = ia32_is_mode_64() ? u64 : u32;
192         if (opType == op_lea) {
193             // For an LEA, aw (address width) is insufficient, use makeSizeType
194             aw = makeSizeType(opType);
195         }
196         if(ia32_is_mode_64())
197         {
198             regType = op_q;
199         }
200         Expression::Ptr e =
201             makeRegisterExpression(makeRegisterID(locs->modrm_rm, regType, locs->rex_b));
202         switch(locs->modrm_mod)
203         {
204             case 0:
205                 if(locs->modrm_rm == modrm_use_sib) {
206                     e = makeSIBExpression(b);
207                 }
208                 if(locs->modrm_rm == 0x5 && !addrSizePrefixPresent)
209                 {
210                     assert(locs->opcode_position > -1);
211                     if(ia32_is_mode_64())
212                     {
213                         e = makeAddExpression(makeRegisterExpression(x86_64::rip),
214                                             getModRMDisplacement(b), aw);
215                     }
216                     else
217                     {
218                         e = getModRMDisplacement(b);
219                     }
220         
221                 }
222                 if(locs->modrm_rm == 0x6 && addrSizePrefixPresent)
223                 {
224                     e = getModRMDisplacement(b);
225                 }
226                 if(opType == op_lea)
227                 {
228                     return e;
229                 }
230                 return makeDereferenceExpression(e, makeSizeType(opType));
231                 assert(0);
232                 break;
233             case 1:
234             case 2:
235             {
236                 if(locs->modrm_rm == modrm_use_sib) {
237                     e = makeSIBExpression(b);
238                 }
239                 Expression::Ptr disp_e = makeAddExpression(e, getModRMDisplacement(b), aw);
240                 if(opType == op_lea)
241                 {
242                     return disp_e;
243                 }
244                 return makeDereferenceExpression(disp_e, makeSizeType(opType));
245             }
246             assert(0);
247             break;
248             case 3:
249                 return makeRegisterExpression(makeRegisterID(locs->modrm_rm, opType, locs->rex_b));
250             default:
251                 return Expression::Ptr();
252         
253         };
254         // can't get here, but make the compiler happy...
255         assert(0);
256         return Expression::Ptr();
257     }
258
259     Expression::Ptr InstructionDecoder_x86::decodeImmediate(unsigned int opType, const unsigned char* immStart, 
260                                                             bool isSigned)
261     {
262         // rex_w indicates we need to sign-extend also.
263         isSigned = isSigned || locs->rex_w;
264
265         switch(opType)
266         {
267             case op_b:
268                 return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart)));
269                 break;
270             case op_d:
271                 return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
272             case op_w:
273                 return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
274                 break;
275             case op_q:
276                 return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
277                 break;
278             case op_v:
279                 if (locs->rex_w || isDefault64Insn()) {
280                     return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart)));
281                 }
282                 //FALLTHROUGH
283             case op_z:
284                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 32 bit
285                 // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit
286                 if(!sizePrefixPresent)
287                 {
288                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
289                 }
290                 else
291                 {
292                     return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart)));
293                 }
294                 break;
295             case op_p:
296                 // 32 bit mode & no prefix, or 16 bit mode & prefix => 48 bit
297                 // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit
298                 if(!sizePrefixPresent)
299                 {
300                     return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart)));
301                 }
302                 else
303                 {
304                     return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart)));
305                 }
306
307                 break;
308             case op_a:
309             case op_dq:
310             case op_pd:
311             case op_ps:
312             case op_s:
313             case op_si:
314             case op_lea:
315             case op_allgprs:
316             case op_512:
317             case op_c:
318                 assert(!"Can't happen: opType unexpected for valid ways to decode an immediate");
319                 return Expression::Ptr();
320             default:
321                 assert(!"Can't happen: opType out of range");
322                 return Expression::Ptr();
323         }
324     }
325     
326     Expression::Ptr InstructionDecoder_x86::getModRMDisplacement(const InstructionDecoder::buffer& b)
327     {
328         int disp_pos;
329
330         if(locs->sib_position != -1)
331         {
332             disp_pos = locs->sib_position + 1;
333         }
334         else
335         {
336             disp_pos = locs->modrm_position + 1;
337         }
338         switch(locs->modrm_mod)
339         {
340             case 1:
341                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, (*(const byte_t*)(b.start +
342                         disp_pos)))));
343                 break;
344             case 2:
345                 if(sizePrefixPresent)
346                 {
347                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s16, *((const word_t*)(b.start +
348                             disp_pos)))));
349                 }
350                 else
351                 {
352                     return make_shared(singleton_object_pool<Immediate>::construct(Result(s32, *((const dword_t*)(b.start +
353                             disp_pos)))));
354                 }
355                 break;
356             case 0:
357                 // In 16-bit mode, the word displacement is modrm r/m 6
358                 if(sizePrefixPresent)
359                 {
360                     if(locs->modrm_rm == 6)
361                     {
362                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s16,
363                                            *((const dword_t*)(b.start + disp_pos)))));
364                     }
365                     // TODO FIXME; this was decoding wrong, but I'm not sure
366                     // why...
367                     else if (locs->modrm_rm == 5) {
368                         assert(b.start + disp_pos + 4 <= b.end);
369                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
370                                            *((const dword_t*)(b.start + disp_pos)))));
371                     } else {
372                         assert(b.start + disp_pos + 1 <= b.end);
373                         return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
374                     }
375                     break;
376                 }
377                 // ...and in 32-bit mode, the dword displacement is modrm r/m 5
378                 else
379                 {
380                     if(locs->modrm_rm == 5)
381                     {
382                         if (b.start + disp_pos + 4 <= b.end) 
383                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s32,
384                                                *((const dword_t*)(b.start + disp_pos)))));
385                         else
386                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
387                     }
388                     else
389                     {
390                         if (b.start + disp_pos + 1 <= b.end)
391                             return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
392                         else
393                             return make_shared(singleton_object_pool<Immediate>::construct(Result()));
394                     }
395                     break;
396                 }
397             default:
398                 assert(b.start + disp_pos + 1 <= b.end);
399                 return make_shared(singleton_object_pool<Immediate>::construct(Result(s8, 0)));
400                 break;
401         }
402     }
403
404     enum intelRegBanks
405     {
406         b_8bitNoREX = 0,
407         b_16bit,
408         b_32bit,
409         b_segment,
410         b_64bit,
411         b_xmm,
412         b_xmmhigh,
413         b_mm,
414         b_cr,
415         b_dr,
416         b_tr,
417         b_amd64ext,
418         b_8bitWithREX,
419         b_fpstack,
420         amd64_ext_8,
421         amd64_ext_16,
422         amd64_ext_32
423     };
424     static MachRegister IntelRegTable32[][8] = {
425         {
426             x86::al, x86::cl, x86::dl, x86::bl, x86::ah, x86::ch, x86::dh, x86::bh
427         },
428         {
429             x86::ax, x86::cx, x86::dx, x86::bx, x86::sp, x86::bp, x86::si, x86::di
430         },
431         {
432             x86::eax, x86::ecx, x86::edx, x86::ebx, x86::esp, x86::ebp, x86::esi, x86::edi
433         },
434         {
435            x86::es, x86::cs, x86::ss, x86::ds, x86::fs, x86::gs, InvalidReg, InvalidReg
436         },
437         {
438             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
439         },
440         {
441             x86::xmm0, x86::xmm1, x86::xmm2, x86::xmm3, x86::xmm4, x86::xmm5, x86::xmm6, x86::xmm7
442         },
443         {
444             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
445         },
446         {
447             x86::mm0, x86::mm1, x86::mm2, x86::mm3, x86::mm4, x86::mm5, x86::mm6, x86::mm7
448         },
449         {
450             x86::cr0, x86::cr1, x86::cr2, x86::cr3, x86::cr4, x86::cr5, x86::cr6, x86::cr7
451         },
452         {
453             x86::dr0, x86::dr1, x86::dr2, x86::dr3, x86::dr4, x86::dr5, x86::dr6, x86::dr7
454         },
455         {
456             x86::tr0, x86::tr1, x86::tr2, x86::tr3, x86::tr4, x86::tr5, x86::tr6, x86::tr7
457         },
458         {
459             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
460         },
461         {
462             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
463         },
464         {
465             x86::st0, x86::st1, x86::st2, x86::st3, x86::st4, x86::st5, x86::st6, x86::st7
466         }
467
468     };
469     static MachRegister IntelRegTable64[][8] = {
470         {
471             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::ah, x86_64::ch, x86_64::dh, x86_64::bh
472         },
473         {
474             x86_64::ax, x86_64::cx, x86_64::dx, x86_64::bx, x86_64::sp, x86_64::bp, x86_64::si, x86_64::di
475         },
476         {
477             x86_64::eax, x86_64::ecx, x86_64::edx, x86_64::ebx, x86_64::esp, x86_64::ebp, x86_64::esi, x86_64::edi
478         },
479         {
480             x86_64::es, x86_64::cs, x86_64::ss, x86_64::ds, x86_64::fs, x86_64::gs, InvalidReg, InvalidReg
481         },
482         {
483             x86_64::rax, x86_64::rcx, x86_64::rdx, x86_64::rbx, x86_64::rsp, x86_64::rbp, x86_64::rsi, x86_64::rdi
484         },
485         {
486             x86_64::xmm0, x86_64::xmm1, x86_64::xmm2, x86_64::xmm3, x86_64::xmm4, x86_64::xmm5, x86_64::xmm6, x86_64::xmm7
487         },
488         {
489             x86_64::xmm8, x86_64::xmm9, x86_64::xmm10, x86_64::xmm11, x86_64::xmm12, x86_64::xmm13, x86_64::xmm14, x86_64::xmm15
490         },
491         {
492             x86_64::mm0, x86_64::mm1, x86_64::mm2, x86_64::mm3, x86_64::mm4, x86_64::mm5, x86_64::mm6, x86_64::mm7
493         },
494         {
495             x86_64::cr0, x86_64::cr1, x86_64::cr2, x86_64::cr3, x86_64::cr4, x86_64::cr5, x86_64::cr6, x86_64::cr7
496         },
497         {
498             x86_64::dr0, x86_64::dr1, x86_64::dr2, x86_64::dr3, x86_64::dr4, x86_64::dr5, x86_64::dr6, x86_64::dr7
499         },
500         {
501             x86_64::tr0, x86_64::tr1, x86_64::tr2, x86_64::tr3, x86_64::tr4, x86_64::tr5, x86_64::tr6, x86_64::tr7
502         },
503         {
504             x86_64::r8, x86_64::r9, x86_64::r10, x86_64::r11, x86_64::r12, x86_64::r13, x86_64::r14, x86_64::r15
505         },
506         {
507             x86_64::al, x86_64::cl, x86_64::dl, x86_64::bl, x86_64::spl, x86_64::bpl, x86_64::sil, x86_64::dil
508         },
509         {
510             x86_64::st0, x86_64::st1, x86_64::st2, x86_64::st3, x86_64::st4, x86_64::st5, x86_64::st6, x86_64::st7
511         },
512         {
513             x86_64::r8b, x86_64::r9b, x86_64::r10b, x86_64::r11b, x86_64::r12b, x86_64::r13b, x86_64::r14b, x86_64::r15b 
514         },
515         {
516             x86_64::r8w, x86_64::r9w, x86_64::r10w, x86_64::r11w, x86_64::r12w, x86_64::r13w, x86_64::r14w, x86_64::r15w 
517         },
518         {
519             x86_64::r8d, x86_64::r9d, x86_64::r10d, x86_64::r11d, x86_64::r12d, x86_64::r13d, x86_64::r14d, x86_64::r15d 
520         }
521
522     };
523
524   /* Uses the appropriate lookup table based on the 
525      decoder architecture */
526   class IntelRegTable_access {
527     public:
528         inline MachRegister operator()(Architecture arch,
529                                        intelRegBanks bank,
530                                        int index)
531         {
532             assert(index >= 0 && index < 8);
533     
534             if(arch == Arch_x86_64)
535                 return IntelRegTable64[bank][index];
536             else if(arch == Arch_x86) 
537             {
538               if(bank > b_fpstack) return InvalidReg;
539               return IntelRegTable32[bank][index];
540             }
541             assert(0);
542             return InvalidReg;
543         }
544
545   };
546   static IntelRegTable_access IntelRegTable;
547
548       bool InstructionDecoder_x86::isDefault64Insn()
549       {
550         switch(m_Operation->getID())
551         {
552         case e_jmp:
553         case e_pop:
554         case e_push:
555         case e_call:
556           return true;
557         default:
558           return false;
559         }
560         
561       }
562       
563
564     MachRegister InstructionDecoder_x86::makeRegisterID(unsigned int intelReg, unsigned int opType,
565                                         bool isExtendedReg)
566     {
567         MachRegister retVal;
568         
569
570         if(isExtendedReg)
571         {
572             switch(opType)
573             {
574                 case op_q:  
575                     retVal = IntelRegTable(m_Arch,b_amd64ext,intelReg);
576                     break;
577                 case op_d:
578                     retVal = IntelRegTable(m_Arch,amd64_ext_32,intelReg);
579                     break;
580                 case op_w:
581                     retVal = IntelRegTable(m_Arch,amd64_ext_16,intelReg);
582                     break;
583                 case op_b:
584                     retVal = IntelRegTable(m_Arch,amd64_ext_8,intelReg);
585                     break;
586                 case op_v:
587                     if (locs->rex_w || isDefault64Insn())
588                         retVal = IntelRegTable(m_Arch, b_amd64ext, intelReg);
589                     else if (!sizePrefixPresent)
590                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
591                     else
592                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
593                     break;      
594                 case op_p:
595                 case op_z:
596                     if (!sizePrefixPresent)
597                         retVal = IntelRegTable(m_Arch, amd64_ext_32, intelReg);
598                     else
599                         retVal = IntelRegTable(m_Arch, amd64_ext_16, intelReg);
600                     break;
601                 default:
602                     retVal = InvalidReg;
603             }
604         }
605         /* Promotion to 64-bit only applies to the operand types
606            that are varible (c,v,z). Ignoring c and z because they
607            do the right thing on 32- and 64-bit code.
608         else if(locs->rex_w)
609         {
610             // AMD64 with 64-bit operands
611             retVal = IntelRegTable[b_64bit][intelReg];
612         }
613         */
614         else
615         {
616             switch(opType)
617             {
618                 case op_v:
619                   if(locs->rex_w || isDefault64Insn())
620                         retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
621                     else
622                         retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
623                     break;
624                 case op_b:
625                     if (locs->rex_position == -1) {
626                         retVal = IntelRegTable(m_Arch,b_8bitNoREX,intelReg);
627                     } else {
628                         retVal = IntelRegTable(m_Arch,b_8bitWithREX,intelReg);
629                     }
630                     break;
631                 case op_q:
632                     retVal = IntelRegTable(m_Arch,b_64bit,intelReg);
633                     break;
634                 case op_w:
635                     retVal = IntelRegTable(m_Arch,b_16bit,intelReg);
636                     break;
637                 case op_f:
638                 case op_dbl:
639                     retVal = IntelRegTable(m_Arch,b_fpstack,intelReg);
640                     break;
641                 case op_d:
642                 case op_si:
643                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
644                     break;
645                 default:
646                     retVal = IntelRegTable(m_Arch,b_32bit,intelReg);
647                     break;
648             }
649         }
650
651         if (!ia32_is_mode_64()) {
652           if ((retVal.val() & 0x00ffffff) == 0x0001000c)
653             assert(0);
654         }
655
656         return MachRegister((retVal.val() & ~retVal.getArchitecture()) | m_Arch);
657     }
658     
659     Result_Type InstructionDecoder_x86::makeSizeType(unsigned int opType)
660     {
661         switch(opType)
662         {
663             case op_b:
664             case op_c:
665                 return u8;
666             case op_d:
667             case op_ss:
668             case op_allgprs:
669             case op_si:
670                 return u32;
671             case op_w:
672             case op_a:
673                 return u16;
674             case op_q:
675             case op_sd:
676                 return u64;
677             case op_v:
678             case op_lea:
679             case op_z:
680                 if (locs->rex_w) 
681                 {
682                     return u64;
683                 }
684               if(ia32_is_mode_64() || !sizePrefixPresent)
685                 {
686                     return u32;
687                 }
688                 else
689                 {
690                     return u16;
691                 }
692                 break;
693             case op_y:
694                 if(ia32_is_mode_64())
695                         return u64;
696                 else
697                         return u32;
698                 break;
699             case op_p:
700                 // book says operand size; arch-x86 says word + word * operand size
701                 if(!ia32_is_mode_64() ^ sizePrefixPresent)
702                 {
703                     return u48;
704                 }
705                 else
706                 {
707                     return u32;
708                 }
709             case op_dq:
710                 return u64;
711             case op_512:
712                 return m512;
713             case op_pi:
714             case op_ps:
715             case op_pd:
716                 return dbl128;
717             case op_s:
718                 return u48;
719             case op_f:
720                 return sp_float;
721             case op_dbl:
722                 return dp_float;
723             case op_14:
724                 return m14;
725             default:
726                 assert(!"Can't happen!");
727                 return u8;
728         }
729     }
730
731
732     bool InstructionDecoder_x86::decodeOneOperand(const InstructionDecoder::buffer& b,
733                                                   const ia32_operand& operand,
734                                                   int & imm_index, /* immediate operand index */
735                                                   const Instruction* insn_to_complete, 
736                                                   bool isRead, bool isWritten)
737     {
738        bool isCFT = false;
739       bool isCall = false;
740       bool isConditional = false;
741       InsnCategory cat = insn_to_complete->getCategory();
742       if(cat == c_BranchInsn || cat == c_CallInsn)
743         {
744           isCFT = true;
745           if(cat == c_CallInsn)
746             {
747               isCall = true;
748             }
749         }
750       if (cat == c_BranchInsn && insn_to_complete->getOperation().getID() != e_jmp) {
751         isConditional = true;
752       }
753
754       unsigned int optype = operand.optype;
755       if (sizePrefixPresent && 
756           ((optype == op_v) ||
757            (optype == op_z))) {
758         optype = op_w;
759       }
760       if(optype == op_y) {
761           if(ia32_is_mode_64() && locs->rex_w)
762                   optype = op_q;
763           else
764                   optype = op_d;
765       }
766                 switch(operand.admet)
767                 {
768                     case 0:
769                     // No operand
770                     {
771 /*                        fprintf(stderr, "ERROR: Instruction with mismatched operands. Raw bytes: ");
772                         for(unsigned int i = 0; i < decodedInstruction->getSize(); i++) {
773                             fprintf(stderr, "%x ", b.start[i]);
774                         }
775                         fprintf(stderr, "\n");*/
776                         assert(!"Mismatched number of operands--check tables");
777                         return false;
778                     }
779                     case am_A:
780                     {
781                         // am_A only shows up as a far call/jump.  Position 1 should be universally safe.
782                         Expression::Ptr addr(decodeImmediate(optype, b.start + 1));
783                         insn_to_complete->addSuccessor(addr, isCall, false, false, false);
784                     }
785                     break;
786                     case am_C:
787                     {
788                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_cr,locs->modrm_reg)));
789                         insn_to_complete->appendOperand(op, isRead, isWritten);
790                     }
791                     break;
792                     case am_D:
793                     {
794                         Expression::Ptr op(makeRegisterExpression(IntelRegTable(m_Arch,b_dr,locs->modrm_reg)));
795                         insn_to_complete->appendOperand(op, isRead, isWritten);
796                     }
797                     break;
798                     case am_E:
799                     // am_M is like am_E, except that mod of 0x03 should never occur (am_M specified memory,
800                     // mod of 0x03 specifies direct register access).
801                     case am_M:
802                     // am_R is the inverse of am_M; it should only have a mod of 3
803                     case am_R:
804                     // can be am_R or am_M      
805                     case am_RM: 
806                         if(isCFT)
807                         {
808                           insn_to_complete->addSuccessor(makeModRMExpression(b, optype), isCall, true, false, false);
809                         }
810                         else
811                         {
812                           insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
813                         }
814                     break;
815                     case am_F:
816                     {
817                         Expression::Ptr op(makeRegisterExpression(x86::flags));
818                         insn_to_complete->appendOperand(op, isRead, isWritten);
819                     }
820                     break;
821                     case am_G:
822                     {
823                         Expression::Ptr op(makeRegisterExpression(makeRegisterID(locs->modrm_reg,
824                                 optype, locs->rex_r)));
825                         insn_to_complete->appendOperand(op, isRead, isWritten);
826                     }
827                     break;
828                     case am_I:
829                         insn_to_complete->appendOperand(decodeImmediate(optype, b.start + 
830                                                                         locs->imm_position[imm_index++]), 
831                                                         isRead, isWritten);
832                         break;
833                     case am_J:
834                     {
835                         Expression::Ptr Offset(decodeImmediate(optype, 
836                                                                b.start + locs->imm_position[imm_index++], 
837                                                                true));
838                         Expression::Ptr EIP(makeRegisterExpression(MachRegister::getPC(m_Arch)));
839                         Expression::Ptr InsnSize(make_shared(singleton_object_pool<Immediate>::construct(Result(u8,
840                             decodedInstruction->getSize()))));
841                         Expression::Ptr postEIP(makeAddExpression(EIP, InsnSize, u32));
842
843                         Expression::Ptr op(makeAddExpression(Offset, postEIP, u32));
844                         insn_to_complete->addSuccessor(op, isCall, false, isConditional, false);
845                         if (isConditional) 
846                           insn_to_complete->addSuccessor(postEIP, false, false, true, true);
847                     }
848                     break;
849                     case am_O:
850                     {
851                     // Address/offset width, which is *not* what's encoded by the optype...
852                     // The deref's width is what's actually encoded here.
853                         int pseudoOpType;
854                         switch(locs->address_size)
855                         {
856                             case 1:
857                                 pseudoOpType = op_b;
858                                 break;
859                             case 2:
860                                 pseudoOpType = op_w;
861                                 break;
862                             case 4:
863                                 pseudoOpType = op_d;
864                                 break;
865                             case 0:
866                                 if(m_Arch == Arch_x86_64) {
867                                     pseudoOpType = op_q;
868                                 } else {
869                                     pseudoOpType = op_v;
870                                 }
871                                 break;
872                             default:
873                                 assert(!"Bad address size, should be 0, 1, 2, or 4!");
874                                 pseudoOpType = op_b;
875                                 break;
876                         }
877
878
879                         int offset_position = locs->opcode_position;
880                         if(locs->modrm_position > offset_position && locs->modrm_operand <
881                            (int)(insn_to_complete->m_Operands.size()))
882                         {
883                             offset_position = locs->modrm_position;
884                         }
885                         if(locs->sib_position > offset_position)
886                         {
887                             offset_position = locs->sib_position;
888                         }
889                         offset_position++;
890                         insn_to_complete->appendOperand(makeDereferenceExpression(
891                                 decodeImmediate(pseudoOpType, b.start + offset_position), makeSizeType(optype)), 
892                                                         isRead, isWritten);
893                     }
894                     break;
895                     case am_P:
896                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_reg)),
897                                 isRead, isWritten);
898                         break;
899                     case am_Q:
900         
901                         switch(locs->modrm_mod)
902                         {
903                             // direct dereference
904                             case 0x00:
905                             case 0x01:
906                             case 0x02:
907                               insn_to_complete->appendOperand(makeModRMExpression(b, optype), isRead, isWritten);
908                                 break;
909                             case 0x03:
910                                 // use of actual register
911                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_mm,locs->modrm_rm)),
912                                                                isRead, isWritten);
913                                 break;
914                             default:
915                                 assert(!"2-bit value modrm_mod out of range");
916                                 break;
917                         };
918                         break;
919                     case am_S:
920                     // Segment register in modrm reg field.
921                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_segment,locs->modrm_reg)),
922                                 isRead, isWritten);
923                         break;
924                     case am_T:
925                         // test register in modrm reg; should only be tr6/tr7, but we'll decode any of them
926                         // NOTE: this only appears in deprecated opcodes
927                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,b_tr,locs->modrm_reg)),
928                                                        isRead, isWritten);
929                         break;
930                     case am_UM:
931                         switch(locs->modrm_mod)
932                         {
933                         // direct dereference
934                         case 0x00:
935                         case 0x01:
936                         case 0x02:
937                                 insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
938                                                 isRead, isWritten);
939                                 break;
940                         case 0x03:
941                                 // use of actual register
942                                 {
943                                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
944                                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
945                                                         isRead, isWritten);
946                                         break;
947                                 }
948                         default:
949                                 assert(!"2-bit value modrm_mod out of range");
950                                 break;
951                         };
952                         break;
953                     case am_V:
954                        
955                         insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
956                                 locs->rex_r ? b_xmmhigh : b_xmm,locs->modrm_reg)),
957                                     isRead, isWritten);
958                         break;
959                     case am_W:
960                         switch(locs->modrm_mod)
961                         {
962                             // direct dereference
963                             case 0x00:
964                             case 0x01:
965                             case 0x02:
966                               insn_to_complete->appendOperand(makeModRMExpression(b, makeSizeType(optype)),
967                                                                isRead, isWritten);
968                                 break;
969                             case 0x03:
970                             // use of actual register
971                             {
972                                 insn_to_complete->appendOperand(makeRegisterExpression(IntelRegTable(m_Arch,
973                                         locs->rex_b ? b_xmmhigh : b_xmm, locs->modrm_rm)),
974                                         isRead, isWritten);
975                                 break;
976                             }
977                             default:
978                                 assert(!"2-bit value modrm_mod out of range");
979                                 break;
980                         };
981                         break;
982                     case am_X:
983                     {
984                         MachRegister si_reg;
985                         if(m_Arch == Arch_x86)
986                         {
987                                 if(addrSizePrefixPresent)
988                                 {
989                                         si_reg = x86::si;
990                                 } else
991                                 {
992                                         si_reg = x86::esi;
993                                 }
994                         }
995                         else
996                         {
997                                 if(addrSizePrefixPresent)
998                                 {
999                                         si_reg = x86_64::esi;
1000                                 } else
1001                                 {
1002                                         si_reg = x86_64::rsi;
1003                                 }
1004                         }
1005                         Expression::Ptr ds(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ds : x86_64::ds));
1006                         Expression::Ptr si(makeRegisterExpression(si_reg));
1007                         Expression::Ptr segmentOffset(make_shared(singleton_object_pool<Immediate>::construct(
1008                                 Result(u32, 0x10))));
1009                         Expression::Ptr ds_segment = makeMultiplyExpression(ds, segmentOffset, u32);
1010                         Expression::Ptr ds_si = makeAddExpression(ds_segment, si, u32);
1011                         insn_to_complete->appendOperand(makeDereferenceExpression(ds_si, makeSizeType(optype)),
1012                                                        isRead, isWritten);
1013                     }
1014                     break;
1015                     case am_Y:
1016                     {
1017                         MachRegister di_reg;
1018                         if(m_Arch == Arch_x86)
1019                         {
1020                                 if(addrSizePrefixPresent)
1021                                 {
1022                                         di_reg = x86::di;
1023                                 } else
1024                                 {
1025                                         di_reg = x86::edi;
1026                                 }
1027                         }
1028                         else
1029                         {
1030                                 if(addrSizePrefixPresent)
1031                                 {
1032                                         di_reg = x86_64::edi;
1033                                 } else
1034                                 {
1035                                         di_reg = x86_64::rdi;
1036                                 }
1037                         }
1038                         Expression::Ptr es(makeRegisterExpression(m_Arch == Arch_x86 ? x86::es : x86_64::es));
1039                         Expression::Ptr di(makeRegisterExpression(di_reg));
1040                         Expression::Ptr es_segment = makeMultiplyExpression(es,
1041                             make_shared(singleton_object_pool<Immediate>::construct(Result(u32, 0x10))), u32);
1042                         Expression::Ptr es_di = makeAddExpression(es_segment, di, u32);
1043                         insn_to_complete->appendOperand(makeDereferenceExpression(es_di, makeSizeType(optype)),
1044                                                        isRead, isWritten);
1045                     }
1046                     break;
1047                     case am_tworeghack:
1048                     {
1049                         if(optype == op_edxeax)
1050                         {
1051                             Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx));
1052                             Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax));
1053                             Expression::Ptr highAddr = makeMultiplyExpression(edx,
1054                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1055                             Expression::Ptr addr = makeAddExpression(highAddr, eax, u64);
1056                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1057                             insn_to_complete->appendOperand(op, isRead, isWritten);
1058                         }
1059                         else if (optype == op_ecxebx)
1060                         {
1061                             Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx));
1062                             Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx));
1063                             Expression::Ptr highAddr = makeMultiplyExpression(ecx,
1064                                     Immediate::makeImmediate(Result(u64, 2^32)), u64);
1065                             Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64);
1066                             Expression::Ptr op = makeDereferenceExpression(addr, u64);
1067                             insn_to_complete->appendOperand(op, isRead, isWritten);
1068                         }
1069                     }
1070                     break;
1071                     
1072                     case am_reg:
1073                     {
1074                         MachRegister r(optype);
1075                         if((m_Arch == Arch_x86_64) && (r.regClass() == x86::GPR) && (r.size() == 4))
1076                         {
1077                             int reg_size = isDefault64Insn() ? op_q : op_v;
1078                             // implicit regs are not extended
1079                             r = makeRegisterID((r.val() & 0xFF), reg_size, false);
1080                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1081                             if(locs->rex_b && insn_to_complete->m_Operands.empty() &&
1082                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0)))
1083                             {
1084                                 r = MachRegister((r.val()) | x86_64::r8.val());
1085                             }
1086                         }
1087                         else 
1088                         {
1089                             r = MachRegister((r.val() & ~r.getArchitecture()) | m_Arch);
1090                             
1091                             entryID entryid = decodedInstruction->getEntry()->getID(locs);
1092                             if(locs->rex_b && insn_to_complete->m_Operands.empty() && 
1093                                (entryid == e_push || entryid == e_pop || entryid == e_xchg || ((*(b.start + locs->opcode_position) & 0xf0) == 0xb0) ) )
1094                             {
1095                                 // FP stack registers are not affected by the rex_b bit in AM_REG.
1096                                 if(r.regClass() != (unsigned) x86::MMX)
1097                                 {
1098                                     r = MachRegister((r.val()) | x86_64::r8.val());
1099                                 }
1100                             }
1101                             if(sizePrefixPresent)
1102                             {
1103                                 r = MachRegister((r.val() & ~x86::FULL) | x86::W_REG);
1104                             }
1105                         }
1106                         Expression::Ptr op(makeRegisterExpression(r));
1107                         insn_to_complete->appendOperand(op, isRead, isWritten);
1108                     }
1109                     break;
1110                 case am_stackH:
1111                 case am_stackP:
1112                 // handled elsewhere
1113                     break;
1114                 case am_allgprs:
1115                 {
1116                     if(m_Arch == Arch_x86)
1117                     {
1118                         insn_to_complete->appendOperand(makeRegisterExpression(x86::eax), isRead, isWritten);
1119                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ecx), isRead, isWritten);
1120                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edx), isRead, isWritten);
1121                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebx), isRead, isWritten);
1122                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esp), isRead, isWritten);
1123                         insn_to_complete->appendOperand(makeRegisterExpression(x86::ebp), isRead, isWritten);
1124                         insn_to_complete->appendOperand(makeRegisterExpression(x86::esi), isRead, isWritten);
1125                         insn_to_complete->appendOperand(makeRegisterExpression(x86::edi), isRead, isWritten);
1126                     }
1127                     else
1128                     {
1129                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::eax), isRead, isWritten);
1130                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ecx), isRead, isWritten);
1131                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edx), isRead, isWritten);
1132                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebx), isRead, isWritten);
1133                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esp), isRead, isWritten);
1134                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::ebp), isRead, isWritten);
1135                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::esi), isRead, isWritten);
1136                         insn_to_complete->appendOperand(makeRegisterExpression(x86_64::edi), isRead, isWritten);
1137                     }
1138                 }
1139                     break;
1140                 case am_ImplImm: {
1141                   insn_to_complete->appendOperand(Immediate::makeImmediate(Result(makeSizeType(optype), 1)), isRead, isWritten);
1142                   break;
1143                 }
1144
1145                 default:
1146                     printf("decodeOneOperand() called with unknown addressing method %d\n", operand.admet);
1147                         break;
1148                 };
1149                 return true;
1150             }
1151
1152     extern ia32_entry invalid;
1153     
1154     void InstructionDecoder_x86::doIA32Decode(InstructionDecoder::buffer& b)
1155     {
1156         if(decodedInstruction == NULL)
1157         {
1158             decodedInstruction = reinterpret_cast<ia32_instruction*>(malloc(sizeof(ia32_instruction)));
1159             assert(decodedInstruction);
1160         }
1161         if(locs == NULL)
1162         {
1163             locs = reinterpret_cast<ia32_locations*>(malloc(sizeof(ia32_locations)));
1164             assert(locs);
1165         }
1166         locs = new(locs) ia32_locations; //reinit();
1167         assert(locs->sib_position == -1);
1168         decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs);
1169         ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction);
1170         sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66);
1171         if (decodedInstruction->getPrefix()->rexW()) {
1172            // as per 2.2.1.2 - rex.w overrides 66h
1173            sizePrefixPresent = false;
1174         }
1175         addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67);
1176         static ia32_entry invalid = { e_No_Entry, 0, 0, true, { {0,0}, {0,0}, {0,0} }, 0, 0 };
1177         if(decodedInstruction->getEntry()) {
1178             m_Operation = make_shared(singleton_object_pool<Operation>::construct(decodedInstruction->getEntry(),
1179                                     decodedInstruction->getPrefix(), locs, m_Arch));
1180             
1181         }
1182         else
1183         {
1184                 // Gap parsing can trigger this case; in particular, when it encounters prefixes in an invalid order.
1185                 // Notably, if a REX prefix (0x40-0x48) appears followed by another prefix (0x66, 0x67, etc)
1186                 // we'll reject the instruction as invalid and send it back with no entry.  Since this is a common
1187                 // byte sequence to see in, for example, ASCII strings, we want to simply accept this and move on, not
1188                 // yell at the user.
1189             m_Operation = make_shared(singleton_object_pool<Operation>::construct(&invalid,
1190                                     decodedInstruction->getPrefix(), locs, m_Arch));
1191         }
1192
1193     }
1194     
1195     void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b)
1196     {
1197         doIA32Decode(b);
1198         b.start += decodedInstruction->getSize();
1199     }
1200     
1201       bool InstructionDecoder_x86::decodeOperands(const Instruction* insn_to_complete)
1202     {
1203        int imm_index = 0; // handle multiple immediate operands
1204         if(!decodedInstruction) return false;
1205         unsigned int opsema = decodedInstruction->getEntry()->opsema & 0xFF;
1206         InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1207
1208         if (decodedInstruction->getEntry()->getID() == e_ret_near ||
1209             decodedInstruction->getEntry()->getID() == e_ret_far) {
1210            Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(ia32_is_mode_64() ? x86_64::rsp : x86::esp), 
1211                                                                 ia32_is_mode_64() ? u64 : u32);
1212            insn_to_complete->addSuccessor(ret_addr, false, true, false, false);
1213         }
1214
1215         for(unsigned i = 0; i < 3; i++)
1216         {
1217             if(decodedInstruction->getEntry()->operands[i].admet == 0 && 
1218                decodedInstruction->getEntry()->operands[i].optype == 0)
1219                 return true;
1220             if(!decodeOneOperand(b,
1221                                  decodedInstruction->getEntry()->operands[i], 
1222                                  imm_index, 
1223                                  insn_to_complete, 
1224                                  readsOperand(opsema, i),
1225                                  writesOperand(opsema, i)))
1226             {
1227                 return false;
1228             }
1229         }
1230     
1231         return true;
1232     }
1233
1234     
1235       INSTRUCTION_EXPORT Instruction::Ptr InstructionDecoder_x86::decode(InstructionDecoder::buffer& b)
1236     {
1237         return InstructionDecoderImpl::decode(b);
1238     }
1239     void InstructionDecoder_x86::doDelayedDecode(const Instruction* insn_to_complete)
1240     {
1241       InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size());
1242       //insn_to_complete->m_Operands.reserve(4);
1243       doIA32Decode(b);        
1244       decodeOperands(insn_to_complete);
1245     }
1246     
1247 };
1248 };
1249