Remove bluegene support (#847)
[dyninst.git] / external / cvconst / cvconst.h
1 /////////////////////////////////////////////////////////////////////////////// 
2 // 
3 // Copyright (c) 2015 Microsoft Corporation. All rights reserved. 
4 // 
5 // This code is licensed under the MIT License (MIT). 
6 // 
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
8 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
9 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
10 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
11 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
12 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
13 // THE SOFTWARE. 
14 // 
15 ///////////////////////////////////////////////////////////////////////////////
16
17 // cvconst.h - codeview constant definitions
18 //-----------------------------------------------------------------
19 //
20 // Copyright Microsoft Corporation.  All Rights Reserved.
21 //
22 //---------------------------------------------------------------
23 #ifndef _CVCONST_H_
24 #define _CVCONST_H_
25
26
27
28 //      Enumeration for function call type
29
30
31 typedef enum CV_call_e {
32     CV_CALL_NEAR_C      = 0x00, // near right to left push, caller pops stack
33     CV_CALL_FAR_C       = 0x01, // far right to left push, caller pops stack
34     CV_CALL_NEAR_PASCAL = 0x02, // near left to right push, callee pops stack
35     CV_CALL_FAR_PASCAL  = 0x03, // far left to right push, callee pops stack
36     CV_CALL_NEAR_FAST   = 0x04, // near left to right push with regs, callee pops stack
37     CV_CALL_FAR_FAST    = 0x05, // far left to right push with regs, callee pops stack
38     CV_CALL_SKIPPED     = 0x06, // skipped (unused) call index
39     CV_CALL_NEAR_STD    = 0x07, // near standard call
40     CV_CALL_FAR_STD     = 0x08, // far standard call
41     CV_CALL_NEAR_SYS    = 0x09, // near sys call
42     CV_CALL_FAR_SYS     = 0x0a, // far sys call
43     CV_CALL_THISCALL    = 0x0b, // this call (this passed in register)
44     CV_CALL_MIPSCALL    = 0x0c, // Mips call
45     CV_CALL_GENERIC     = 0x0d, // Generic call sequence
46     CV_CALL_ALPHACALL   = 0x0e, // Alpha call
47     CV_CALL_PPCCALL     = 0x0f, // PPC call
48     CV_CALL_SHCALL      = 0x10, // Hitachi SuperH call
49     CV_CALL_ARMCALL     = 0x11, // ARM call
50     CV_CALL_AM33CALL    = 0x12, // AM33 call
51     CV_CALL_TRICALL     = 0x13, // TriCore Call
52     CV_CALL_SH5CALL     = 0x14, // Hitachi SuperH-5 call
53     CV_CALL_M32RCALL    = 0x15, // M32R Call
54     CV_CALL_CLRCALL     = 0x16, // clr call
55     CV_CALL_INLINE      = 0x17, // Marker for routines always inlined and thus lacking a convention
56     CV_CALL_NEAR_VECTOR = 0x18, // near left to right push with regs, callee pops stack
57     CV_CALL_RESERVED    = 0x19  // first unused call enumeration
58
59     // Do NOT add any more machine specific conventions.  This is to be used for
60     // calling conventions in the source only (e.g. __cdecl, __stdcall).
61 } CV_call_e;
62
63
64 //      Values for the access protection of class attributes
65
66
67 typedef enum CV_access_e {
68     CV_private   = 1,
69     CV_protected = 2,
70     CV_public    = 3
71 } CV_access_e;
72
73 typedef enum THUNK_ORDINAL {
74     THUNK_ORDINAL_NOTYPE,       // standard thunk
75     THUNK_ORDINAL_ADJUSTOR,     // "this" adjustor thunk
76     THUNK_ORDINAL_VCALL,        // virtual call thunk
77     THUNK_ORDINAL_PCODE,        // pcode thunk
78     THUNK_ORDINAL_LOAD,         // thunk which loads the address to jump to
79                                 //  via unknown means...
80
81  // trampoline thunk ordinals   - only for use in Trampoline thunk symbols
82     THUNK_ORDINAL_TRAMP_INCREMENTAL,
83     THUNK_ORDINAL_TRAMP_BRANCHISLAND,
84
85 } THUNK_ORDINAL;
86
87
88 enum CV_SourceChksum_t {
89     CHKSUM_TYPE_NONE = 0,        // indicates no checksum is available
90     CHKSUM_TYPE_MD5,
91     CHKSUM_TYPE_SHA1,
92     CHKSUM_TYPE_SHA_256,
93 };
94
95 //
96 // DIA enums
97 //
98
99 enum SymTagEnum
100 {
101     SymTagNull,
102     SymTagExe,
103     SymTagCompiland,
104     SymTagCompilandDetails,
105     SymTagCompilandEnv,
106     SymTagFunction,
107     SymTagBlock,
108     SymTagData,
109     SymTagAnnotation,
110     SymTagLabel,
111     SymTagPublicSymbol,
112     SymTagUDT,
113     SymTagEnum,
114     SymTagFunctionType,
115     SymTagPointerType,
116     SymTagArrayType,
117     SymTagBaseType,
118     SymTagTypedef,
119     SymTagBaseClass,
120     SymTagFriend,
121     SymTagFunctionArgType,
122     SymTagFuncDebugStart,
123     SymTagFuncDebugEnd,
124     SymTagUsingNamespace,
125     SymTagVTableShape,
126     SymTagVTable,
127     SymTagCustom,
128     SymTagThunk,
129     SymTagCustomType,
130     SymTagManagedType,
131     SymTagDimension,
132     SymTagCallSite,
133     SymTagInlineSite,
134     SymTagBaseInterface,
135     SymTagVectorType,
136     SymTagMatrixType,
137     SymTagHLSLType,
138     SymTagCaller,
139     SymTagCallee,
140     SymTagExport,
141     SymTagHeapAllocationSite,
142     SymTagCoffGroup,
143     SymTagMax
144 };
145
146 enum LocationType
147 {
148     LocIsNull,
149     LocIsStatic,
150     LocIsTLS,
151     LocIsRegRel,
152     LocIsThisRel,
153     LocIsEnregistered,
154     LocIsBitField,
155     LocIsSlot,
156     LocIsIlRel,
157     LocInMetaData,
158     LocIsConstant,
159     LocTypeMax
160 };
161
162 enum DataKind
163 {
164     DataIsUnknown,
165     DataIsLocal,
166     DataIsStaticLocal,
167     DataIsParam,
168     DataIsObjectPtr,
169     DataIsFileStatic,
170     DataIsGlobal,
171     DataIsMember,
172     DataIsStaticMember,
173     DataIsConstant
174 };
175
176 enum UdtKind
177 {
178     UdtStruct,
179     UdtClass,
180     UdtUnion,
181     UdtInterface
182 };
183
184 enum BasicType
185 {
186     btNoType = 0,
187     btVoid = 1,
188     btChar = 2,
189     btWChar = 3,
190     btInt = 6,
191     btUInt = 7,
192     btFloat = 8,
193     btBCD = 9,
194     btBool = 10,
195     btLong = 13,
196     btULong = 14,
197     btCurrency = 25,
198     btDate = 26,
199     btVariant = 27,
200     btComplex = 28,
201     btBit = 29,
202     btBSTR = 30,
203     btHresult = 31,
204     btChar16 = 32,  // char16_t
205     btChar32 = 33,  // char32_t
206 };
207
208
209 //      enumeration for type modifier values
210
211 typedef enum CV_modifier_e {
212     // 0x0000 - 0x01ff - Reserved.
213
214     CV_MOD_INVALID                      = 0x0000,
215
216     // Standard modifiers.
217
218     CV_MOD_CONST                        = 0x0001,
219     CV_MOD_VOLATILE                     = 0x0002,
220     CV_MOD_UNALIGNED                    = 0x0003,
221     
222     // 0x0200 - 0x03ff - HLSL modifiers.
223
224     CV_MOD_HLSL_UNIFORM                 = 0x0200,
225     CV_MOD_HLSL_LINE                    = 0x0201,
226     CV_MOD_HLSL_TRIANGLE                = 0x0202,
227     CV_MOD_HLSL_LINEADJ                 = 0x0203,
228     CV_MOD_HLSL_TRIANGLEADJ             = 0x0204,
229     CV_MOD_HLSL_LINEAR                  = 0x0205,
230     CV_MOD_HLSL_CENTROID                = 0x0206,
231     CV_MOD_HLSL_CONSTINTERP             = 0x0207,
232     CV_MOD_HLSL_NOPERSPECTIVE           = 0x0208,
233     CV_MOD_HLSL_SAMPLE                  = 0x0209,
234     CV_MOD_HLSL_CENTER                  = 0x020a,
235     CV_MOD_HLSL_SNORM                   = 0x020b,
236     CV_MOD_HLSL_UNORM                   = 0x020c,
237     CV_MOD_HLSL_PRECISE                 = 0x020d,
238     CV_MOD_HLSL_UAV_GLOBALLY_COHERENT   = 0x020e,
239
240     // 0x0400 - 0xffff - Unused.
241     
242 } CV_modifier_e;
243
244
245 //      built-in type kinds
246
247
248 typedef enum CV_builtin_e {
249
250     // 0x0000 - 0x01ff - Reserved.
251     CV_BI_INVALID                       = 0x0000,
252     
253     // 0x0200 - 0x03ff - HLSL types.
254
255     CV_BI_HLSL_INTERFACE_POINTER        = 0x0200,
256     CV_BI_HLSL_TEXTURE1D                = 0x0201,
257     CV_BI_HLSL_TEXTURE1D_ARRAY          = 0x0202,
258     CV_BI_HLSL_TEXTURE2D                = 0x0203,
259     CV_BI_HLSL_TEXTURE2D_ARRAY          = 0x0204,
260     CV_BI_HLSL_TEXTURE3D                = 0x0205,
261     CV_BI_HLSL_TEXTURECUBE              = 0x0206,
262     CV_BI_HLSL_TEXTURECUBE_ARRAY        = 0x0207,
263     CV_BI_HLSL_TEXTURE2DMS              = 0x0208,
264     CV_BI_HLSL_TEXTURE2DMS_ARRAY        = 0x0209,
265     CV_BI_HLSL_SAMPLER                  = 0x020a,
266     CV_BI_HLSL_SAMPLERCOMPARISON        = 0x020b,
267     CV_BI_HLSL_BUFFER                   = 0x020c,
268     CV_BI_HLSL_POINTSTREAM              = 0x020d,
269     CV_BI_HLSL_LINESTREAM               = 0x020e,
270     CV_BI_HLSL_TRIANGLESTREAM           = 0x020f,
271     CV_BI_HLSL_INPUTPATCH               = 0x0210,
272     CV_BI_HLSL_OUTPUTPATCH              = 0x0211,
273     CV_BI_HLSL_RWTEXTURE1D              = 0x0212,
274     CV_BI_HLSL_RWTEXTURE1D_ARRAY        = 0x0213,
275     CV_BI_HLSL_RWTEXTURE2D              = 0x0214,
276     CV_BI_HLSL_RWTEXTURE2D_ARRAY        = 0x0215,
277     CV_BI_HLSL_RWTEXTURE3D              = 0x0216,
278     CV_BI_HLSL_RWBUFFER                 = 0x0217,
279     CV_BI_HLSL_BYTEADDRESS_BUFFER       = 0x0218,
280     CV_BI_HLSL_RWBYTEADDRESS_BUFFER     = 0x0219,
281     CV_BI_HLSL_STRUCTURED_BUFFER        = 0x021a,
282     CV_BI_HLSL_RWSTRUCTURED_BUFFER      = 0x021b,
283     CV_BI_HLSL_APPEND_STRUCTURED_BUFFER = 0x021c,
284     CV_BI_HLSL_CONSUME_STRUCTURED_BUFFER= 0x021d,
285     CV_BI_HLSL_MIN8FLOAT                = 0x021e,
286     CV_BI_HLSL_MIN10FLOAT               = 0x021f,
287     CV_BI_HLSL_MIN16FLOAT               = 0x0220,
288     CV_BI_HLSL_MIN12INT                 = 0x0221,
289     CV_BI_HLSL_MIN16INT                 = 0x0222,
290     CV_BI_HLSL_MIN16UINT                = 0x0223,
291
292     // 0x0400 - 0xffff - Unused.
293     
294 } CV_builtin_e;
295
296
297 //  enum describing the compile flag source language
298
299
300 typedef enum CV_CFL_LANG {
301     CV_CFL_C        = 0x00,
302     CV_CFL_CXX      = 0x01,
303     CV_CFL_FORTRAN  = 0x02,
304     CV_CFL_MASM     = 0x03,
305     CV_CFL_PASCAL   = 0x04,
306     CV_CFL_BASIC    = 0x05,
307     CV_CFL_COBOL    = 0x06,
308     CV_CFL_LINK     = 0x07,
309     CV_CFL_CVTRES   = 0x08,
310     CV_CFL_CVTPGD   = 0x09,
311     CV_CFL_CSHARP   = 0x0A,  // C#
312     CV_CFL_VB       = 0x0B,  // Visual Basic
313     CV_CFL_ILASM    = 0x0C,  // IL (as in CLR) ASM
314     CV_CFL_JAVA     = 0x0D,
315     CV_CFL_JSCRIPT  = 0x0E,
316     CV_CFL_MSIL     = 0x0F,  // Unknown MSIL (LTCG of .NETMODULE)
317     CV_CFL_HLSL     = 0x10,  // High Level Shader Language
318 } CV_CFL_LANG;
319
320
321 //  enum describing target processor
322
323
324 typedef enum CV_CPU_TYPE_e {
325     CV_CFL_8080         = 0x00,
326     CV_CFL_8086         = 0x01,
327     CV_CFL_80286        = 0x02,
328     CV_CFL_80386        = 0x03,
329     CV_CFL_80486        = 0x04,
330     CV_CFL_PENTIUM      = 0x05,
331     CV_CFL_PENTIUMII    = 0x06,
332     CV_CFL_PENTIUMPRO   = CV_CFL_PENTIUMII,
333     CV_CFL_PENTIUMIII   = 0x07,
334     CV_CFL_MIPS         = 0x10,
335     CV_CFL_MIPSR4000    = CV_CFL_MIPS,  // don't break current code
336     CV_CFL_MIPS16       = 0x11,
337     CV_CFL_MIPS32       = 0x12,
338     CV_CFL_MIPS64       = 0x13,
339     CV_CFL_MIPSI        = 0x14,
340     CV_CFL_MIPSII       = 0x15,
341     CV_CFL_MIPSIII      = 0x16,
342     CV_CFL_MIPSIV       = 0x17,
343     CV_CFL_MIPSV        = 0x18,
344     CV_CFL_M68000       = 0x20,
345     CV_CFL_M68010       = 0x21,
346     CV_CFL_M68020       = 0x22,
347     CV_CFL_M68030       = 0x23,
348     CV_CFL_M68040       = 0x24,
349     CV_CFL_ALPHA        = 0x30,
350     CV_CFL_ALPHA_21064  = 0x30,
351     CV_CFL_ALPHA_21164  = 0x31,
352     CV_CFL_ALPHA_21164A = 0x32,
353     CV_CFL_ALPHA_21264  = 0x33,
354     CV_CFL_ALPHA_21364  = 0x34,
355     CV_CFL_PPC601       = 0x40,
356     CV_CFL_PPC603       = 0x41,
357     CV_CFL_PPC604       = 0x42,
358     CV_CFL_PPC620       = 0x43,
359     CV_CFL_PPCFP        = 0x44,
360     CV_CFL_PPCBE        = 0x45,
361     CV_CFL_SH3          = 0x50,
362     CV_CFL_SH3E         = 0x51,
363     CV_CFL_SH3DSP       = 0x52,
364     CV_CFL_SH4          = 0x53,
365     CV_CFL_SHMEDIA      = 0x54,
366     CV_CFL_ARM3         = 0x60,
367     CV_CFL_ARM4         = 0x61,
368     CV_CFL_ARM4T        = 0x62,
369     CV_CFL_ARM5         = 0x63,
370     CV_CFL_ARM5T        = 0x64,
371     CV_CFL_ARM6         = 0x65,
372     CV_CFL_ARM_XMAC     = 0x66,
373     CV_CFL_ARM_WMMX     = 0x67,
374     CV_CFL_ARM7         = 0x68,
375     CV_CFL_OMNI         = 0x70,
376     CV_CFL_IA64         = 0x80,
377     CV_CFL_IA64_1       = 0x80,
378     CV_CFL_IA64_2       = 0x81,
379     CV_CFL_CEE          = 0x90,
380     CV_CFL_AM33         = 0xA0,
381     CV_CFL_M32R         = 0xB0,
382     CV_CFL_TRICORE      = 0xC0,
383     CV_CFL_X64          = 0xD0,
384     CV_CFL_AMD64        = CV_CFL_X64,
385     CV_CFL_EBC          = 0xE0,
386     CV_CFL_THUMB        = 0xF0,
387     CV_CFL_ARMNT        = 0xF4,
388     CV_CFL_ARM64        = 0xF6,
389     CV_CFL_D3D11_SHADER = 0x100,
390 } CV_CPU_TYPE_e;
391
392 typedef enum CV_HREG_e {
393     // Register subset shared by all processor types,
394     // must not overlap with any of the ranges below, hence the high values
395
396     CV_ALLREG_ERR   =   30000,
397     CV_ALLREG_TEB   =   30001,
398     CV_ALLREG_TIMER =   30002,
399     CV_ALLREG_EFAD1 =   30003,
400     CV_ALLREG_EFAD2 =   30004,
401     CV_ALLREG_EFAD3 =   30005,
402     CV_ALLREG_VFRAME=   30006,
403     CV_ALLREG_HANDLE=   30007,
404     CV_ALLREG_PARAMS=   30008,
405     CV_ALLREG_LOCALS=   30009,
406     CV_ALLREG_TID   =   30010,
407     CV_ALLREG_ENV   =   30011,
408     CV_ALLREG_CMDLN =   30012,
409
410
411     //  Register set for the Intel 80x86 and ix86 processor series
412     //  (plus PCODE registers)
413
414     CV_REG_NONE     =   0,
415     CV_REG_AL       =   1,
416     CV_REG_CL       =   2,
417     CV_REG_DL       =   3,
418     CV_REG_BL       =   4,
419     CV_REG_AH       =   5,
420     CV_REG_CH       =   6,
421     CV_REG_DH       =   7,
422     CV_REG_BH       =   8,
423     CV_REG_AX       =   9,
424     CV_REG_CX       =  10,
425     CV_REG_DX       =  11,
426     CV_REG_BX       =  12,
427     CV_REG_SP       =  13,
428     CV_REG_BP       =  14,
429     CV_REG_SI       =  15,
430     CV_REG_DI       =  16,
431     CV_REG_EAX      =  17,
432     CV_REG_ECX      =  18,
433     CV_REG_EDX      =  19,
434     CV_REG_EBX      =  20,
435     CV_REG_ESP      =  21,
436     CV_REG_EBP      =  22,
437     CV_REG_ESI      =  23,
438     CV_REG_EDI      =  24,
439     CV_REG_ES       =  25,
440     CV_REG_CS       =  26,
441     CV_REG_SS       =  27,
442     CV_REG_DS       =  28,
443     CV_REG_FS       =  29,
444     CV_REG_GS       =  30,
445     CV_REG_IP       =  31,
446     CV_REG_FLAGS    =  32,
447     CV_REG_EIP      =  33,
448     CV_REG_EFLAGS   =  34,
449     CV_REG_TEMP     =  40,          // PCODE Temp
450     CV_REG_TEMPH    =  41,          // PCODE TempH
451     CV_REG_QUOTE    =  42,          // PCODE Quote
452     CV_REG_PCDR3    =  43,          // PCODE reserved
453     CV_REG_PCDR4    =  44,          // PCODE reserved
454     CV_REG_PCDR5    =  45,          // PCODE reserved
455     CV_REG_PCDR6    =  46,          // PCODE reserved
456     CV_REG_PCDR7    =  47,          // PCODE reserved
457     CV_REG_CR0      =  80,          // CR0 -- control registers
458     CV_REG_CR1      =  81,
459     CV_REG_CR2      =  82,
460     CV_REG_CR3      =  83,
461     CV_REG_CR4      =  84,          // Pentium
462     CV_REG_DR0      =  90,          // Debug register
463     CV_REG_DR1      =  91,
464     CV_REG_DR2      =  92,
465     CV_REG_DR3      =  93,
466     CV_REG_DR4      =  94,
467     CV_REG_DR5      =  95,
468     CV_REG_DR6      =  96,
469     CV_REG_DR7      =  97,
470     CV_REG_GDTR     =  110,
471     CV_REG_GDTL     =  111,
472     CV_REG_IDTR     =  112,
473     CV_REG_IDTL     =  113,
474     CV_REG_LDTR     =  114,
475     CV_REG_TR       =  115,
476
477     CV_REG_PSEUDO1  =  116,
478     CV_REG_PSEUDO2  =  117,
479     CV_REG_PSEUDO3  =  118,
480     CV_REG_PSEUDO4  =  119,
481     CV_REG_PSEUDO5  =  120,
482     CV_REG_PSEUDO6  =  121,
483     CV_REG_PSEUDO7  =  122,
484     CV_REG_PSEUDO8  =  123,
485     CV_REG_PSEUDO9  =  124,
486
487     CV_REG_ST0      =  128,
488     CV_REG_ST1      =  129,
489     CV_REG_ST2      =  130,
490     CV_REG_ST3      =  131,
491     CV_REG_ST4      =  132,
492     CV_REG_ST5      =  133,
493     CV_REG_ST6      =  134,
494     CV_REG_ST7      =  135,
495     CV_REG_CTRL     =  136,
496     CV_REG_STAT     =  137,
497     CV_REG_TAG      =  138,
498     CV_REG_FPIP     =  139,
499     CV_REG_FPCS     =  140,
500     CV_REG_FPDO     =  141,
501     CV_REG_FPDS     =  142,
502     CV_REG_ISEM     =  143,
503     CV_REG_FPEIP    =  144,
504     CV_REG_FPEDO    =  145,
505
506     CV_REG_MM0      =  146,
507     CV_REG_MM1      =  147,
508     CV_REG_MM2      =  148,
509     CV_REG_MM3      =  149,
510     CV_REG_MM4      =  150,
511     CV_REG_MM5      =  151,
512     CV_REG_MM6      =  152,
513     CV_REG_MM7      =  153,
514
515     CV_REG_XMM0     =  154, // KATMAI registers
516     CV_REG_XMM1     =  155,
517     CV_REG_XMM2     =  156,
518     CV_REG_XMM3     =  157,
519     CV_REG_XMM4     =  158,
520     CV_REG_XMM5     =  159,
521     CV_REG_XMM6     =  160,
522     CV_REG_XMM7     =  161,
523
524     CV_REG_XMM00    =  162, // KATMAI sub-registers
525     CV_REG_XMM01    =  163,
526     CV_REG_XMM02    =  164,
527     CV_REG_XMM03    =  165,
528     CV_REG_XMM10    =  166,
529     CV_REG_XMM11    =  167,
530     CV_REG_XMM12    =  168,
531     CV_REG_XMM13    =  169,
532     CV_REG_XMM20    =  170,
533     CV_REG_XMM21    =  171,
534     CV_REG_XMM22    =  172,
535     CV_REG_XMM23    =  173,
536     CV_REG_XMM30    =  174,
537     CV_REG_XMM31    =  175,
538     CV_REG_XMM32    =  176,
539     CV_REG_XMM33    =  177,
540     CV_REG_XMM40    =  178,
541     CV_REG_XMM41    =  179,
542     CV_REG_XMM42    =  180,
543     CV_REG_XMM43    =  181,
544     CV_REG_XMM50    =  182,
545     CV_REG_XMM51    =  183,
546     CV_REG_XMM52    =  184,
547     CV_REG_XMM53    =  185,
548     CV_REG_XMM60    =  186,
549     CV_REG_XMM61    =  187,
550     CV_REG_XMM62    =  188,
551     CV_REG_XMM63    =  189,
552     CV_REG_XMM70    =  190,
553     CV_REG_XMM71    =  191,
554     CV_REG_XMM72    =  192,
555     CV_REG_XMM73    =  193,
556
557     CV_REG_XMM0L    =  194,
558     CV_REG_XMM1L    =  195,
559     CV_REG_XMM2L    =  196,
560     CV_REG_XMM3L    =  197,
561     CV_REG_XMM4L    =  198,
562     CV_REG_XMM5L    =  199,
563     CV_REG_XMM6L    =  200,
564     CV_REG_XMM7L    =  201,
565
566     CV_REG_XMM0H    =  202,
567     CV_REG_XMM1H    =  203,
568     CV_REG_XMM2H    =  204,
569     CV_REG_XMM3H    =  205,
570     CV_REG_XMM4H    =  206,
571     CV_REG_XMM5H    =  207,
572     CV_REG_XMM6H    =  208,
573     CV_REG_XMM7H    =  209,
574
575     CV_REG_MXCSR    =  211, // XMM status register
576
577     CV_REG_EDXEAX   =  212, // EDX:EAX pair
578
579     CV_REG_EMM0L    =  220, // XMM sub-registers (WNI integer)
580     CV_REG_EMM1L    =  221,
581     CV_REG_EMM2L    =  222,
582     CV_REG_EMM3L    =  223,
583     CV_REG_EMM4L    =  224,
584     CV_REG_EMM5L    =  225,
585     CV_REG_EMM6L    =  226,
586     CV_REG_EMM7L    =  227,
587
588     CV_REG_EMM0H    =  228,
589     CV_REG_EMM1H    =  229,
590     CV_REG_EMM2H    =  230,
591     CV_REG_EMM3H    =  231,
592     CV_REG_EMM4H    =  232,
593     CV_REG_EMM5H    =  233,
594     CV_REG_EMM6H    =  234,
595     CV_REG_EMM7H    =  235,
596
597     // do not change the order of these regs, first one must be even too
598     CV_REG_MM00     =  236,
599     CV_REG_MM01     =  237,
600     CV_REG_MM10     =  238,
601     CV_REG_MM11     =  239,
602     CV_REG_MM20     =  240,
603     CV_REG_MM21     =  241,
604     CV_REG_MM30     =  242,
605     CV_REG_MM31     =  243,
606     CV_REG_MM40     =  244,
607     CV_REG_MM41     =  245,
608     CV_REG_MM50     =  246,
609     CV_REG_MM51     =  247,
610     CV_REG_MM60     =  248,
611     CV_REG_MM61     =  249,
612     CV_REG_MM70     =  250,
613     CV_REG_MM71     =  251,
614
615     CV_REG_YMM0     =  252, // AVX registers
616     CV_REG_YMM1     =  253,
617     CV_REG_YMM2     =  254,
618     CV_REG_YMM3     =  255,
619     CV_REG_YMM4     =  256,
620     CV_REG_YMM5     =  257,
621     CV_REG_YMM6     =  258,
622     CV_REG_YMM7     =  259,
623
624     CV_REG_YMM0H    =  260,
625     CV_REG_YMM1H    =  261,
626     CV_REG_YMM2H    =  262,
627     CV_REG_YMM3H    =  263,
628     CV_REG_YMM4H    =  264,
629     CV_REG_YMM5H    =  265,
630     CV_REG_YMM6H    =  266,
631     CV_REG_YMM7H    =  267,
632
633     CV_REG_YMM0I0     =    268,    // AVX integer registers
634     CV_REG_YMM0I1     =    269,
635     CV_REG_YMM0I2     =    270,
636     CV_REG_YMM0I3     =    271,
637     CV_REG_YMM1I0     =    272,
638     CV_REG_YMM1I1     =    273,
639     CV_REG_YMM1I2     =    274,
640     CV_REG_YMM1I3     =    275,
641     CV_REG_YMM2I0     =    276,
642     CV_REG_YMM2I1     =    277,
643     CV_REG_YMM2I2     =    278,
644     CV_REG_YMM2I3     =    279,
645     CV_REG_YMM3I0     =    280,
646     CV_REG_YMM3I1     =    281,
647     CV_REG_YMM3I2     =    282,
648     CV_REG_YMM3I3     =    283,
649     CV_REG_YMM4I0     =    284,
650     CV_REG_YMM4I1     =    285,
651     CV_REG_YMM4I2     =    286,
652     CV_REG_YMM4I3     =    287,
653     CV_REG_YMM5I0     =    288,
654     CV_REG_YMM5I1     =    289,
655     CV_REG_YMM5I2     =    290,
656     CV_REG_YMM5I3     =    291,
657     CV_REG_YMM6I0     =    292,
658     CV_REG_YMM6I1     =    293,
659     CV_REG_YMM6I2     =    294,
660     CV_REG_YMM6I3     =    295,
661     CV_REG_YMM7I0     =    296,
662     CV_REG_YMM7I1     =    297,
663     CV_REG_YMM7I2     =    298,
664     CV_REG_YMM7I3     =    299,
665         
666     CV_REG_YMM0F0    =  300,     // AVX floating-point single precise registers
667     CV_REG_YMM0F1    =  301,
668     CV_REG_YMM0F2    =  302,
669     CV_REG_YMM0F3    =  303,
670     CV_REG_YMM0F4    =  304,
671     CV_REG_YMM0F5    =  305,
672     CV_REG_YMM0F6    =  306,
673     CV_REG_YMM0F7    =  307,
674     CV_REG_YMM1F0    =  308,
675     CV_REG_YMM1F1    =  309,
676     CV_REG_YMM1F2    =  310,
677     CV_REG_YMM1F3    =  311,
678     CV_REG_YMM1F4    =  312,
679     CV_REG_YMM1F5    =  313,
680     CV_REG_YMM1F6    =  314,
681     CV_REG_YMM1F7    =  315,
682     CV_REG_YMM2F0    =  316,
683     CV_REG_YMM2F1    =  317,
684     CV_REG_YMM2F2    =  318,
685     CV_REG_YMM2F3    =  319,
686     CV_REG_YMM2F4    =  320,
687     CV_REG_YMM2F5    =  321,
688     CV_REG_YMM2F6    =  322,
689     CV_REG_YMM2F7    =  323,
690     CV_REG_YMM3F0    =  324,
691     CV_REG_YMM3F1    =  325,
692     CV_REG_YMM3F2    =  326,
693     CV_REG_YMM3F3    =  327,
694     CV_REG_YMM3F4    =  328,
695     CV_REG_YMM3F5    =  329,
696     CV_REG_YMM3F6    =  330,
697     CV_REG_YMM3F7    =  331,
698     CV_REG_YMM4F0    =  332,
699     CV_REG_YMM4F1    =  333,
700     CV_REG_YMM4F2    =  334,
701     CV_REG_YMM4F3    =  335,
702     CV_REG_YMM4F4    =  336,
703     CV_REG_YMM4F5    =  337,
704     CV_REG_YMM4F6    =  338,
705     CV_REG_YMM4F7    =  339,
706     CV_REG_YMM5F0    =  340,
707     CV_REG_YMM5F1    =  341,
708     CV_REG_YMM5F2    =  342,
709     CV_REG_YMM5F3    =  343,
710     CV_REG_YMM5F4    =  344,
711     CV_REG_YMM5F5    =  345,
712     CV_REG_YMM5F6    =  346,
713     CV_REG_YMM5F7    =  347,
714     CV_REG_YMM6F0    =  348,
715     CV_REG_YMM6F1    =  349,
716     CV_REG_YMM6F2    =  350,
717     CV_REG_YMM6F3    =  351,
718     CV_REG_YMM6F4    =  352,
719     CV_REG_YMM6F5    =  353,
720     CV_REG_YMM6F6    =  354,
721     CV_REG_YMM6F7    =  355,
722     CV_REG_YMM7F0    =  356,
723     CV_REG_YMM7F1    =  357,
724     CV_REG_YMM7F2    =  358,
725     CV_REG_YMM7F3    =  359,
726     CV_REG_YMM7F4    =  360,
727     CV_REG_YMM7F5    =  361,
728     CV_REG_YMM7F6    =  362,
729     CV_REG_YMM7F7    =  363,
730     
731     CV_REG_YMM0D0     =    364,    // AVX floating-point double precise registers
732     CV_REG_YMM0D1     =    365,
733     CV_REG_YMM0D2     =    366,
734     CV_REG_YMM0D3     =    367,
735     CV_REG_YMM1D0     =    368,
736     CV_REG_YMM1D1     =    369,
737     CV_REG_YMM1D2     =    370,
738     CV_REG_YMM1D3     =    371,
739     CV_REG_YMM2D0     =    372,
740     CV_REG_YMM2D1     =    373,
741     CV_REG_YMM2D2     =    374,
742     CV_REG_YMM2D3     =    375,
743     CV_REG_YMM3D0     =    376,
744     CV_REG_YMM3D1     =    377,
745     CV_REG_YMM3D2     =    378,
746     CV_REG_YMM3D3     =    379,
747     CV_REG_YMM4D0     =    380,
748     CV_REG_YMM4D1     =    381,
749     CV_REG_YMM4D2     =    382,
750     CV_REG_YMM4D3     =    383,
751     CV_REG_YMM5D0     =    384,
752     CV_REG_YMM5D1     =    385,
753     CV_REG_YMM5D2     =    386,
754     CV_REG_YMM5D3     =    387,
755     CV_REG_YMM6D0     =    388,
756     CV_REG_YMM6D1     =    389,
757     CV_REG_YMM6D2     =    390,
758     CV_REG_YMM6D3     =    391,
759     CV_REG_YMM7D0     =    392,
760     CV_REG_YMM7D1     =    393,
761     CV_REG_YMM7D2     =    394,
762     CV_REG_YMM7D3     =    395,
763
764     CV_REG_BND0       =    396,
765     CV_REG_BND1       =    397,
766     CV_REG_BND2       =    398,
767     CV_REG_BND3       =    399,
768
769     // registers for the 68K processors
770
771     CV_R68_D0       =    0,
772     CV_R68_D1       =    1,
773     CV_R68_D2       =    2,
774     CV_R68_D3       =    3,
775     CV_R68_D4       =    4,
776     CV_R68_D5       =    5,
777     CV_R68_D6       =    6,
778     CV_R68_D7       =    7,
779     CV_R68_A0       =    8,
780     CV_R68_A1       =    9,
781     CV_R68_A2       =   10,
782     CV_R68_A3       =   11,
783     CV_R68_A4       =   12,
784     CV_R68_A5       =   13,
785     CV_R68_A6       =   14,
786     CV_R68_A7       =   15,
787     CV_R68_CCR      =   16,
788     CV_R68_SR       =   17,
789     CV_R68_USP      =   18,
790     CV_R68_MSP      =   19,
791     CV_R68_SFC      =   20,
792     CV_R68_DFC      =   21,
793     CV_R68_CACR     =   22,
794     CV_R68_VBR      =   23,
795     CV_R68_CAAR     =   24,
796     CV_R68_ISP      =   25,
797     CV_R68_PC       =   26,
798     //reserved  27
799     CV_R68_FPCR     =   28,
800     CV_R68_FPSR     =   29,
801     CV_R68_FPIAR    =   30,
802     //reserved  31
803     CV_R68_FP0      =   32,
804     CV_R68_FP1      =   33,
805     CV_R68_FP2      =   34,
806     CV_R68_FP3      =   35,
807     CV_R68_FP4      =   36,
808     CV_R68_FP5      =   37,
809     CV_R68_FP6      =   38,
810     CV_R68_FP7      =   39,
811     //reserved  40
812     CV_R68_MMUSR030 =   41,
813     CV_R68_MMUSR    =   42,
814     CV_R68_URP      =   43,
815     CV_R68_DTT0     =   44,
816     CV_R68_DTT1     =   45,
817     CV_R68_ITT0     =   46,
818     CV_R68_ITT1     =   47,
819     //reserved  50
820     CV_R68_PSR      =   51,
821     CV_R68_PCSR     =   52,
822     CV_R68_VAL      =   53,
823     CV_R68_CRP      =   54,
824     CV_R68_SRP      =   55,
825     CV_R68_DRP      =   56,
826     CV_R68_TC       =   57,
827     CV_R68_AC       =   58,
828     CV_R68_SCC      =   59,
829     CV_R68_CAL      =   60,
830     CV_R68_TT0      =   61,
831     CV_R68_TT1      =   62,
832     //reserved  63
833     CV_R68_BAD0     =   64,
834     CV_R68_BAD1     =   65,
835     CV_R68_BAD2     =   66,
836     CV_R68_BAD3     =   67,
837     CV_R68_BAD4     =   68,
838     CV_R68_BAD5     =   69,
839     CV_R68_BAD6     =   70,
840     CV_R68_BAD7     =   71,
841     CV_R68_BAC0     =   72,
842     CV_R68_BAC1     =   73,
843     CV_R68_BAC2     =   74,
844     CV_R68_BAC3     =   75,
845     CV_R68_BAC4     =   76,
846     CV_R68_BAC5     =   77,
847     CV_R68_BAC6     =   78,
848     CV_R68_BAC7     =   79,
849
850      // Register set for the MIPS 4000
851
852     CV_M4_NOREG     =   CV_REG_NONE,
853
854     CV_M4_IntZERO   =   10,      /* CPU REGISTER */
855     CV_M4_IntAT     =   11,
856     CV_M4_IntV0     =   12,
857     CV_M4_IntV1     =   13,
858     CV_M4_IntA0     =   14,
859     CV_M4_IntA1     =   15,
860     CV_M4_IntA2     =   16,
861     CV_M4_IntA3     =   17,
862     CV_M4_IntT0     =   18,
863     CV_M4_IntT1     =   19,
864     CV_M4_IntT2     =   20,
865     CV_M4_IntT3     =   21,
866     CV_M4_IntT4     =   22,
867     CV_M4_IntT5     =   23,
868     CV_M4_IntT6     =   24,
869     CV_M4_IntT7     =   25,
870     CV_M4_IntS0     =   26,
871     CV_M4_IntS1     =   27,
872     CV_M4_IntS2     =   28,
873     CV_M4_IntS3     =   29,
874     CV_M4_IntS4     =   30,
875     CV_M4_IntS5     =   31,
876     CV_M4_IntS6     =   32,
877     CV_M4_IntS7     =   33,
878     CV_M4_IntT8     =   34,
879     CV_M4_IntT9     =   35,
880     CV_M4_IntKT0    =   36,
881     CV_M4_IntKT1    =   37,
882     CV_M4_IntGP     =   38,
883     CV_M4_IntSP     =   39,
884     CV_M4_IntS8     =   40,
885     CV_M4_IntRA     =   41,
886     CV_M4_IntLO     =   42,
887     CV_M4_IntHI     =   43,
888
889     CV_M4_Fir       =   50,
890     CV_M4_Psr       =   51,
891
892     CV_M4_FltF0     =   60,      /* Floating point registers */
893     CV_M4_FltF1     =   61,
894     CV_M4_FltF2     =   62,
895     CV_M4_FltF3     =   63,
896     CV_M4_FltF4     =   64,
897     CV_M4_FltF5     =   65,
898     CV_M4_FltF6     =   66,
899     CV_M4_FltF7     =   67,
900     CV_M4_FltF8     =   68,
901     CV_M4_FltF9     =   69,
902     CV_M4_FltF10    =   70,
903     CV_M4_FltF11    =   71,
904     CV_M4_FltF12    =   72,
905     CV_M4_FltF13    =   73,
906     CV_M4_FltF14    =   74,
907     CV_M4_FltF15    =   75,
908     CV_M4_FltF16    =   76,
909     CV_M4_FltF17    =   77,
910     CV_M4_FltF18    =   78,
911     CV_M4_FltF19    =   79,
912     CV_M4_FltF20    =   80,
913     CV_M4_FltF21    =   81,
914     CV_M4_FltF22    =   82,
915     CV_M4_FltF23    =   83,
916     CV_M4_FltF24    =   84,
917     CV_M4_FltF25    =   85,
918     CV_M4_FltF26    =   86,
919     CV_M4_FltF27    =   87,
920     CV_M4_FltF28    =   88,
921     CV_M4_FltF29    =   89,
922     CV_M4_FltF30    =   90,
923     CV_M4_FltF31    =   91,
924     CV_M4_FltFsr    =   92,
925
926
927     // Register set for the ALPHA AXP
928
929     CV_ALPHA_NOREG  = CV_REG_NONE,
930
931     CV_ALPHA_FltF0  =   10,   // Floating point registers
932     CV_ALPHA_FltF1  =   11,
933     CV_ALPHA_FltF2  =   12,
934     CV_ALPHA_FltF3  =   13,
935     CV_ALPHA_FltF4  =   14,
936     CV_ALPHA_FltF5  =   15,
937     CV_ALPHA_FltF6  =   16,
938     CV_ALPHA_FltF7  =   17,
939     CV_ALPHA_FltF8  =   18,
940     CV_ALPHA_FltF9  =   19,
941     CV_ALPHA_FltF10 =   20,
942     CV_ALPHA_FltF11 =   21,
943     CV_ALPHA_FltF12 =   22,
944     CV_ALPHA_FltF13 =   23,
945     CV_ALPHA_FltF14 =   24,
946     CV_ALPHA_FltF15 =   25,
947     CV_ALPHA_FltF16 =   26,
948     CV_ALPHA_FltF17 =   27,
949     CV_ALPHA_FltF18 =   28,
950     CV_ALPHA_FltF19 =   29,
951     CV_ALPHA_FltF20 =   30,
952     CV_ALPHA_FltF21 =   31,
953     CV_ALPHA_FltF22 =   32,
954     CV_ALPHA_FltF23 =   33,
955     CV_ALPHA_FltF24 =   34,
956     CV_ALPHA_FltF25 =   35,
957     CV_ALPHA_FltF26 =   36,
958     CV_ALPHA_FltF27 =   37,
959     CV_ALPHA_FltF28 =   38,
960     CV_ALPHA_FltF29 =   39,
961     CV_ALPHA_FltF30 =   40,
962     CV_ALPHA_FltF31 =   41,
963
964     CV_ALPHA_IntV0  =   42,   // Integer registers
965     CV_ALPHA_IntT0  =   43,
966     CV_ALPHA_IntT1  =   44,
967     CV_ALPHA_IntT2  =   45,
968     CV_ALPHA_IntT3  =   46,
969     CV_ALPHA_IntT4  =   47,
970     CV_ALPHA_IntT5  =   48,
971     CV_ALPHA_IntT6  =   49,
972     CV_ALPHA_IntT7  =   50,
973     CV_ALPHA_IntS0  =   51,
974     CV_ALPHA_IntS1  =   52,
975     CV_ALPHA_IntS2  =   53,
976     CV_ALPHA_IntS3  =   54,
977     CV_ALPHA_IntS4  =   55,
978     CV_ALPHA_IntS5  =   56,
979     CV_ALPHA_IntFP  =   57,
980     CV_ALPHA_IntA0  =   58,
981     CV_ALPHA_IntA1  =   59,
982     CV_ALPHA_IntA2  =   60,
983     CV_ALPHA_IntA3  =   61,
984     CV_ALPHA_IntA4  =   62,
985     CV_ALPHA_IntA5  =   63,
986     CV_ALPHA_IntT8  =   64,
987     CV_ALPHA_IntT9  =   65,
988     CV_ALPHA_IntT10 =   66,
989     CV_ALPHA_IntT11 =   67,
990     CV_ALPHA_IntRA  =   68,
991     CV_ALPHA_IntT12 =   69,
992     CV_ALPHA_IntAT  =   70,
993     CV_ALPHA_IntGP  =   71,
994     CV_ALPHA_IntSP  =   72,
995     CV_ALPHA_IntZERO =  73,
996
997
998     CV_ALPHA_Fpcr   =   74,   // Control registers
999     CV_ALPHA_Fir    =   75,
1000     CV_ALPHA_Psr    =   76,
1001     CV_ALPHA_FltFsr =   77,
1002     CV_ALPHA_SoftFpcr =   78,
1003
1004     // Register Set for Motorola/IBM PowerPC
1005
1006     /*
1007     ** PowerPC General Registers ( User Level )
1008     */
1009     CV_PPC_GPR0     =  1,
1010     CV_PPC_GPR1     =  2,
1011     CV_PPC_GPR2     =  3,
1012     CV_PPC_GPR3     =  4,
1013     CV_PPC_GPR4     =  5,
1014     CV_PPC_GPR5     =  6,
1015     CV_PPC_GPR6     =  7,
1016     CV_PPC_GPR7     =  8,
1017     CV_PPC_GPR8     =  9,
1018     CV_PPC_GPR9     = 10,
1019     CV_PPC_GPR10    = 11,
1020     CV_PPC_GPR11    = 12,
1021     CV_PPC_GPR12    = 13,
1022     CV_PPC_GPR13    = 14,
1023     CV_PPC_GPR14    = 15,
1024     CV_PPC_GPR15    = 16,
1025     CV_PPC_GPR16    = 17,
1026     CV_PPC_GPR17    = 18,
1027     CV_PPC_GPR18    = 19,
1028     CV_PPC_GPR19    = 20,
1029     CV_PPC_GPR20    = 21,
1030     CV_PPC_GPR21    = 22,
1031     CV_PPC_GPR22    = 23,
1032     CV_PPC_GPR23    = 24,
1033     CV_PPC_GPR24    = 25,
1034     CV_PPC_GPR25    = 26,
1035     CV_PPC_GPR26    = 27,
1036     CV_PPC_GPR27    = 28,
1037     CV_PPC_GPR28    = 29,
1038     CV_PPC_GPR29    = 30,
1039     CV_PPC_GPR30    = 31,
1040     CV_PPC_GPR31    = 32,
1041
1042     /*
1043     ** PowerPC Condition Register ( User Level )
1044     */
1045     CV_PPC_CR       = 33,
1046     CV_PPC_CR0      = 34,
1047     CV_PPC_CR1      = 35,
1048     CV_PPC_CR2      = 36,
1049     CV_PPC_CR3      = 37,
1050     CV_PPC_CR4      = 38,
1051     CV_PPC_CR5      = 39,
1052     CV_PPC_CR6      = 40,
1053     CV_PPC_CR7      = 41,
1054
1055     /*
1056     ** PowerPC Floating Point Registers ( User Level )
1057     */
1058     CV_PPC_FPR0     = 42,
1059     CV_PPC_FPR1     = 43,
1060     CV_PPC_FPR2     = 44,
1061     CV_PPC_FPR3     = 45,
1062     CV_PPC_FPR4     = 46,
1063     CV_PPC_FPR5     = 47,
1064     CV_PPC_FPR6     = 48,
1065     CV_PPC_FPR7     = 49,
1066     CV_PPC_FPR8     = 50,
1067     CV_PPC_FPR9     = 51,
1068     CV_PPC_FPR10    = 52,
1069     CV_PPC_FPR11    = 53,
1070     CV_PPC_FPR12    = 54,
1071     CV_PPC_FPR13    = 55,
1072     CV_PPC_FPR14    = 56,
1073     CV_PPC_FPR15    = 57,
1074     CV_PPC_FPR16    = 58,
1075     CV_PPC_FPR17    = 59,
1076     CV_PPC_FPR18    = 60,
1077     CV_PPC_FPR19    = 61,
1078     CV_PPC_FPR20    = 62,
1079     CV_PPC_FPR21    = 63,
1080     CV_PPC_FPR22    = 64,
1081     CV_PPC_FPR23    = 65,
1082     CV_PPC_FPR24    = 66,
1083     CV_PPC_FPR25    = 67,
1084     CV_PPC_FPR26    = 68,
1085     CV_PPC_FPR27    = 69,
1086     CV_PPC_FPR28    = 70,
1087     CV_PPC_FPR29    = 71,
1088     CV_PPC_FPR30    = 72,
1089     CV_PPC_FPR31    = 73,
1090
1091     /*
1092     ** PowerPC Floating Point Status and Control Register ( User Level )
1093     */
1094     CV_PPC_FPSCR    = 74,
1095
1096     /*
1097     ** PowerPC Machine State Register ( Supervisor Level )
1098     */
1099     CV_PPC_MSR      = 75,
1100
1101     /*
1102     ** PowerPC Segment Registers ( Supervisor Level )
1103     */
1104     CV_PPC_SR0      = 76,
1105     CV_PPC_SR1      = 77,
1106     CV_PPC_SR2      = 78,
1107     CV_PPC_SR3      = 79,
1108     CV_PPC_SR4      = 80,
1109     CV_PPC_SR5      = 81,
1110     CV_PPC_SR6      = 82,
1111     CV_PPC_SR7      = 83,
1112     CV_PPC_SR8      = 84,
1113     CV_PPC_SR9      = 85,
1114     CV_PPC_SR10     = 86,
1115     CV_PPC_SR11     = 87,
1116     CV_PPC_SR12     = 88,
1117     CV_PPC_SR13     = 89,
1118     CV_PPC_SR14     = 90,
1119     CV_PPC_SR15     = 91,
1120
1121     /*
1122     ** For all of the special purpose registers add 100 to the SPR# that the
1123     ** Motorola/IBM documentation gives with the exception of any imaginary
1124     ** registers.
1125     */
1126
1127     /*
1128     ** PowerPC Special Purpose Registers ( User Level )
1129     */
1130     CV_PPC_PC       = 99,     // PC (imaginary register)
1131
1132     CV_PPC_MQ       = 100,    // MPC601
1133     CV_PPC_XER      = 101,
1134     CV_PPC_RTCU     = 104,    // MPC601
1135     CV_PPC_RTCL     = 105,    // MPC601
1136     CV_PPC_LR       = 108,
1137     CV_PPC_CTR      = 109,
1138
1139     CV_PPC_COMPARE  = 110,    // part of XER (internal to the debugger only)
1140     CV_PPC_COUNT    = 111,    // part of XER (internal to the debugger only)
1141
1142     /*
1143     ** PowerPC Special Purpose Registers ( Supervisor Level )
1144     */
1145     CV_PPC_DSISR    = 118,
1146     CV_PPC_DAR      = 119,
1147     CV_PPC_DEC      = 122,
1148     CV_PPC_SDR1     = 125,
1149     CV_PPC_SRR0     = 126,
1150     CV_PPC_SRR1     = 127,
1151     CV_PPC_SPRG0    = 372,
1152     CV_PPC_SPRG1    = 373,
1153     CV_PPC_SPRG2    = 374,
1154     CV_PPC_SPRG3    = 375,
1155     CV_PPC_ASR      = 280,    // 64-bit implementations only
1156     CV_PPC_EAR      = 382,
1157     CV_PPC_PVR      = 287,
1158     CV_PPC_BAT0U    = 628,
1159     CV_PPC_BAT0L    = 629,
1160     CV_PPC_BAT1U    = 630,
1161     CV_PPC_BAT1L    = 631,
1162     CV_PPC_BAT2U    = 632,
1163     CV_PPC_BAT2L    = 633,
1164     CV_PPC_BAT3U    = 634,
1165     CV_PPC_BAT3L    = 635,
1166     CV_PPC_DBAT0U   = 636,
1167     CV_PPC_DBAT0L   = 637,
1168     CV_PPC_DBAT1U   = 638,
1169     CV_PPC_DBAT1L   = 639,
1170     CV_PPC_DBAT2U   = 640,
1171     CV_PPC_DBAT2L   = 641,
1172     CV_PPC_DBAT3U   = 642,
1173     CV_PPC_DBAT3L   = 643,
1174
1175     /*
1176     ** PowerPC Special Purpose Registers Implementation Dependent ( Supervisor Level )
1177     */
1178
1179     /*
1180     ** Doesn't appear that IBM/Motorola has finished defining these.
1181     */
1182
1183     CV_PPC_PMR0     = 1044,   // MPC620,
1184     CV_PPC_PMR1     = 1045,   // MPC620,
1185     CV_PPC_PMR2     = 1046,   // MPC620,
1186     CV_PPC_PMR3     = 1047,   // MPC620,
1187     CV_PPC_PMR4     = 1048,   // MPC620,
1188     CV_PPC_PMR5     = 1049,   // MPC620,
1189     CV_PPC_PMR6     = 1050,   // MPC620,
1190     CV_PPC_PMR7     = 1051,   // MPC620,
1191     CV_PPC_PMR8     = 1052,   // MPC620,
1192     CV_PPC_PMR9     = 1053,   // MPC620,
1193     CV_PPC_PMR10    = 1054,   // MPC620,
1194     CV_PPC_PMR11    = 1055,   // MPC620,
1195     CV_PPC_PMR12    = 1056,   // MPC620,
1196     CV_PPC_PMR13    = 1057,   // MPC620,
1197     CV_PPC_PMR14    = 1058,   // MPC620,
1198     CV_PPC_PMR15    = 1059,   // MPC620,
1199
1200     CV_PPC_DMISS    = 1076,   // MPC603
1201     CV_PPC_DCMP     = 1077,   // MPC603
1202     CV_PPC_HASH1    = 1078,   // MPC603
1203     CV_PPC_HASH2    = 1079,   // MPC603
1204     CV_PPC_IMISS    = 1080,   // MPC603
1205     CV_PPC_ICMP     = 1081,   // MPC603
1206     CV_PPC_RPA      = 1082,   // MPC603
1207
1208     CV_PPC_HID0     = 1108,   // MPC601, MPC603, MPC620
1209     CV_PPC_HID1     = 1109,   // MPC601
1210     CV_PPC_HID2     = 1110,   // MPC601, MPC603, MPC620 ( IABR )
1211     CV_PPC_HID3     = 1111,   // Not Defined
1212     CV_PPC_HID4     = 1112,   // Not Defined
1213     CV_PPC_HID5     = 1113,   // MPC601, MPC604, MPC620 ( DABR )
1214     CV_PPC_HID6     = 1114,   // Not Defined
1215     CV_PPC_HID7     = 1115,   // Not Defined
1216     CV_PPC_HID8     = 1116,   // MPC620 ( BUSCSR )
1217     CV_PPC_HID9     = 1117,   // MPC620 ( L2CSR )
1218     CV_PPC_HID10    = 1118,   // Not Defined
1219     CV_PPC_HID11    = 1119,   // Not Defined
1220     CV_PPC_HID12    = 1120,   // Not Defined
1221     CV_PPC_HID13    = 1121,   // MPC604 ( HCR )
1222     CV_PPC_HID14    = 1122,   // Not Defined
1223     CV_PPC_HID15    = 1123,   // MPC601, MPC604, MPC620 ( PIR )
1224
1225     //
1226     // JAVA VM registers
1227     //
1228
1229     CV_JAVA_PC      = 1,
1230
1231     //
1232     // Register set for the Hitachi SH3
1233     //
1234
1235     CV_SH3_NOREG    =   CV_REG_NONE,
1236
1237     CV_SH3_IntR0    =   10,   // CPU REGISTER
1238     CV_SH3_IntR1    =   11,
1239     CV_SH3_IntR2    =   12,
1240     CV_SH3_IntR3    =   13,
1241     CV_SH3_IntR4    =   14,
1242     CV_SH3_IntR5    =   15,
1243     CV_SH3_IntR6    =   16,
1244     CV_SH3_IntR7    =   17,
1245     CV_SH3_IntR8    =   18,
1246     CV_SH3_IntR9    =   19,
1247     CV_SH3_IntR10   =   20,
1248     CV_SH3_IntR11   =   21,
1249     CV_SH3_IntR12   =   22,
1250     CV_SH3_IntR13   =   23,
1251     CV_SH3_IntFp    =   24,
1252     CV_SH3_IntSp    =   25,
1253     CV_SH3_Gbr      =   38,
1254     CV_SH3_Pr       =   39,
1255     CV_SH3_Mach     =   40,
1256     CV_SH3_Macl     =   41,
1257
1258     CV_SH3_Pc       =   50,
1259     CV_SH3_Sr       =   51,
1260
1261     CV_SH3_BarA     =   60,
1262     CV_SH3_BasrA    =   61,
1263     CV_SH3_BamrA    =   62,
1264     CV_SH3_BbrA     =   63,
1265     CV_SH3_BarB     =   64,
1266     CV_SH3_BasrB    =   65,
1267     CV_SH3_BamrB    =   66,
1268     CV_SH3_BbrB     =   67,
1269     CV_SH3_BdrB     =   68,
1270     CV_SH3_BdmrB    =   69,
1271     CV_SH3_Brcr     =   70,
1272
1273     //
1274     // Additional registers for Hitachi SH processors
1275     //
1276
1277     CV_SH_Fpscr    =   75,    // floating point status/control register
1278     CV_SH_Fpul     =   76,    // floating point communication register
1279
1280     CV_SH_FpR0     =   80,    // Floating point registers
1281     CV_SH_FpR1     =   81,
1282     CV_SH_FpR2     =   82,
1283     CV_SH_FpR3     =   83,
1284     CV_SH_FpR4     =   84,
1285     CV_SH_FpR5     =   85,
1286     CV_SH_FpR6     =   86,
1287     CV_SH_FpR7     =   87,
1288     CV_SH_FpR8     =   88,
1289     CV_SH_FpR9     =   89,
1290     CV_SH_FpR10    =   90,
1291     CV_SH_FpR11    =   91,
1292     CV_SH_FpR12    =   92,
1293     CV_SH_FpR13    =   93,
1294     CV_SH_FpR14    =   94,
1295     CV_SH_FpR15    =   95,
1296
1297     CV_SH_XFpR0    =   96,
1298     CV_SH_XFpR1    =   97,
1299     CV_SH_XFpR2    =   98,
1300     CV_SH_XFpR3    =   99,
1301     CV_SH_XFpR4    =  100,
1302     CV_SH_XFpR5    =  101,
1303     CV_SH_XFpR6    =  102,
1304     CV_SH_XFpR7    =  103,
1305     CV_SH_XFpR8    =  104,
1306     CV_SH_XFpR9    =  105,
1307     CV_SH_XFpR10   =  106,
1308     CV_SH_XFpR11   =  107,
1309     CV_SH_XFpR12   =  108,
1310     CV_SH_XFpR13   =  109,
1311     CV_SH_XFpR14   =  110,
1312     CV_SH_XFpR15   =  111,
1313
1314     //
1315     // Register set for the ARM processor.
1316     //
1317
1318     CV_ARM_NOREG    =   CV_REG_NONE,
1319
1320     CV_ARM_R0       =   10,
1321     CV_ARM_R1       =   11,
1322     CV_ARM_R2       =   12,
1323     CV_ARM_R3       =   13,
1324     CV_ARM_R4       =   14,
1325     CV_ARM_R5       =   15,
1326     CV_ARM_R6       =   16,
1327     CV_ARM_R7       =   17,
1328     CV_ARM_R8       =   18,
1329     CV_ARM_R9       =   19,
1330     CV_ARM_R10      =   20,
1331     CV_ARM_R11      =   21, // Frame pointer, if allocated
1332     CV_ARM_R12      =   22,
1333     CV_ARM_SP       =   23, // Stack pointer
1334     CV_ARM_LR       =   24, // Link Register
1335     CV_ARM_PC       =   25, // Program counter
1336     CV_ARM_CPSR     =   26, // Current program status register
1337
1338     CV_ARM_ACC0     =   27, // DSP co-processor 0 40 bit accumulator
1339
1340     //
1341     // Registers for ARM VFP10 support
1342     //
1343     
1344     CV_ARM_FPSCR    =   40,
1345     CV_ARM_FPEXC    =   41,
1346     
1347     CV_ARM_FS0      =   50,
1348     CV_ARM_FS1      =   51,
1349     CV_ARM_FS2      =   52,
1350     CV_ARM_FS3      =   53,
1351     CV_ARM_FS4      =   54,
1352     CV_ARM_FS5      =   55,
1353     CV_ARM_FS6      =   56,
1354     CV_ARM_FS7      =   57,
1355     CV_ARM_FS8      =   58,
1356     CV_ARM_FS9      =   59,
1357     CV_ARM_FS10     =   60,
1358     CV_ARM_FS11     =   61,
1359     CV_ARM_FS12     =   62,
1360     CV_ARM_FS13     =   63,
1361     CV_ARM_FS14     =   64,
1362     CV_ARM_FS15     =   65,
1363     CV_ARM_FS16     =   66,
1364     CV_ARM_FS17     =   67,
1365     CV_ARM_FS18     =   68,
1366     CV_ARM_FS19     =   69,
1367     CV_ARM_FS20     =   70,
1368     CV_ARM_FS21     =   71,
1369     CV_ARM_FS22     =   72,
1370     CV_ARM_FS23     =   73,
1371     CV_ARM_FS24     =   74,
1372     CV_ARM_FS25     =   75,
1373     CV_ARM_FS26     =   76,
1374     CV_ARM_FS27     =   77,
1375     CV_ARM_FS28     =   78,
1376     CV_ARM_FS29     =   79,
1377     CV_ARM_FS30     =   80,
1378     CV_ARM_FS31     =   81,
1379
1380     //
1381     // ARM VFP Floating Point Extra control registers
1382     //
1383     
1384     CV_ARM_FPEXTRA0 =   90,
1385     CV_ARM_FPEXTRA1 =   91,
1386     CV_ARM_FPEXTRA2 =   92,
1387     CV_ARM_FPEXTRA3 =   93,
1388     CV_ARM_FPEXTRA4 =   94,
1389     CV_ARM_FPEXTRA5 =   95,
1390     CV_ARM_FPEXTRA6 =   96,
1391     CV_ARM_FPEXTRA7 =   97,
1392
1393     // XSCALE Concan co-processor registers
1394     CV_ARM_WR0      =   128, 
1395     CV_ARM_WR1      =   129, 
1396     CV_ARM_WR2      =   130, 
1397     CV_ARM_WR3      =   131, 
1398     CV_ARM_WR4      =   132, 
1399     CV_ARM_WR5      =   133, 
1400     CV_ARM_WR6      =   134, 
1401     CV_ARM_WR7      =   135, 
1402     CV_ARM_WR8      =   136, 
1403     CV_ARM_WR9      =   137, 
1404     CV_ARM_WR10     =   138, 
1405     CV_ARM_WR11     =   139, 
1406     CV_ARM_WR12     =   140, 
1407     CV_ARM_WR13     =   141, 
1408     CV_ARM_WR14     =   142, 
1409     CV_ARM_WR15     =   143, 
1410     
1411     // XSCALE Concan co-processor control registers
1412     CV_ARM_WCID     =   144,
1413     CV_ARM_WCON     =   145,
1414     CV_ARM_WCSSF    =   146,
1415     CV_ARM_WCASF    =   147,
1416     CV_ARM_WC4      =   148,
1417     CV_ARM_WC5      =   149,
1418     CV_ARM_WC6      =   150,
1419     CV_ARM_WC7      =   151,
1420     CV_ARM_WCGR0    =   152,
1421     CV_ARM_WCGR1    =   153,
1422     CV_ARM_WCGR2    =   154,
1423     CV_ARM_WCGR3    =   155,
1424     CV_ARM_WC12     =   156,
1425     CV_ARM_WC13     =   157,
1426     CV_ARM_WC14     =   158,
1427     CV_ARM_WC15     =   159,
1428
1429     //
1430     // ARM VFPv3/Neon extended floating Point
1431     //
1432     
1433     CV_ARM_FS32     =   200,
1434     CV_ARM_FS33     =   201,
1435     CV_ARM_FS34     =   202,
1436     CV_ARM_FS35     =   203,
1437     CV_ARM_FS36     =   204,
1438     CV_ARM_FS37     =   205,
1439     CV_ARM_FS38     =   206,
1440     CV_ARM_FS39     =   207,
1441     CV_ARM_FS40     =   208,
1442     CV_ARM_FS41     =   209,
1443     CV_ARM_FS42     =   210,
1444     CV_ARM_FS43     =   211,
1445     CV_ARM_FS44     =   212,
1446     CV_ARM_FS45     =   213,
1447     CV_ARM_FS46     =   214,
1448     CV_ARM_FS47     =   215,
1449     CV_ARM_FS48     =   216,
1450     CV_ARM_FS49     =   217,
1451     CV_ARM_FS50     =   218,
1452     CV_ARM_FS51     =   219,
1453     CV_ARM_FS52     =   220,
1454     CV_ARM_FS53     =   221,
1455     CV_ARM_FS54     =   222,
1456     CV_ARM_FS55     =   223,
1457     CV_ARM_FS56     =   224,
1458     CV_ARM_FS57     =   225,
1459     CV_ARM_FS58     =   226,
1460     CV_ARM_FS59     =   227,
1461     CV_ARM_FS60     =   228,
1462     CV_ARM_FS61     =   229,
1463     CV_ARM_FS62     =   230,
1464     CV_ARM_FS63     =   231,
1465
1466     // ARM double-precision floating point
1467
1468     CV_ARM_ND0 = 300, 
1469     CV_ARM_ND1 = 301, 
1470     CV_ARM_ND2 = 302, 
1471     CV_ARM_ND3 = 303, 
1472     CV_ARM_ND4 = 304, 
1473     CV_ARM_ND5 = 305,
1474     CV_ARM_ND6 = 306, 
1475     CV_ARM_ND7 = 307, 
1476     CV_ARM_ND8 = 308, 
1477     CV_ARM_ND9 = 309, 
1478     CV_ARM_ND10 = 310, 
1479     CV_ARM_ND11 = 311,
1480     CV_ARM_ND12 = 312, 
1481     CV_ARM_ND13 = 313, 
1482     CV_ARM_ND14 = 314, 
1483     CV_ARM_ND15 = 315, 
1484     CV_ARM_ND16 = 316,
1485     CV_ARM_ND17 = 317, 
1486     CV_ARM_ND18 = 318, 
1487     CV_ARM_ND19 = 319, 
1488     CV_ARM_ND20 = 320, 
1489     CV_ARM_ND21 = 321,
1490     CV_ARM_ND22 = 322, 
1491     CV_ARM_ND23 = 323, 
1492     CV_ARM_ND24 = 324, 
1493     CV_ARM_ND25 = 325, 
1494     CV_ARM_ND26 = 326,
1495     CV_ARM_ND27 = 327, 
1496     CV_ARM_ND28 = 328, 
1497     CV_ARM_ND29 = 329, 
1498     CV_ARM_ND30 = 330, 
1499     CV_ARM_ND31 = 331,
1500
1501     // ARM extended precision floating point
1502
1503     CV_ARM_NQ0 = 400, 
1504     CV_ARM_NQ1 = 401, 
1505     CV_ARM_NQ2 = 402, 
1506     CV_ARM_NQ3 = 403, 
1507     CV_ARM_NQ4 = 404, 
1508     CV_ARM_NQ5 = 405,
1509     CV_ARM_NQ6 = 406, 
1510     CV_ARM_NQ7 = 407, 
1511     CV_ARM_NQ8 = 408, 
1512     CV_ARM_NQ9 = 409, 
1513     CV_ARM_NQ10 = 410, 
1514     CV_ARM_NQ11 = 411,
1515     CV_ARM_NQ12 = 412, 
1516     CV_ARM_NQ13 = 413, 
1517     CV_ARM_NQ14 = 414, 
1518     CV_ARM_NQ15 = 415, 
1519
1520     //
1521     // Register set for ARM64
1522     //
1523
1524     CV_ARM64_NOREG  =  CV_REG_NONE,
1525
1526     // General purpose 32-bit integer registers
1527
1528     CV_ARM64_W0     =  10,
1529     CV_ARM64_W1     =  11,
1530     CV_ARM64_W2     =  12,
1531     CV_ARM64_W3     =  13,
1532     CV_ARM64_W4     =  14,
1533     CV_ARM64_W5     =  15,
1534     CV_ARM64_W6     =  16,
1535     CV_ARM64_W7     =  17,
1536     CV_ARM64_W8     =  18,
1537     CV_ARM64_W9     =  19,
1538     CV_ARM64_W10    =  20,
1539     CV_ARM64_W11    =  21,
1540     CV_ARM64_W12    =  22,
1541     CV_ARM64_W13    =  23,
1542     CV_ARM64_W14    =  24,
1543     CV_ARM64_W15    =  25,
1544     CV_ARM64_W16    =  26,
1545     CV_ARM64_W17    =  27,
1546     CV_ARM64_W18    =  28,
1547     CV_ARM64_W19    =  29,
1548     CV_ARM64_W20    =  30,
1549     CV_ARM64_W21    =  31,
1550     CV_ARM64_W22    =  32,
1551     CV_ARM64_W23    =  33,
1552     CV_ARM64_W24    =  34,
1553     CV_ARM64_W25    =  35,
1554     CV_ARM64_W26    =  36,
1555     CV_ARM64_W27    =  37,
1556     CV_ARM64_W28    =  38,
1557     CV_ARM64_W29    =  39,
1558     CV_ARM64_W30    =  40,
1559     CV_ARM64_WZR    =  41,
1560
1561     // General purpose 64-bit integer registers
1562
1563     CV_ARM64_X0     =  50,
1564     CV_ARM64_X1     =  51,
1565     CV_ARM64_X2     =  52,
1566     CV_ARM64_X3     =  53,
1567     CV_ARM64_X4     =  54,
1568     CV_ARM64_X5     =  55,
1569     CV_ARM64_X6     =  56,
1570     CV_ARM64_X7     =  57,
1571     CV_ARM64_X8     =  58,
1572     CV_ARM64_X9     =  59,
1573     CV_ARM64_X10    =  60,
1574     CV_ARM64_X11    =  61,
1575     CV_ARM64_X12    =  62,
1576     CV_ARM64_X13    =  63,
1577     CV_ARM64_X14    =  64,
1578     CV_ARM64_X15    =  65,
1579     CV_ARM64_IP0    =  66,
1580     CV_ARM64_IP1    =  67,
1581     CV_ARM64_X18    =  68,
1582     CV_ARM64_X19    =  69,
1583     CV_ARM64_X20    =  70,
1584     CV_ARM64_X21    =  71,
1585     CV_ARM64_X22    =  72,
1586     CV_ARM64_X23    =  73,
1587     CV_ARM64_X24    =  74,
1588     CV_ARM64_X25    =  75,
1589     CV_ARM64_X26    =  76,
1590     CV_ARM64_X27    =  77,
1591     CV_ARM64_X28    =  78,
1592     CV_ARM64_FP     =  79,
1593     CV_ARM64_LR     =  80,
1594     CV_ARM64_SP     =  81,
1595     CV_ARM64_ZR     =  82,
1596
1597     // statue register
1598
1599     CV_ARM64_NZCV   =  90,
1600
1601     // 32-bit floating point registers
1602
1603     CV_ARM64_S0     =  100,
1604     CV_ARM64_S1     =  101,
1605     CV_ARM64_S2     =  102,
1606     CV_ARM64_S3     =  103,
1607     CV_ARM64_S4     =  104,
1608     CV_ARM64_S5     =  105,
1609     CV_ARM64_S6     =  106,
1610     CV_ARM64_S7     =  107,
1611     CV_ARM64_S8     =  108,
1612     CV_ARM64_S9     =  109,
1613     CV_ARM64_S10    =  110,
1614     CV_ARM64_S11    =  111,
1615     CV_ARM64_S12    =  112,
1616     CV_ARM64_S13    =  113,
1617     CV_ARM64_S14    =  114,
1618     CV_ARM64_S15    =  115,
1619     CV_ARM64_S16    =  116,
1620     CV_ARM64_S17    =  117,
1621     CV_ARM64_S18    =  118,
1622     CV_ARM64_S19    =  119,
1623     CV_ARM64_S20    =  120,
1624     CV_ARM64_S21    =  121,
1625     CV_ARM64_S22    =  122,
1626     CV_ARM64_S23    =  123,
1627     CV_ARM64_S24    =  124,
1628     CV_ARM64_S25    =  125,
1629     CV_ARM64_S26    =  126,
1630     CV_ARM64_S27    =  127,
1631     CV_ARM64_S28    =  128,
1632     CV_ARM64_S29    =  129,
1633     CV_ARM64_S30    =  130,
1634     CV_ARM64_S31    =  131,
1635
1636     // 64-bit floating point registers
1637
1638     CV_ARM64_D0     =  140,
1639     CV_ARM64_D1     =  141,
1640     CV_ARM64_D2     =  142,
1641     CV_ARM64_D3     =  143,
1642     CV_ARM64_D4     =  144,
1643     CV_ARM64_D5     =  145,
1644     CV_ARM64_D6     =  146,
1645     CV_ARM64_D7     =  147,
1646     CV_ARM64_D8     =  148,
1647     CV_ARM64_D9     =  149,
1648     CV_ARM64_D10    =  150,
1649     CV_ARM64_D11    =  151,
1650     CV_ARM64_D12    =  152,
1651     CV_ARM64_D13    =  153,
1652     CV_ARM64_D14    =  154,
1653     CV_ARM64_D15    =  155,
1654     CV_ARM64_D16    =  156,
1655     CV_ARM64_D17    =  157,
1656     CV_ARM64_D18    =  158,
1657     CV_ARM64_D19    =  159,
1658     CV_ARM64_D20    =  160,
1659     CV_ARM64_D21    =  161,
1660     CV_ARM64_D22    =  162,
1661     CV_ARM64_D23    =  163,
1662     CV_ARM64_D24    =  164,
1663     CV_ARM64_D25    =  165,
1664     CV_ARM64_D26    =  166,
1665     CV_ARM64_D27    =  167,
1666     CV_ARM64_D28    =  168,
1667     CV_ARM64_D29    =  169,
1668     CV_ARM64_D30    =  170,
1669     CV_ARM64_D31    =  171,
1670
1671     // 128-bit SIMD registers
1672
1673     CV_ARM64_Q0     =  180,
1674     CV_ARM64_Q1     =  181,
1675     CV_ARM64_Q2     =  182,
1676     CV_ARM64_Q3     =  183,
1677     CV_ARM64_Q4     =  184,
1678     CV_ARM64_Q5     =  185,
1679     CV_ARM64_Q6     =  186,
1680     CV_ARM64_Q7     =  187,
1681     CV_ARM64_Q8     =  188,
1682     CV_ARM64_Q9     =  189,
1683     CV_ARM64_Q10    =  190,
1684     CV_ARM64_Q11    =  191,
1685     CV_ARM64_Q12    =  192,
1686     CV_ARM64_Q13    =  193,
1687     CV_ARM64_Q14    =  194,
1688     CV_ARM64_Q15    =  195,
1689     CV_ARM64_Q16    =  196,
1690     CV_ARM64_Q17    =  197,
1691     CV_ARM64_Q18    =  198,
1692     CV_ARM64_Q19    =  199,
1693     CV_ARM64_Q20    =  200,
1694     CV_ARM64_Q21    =  201,
1695     CV_ARM64_Q22    =  202,
1696     CV_ARM64_Q23    =  203,
1697     CV_ARM64_Q24    =  204,
1698     CV_ARM64_Q25    =  205,
1699     CV_ARM64_Q26    =  206,
1700     CV_ARM64_Q27    =  207,
1701     CV_ARM64_Q28    =  208,
1702     CV_ARM64_Q29    =  209,
1703     CV_ARM64_Q30    =  210,
1704     CV_ARM64_Q31    =  211,
1705
1706     // Floating point status register
1707
1708     CV_ARM64_FPSR   =  220,
1709     
1710     //
1711     // Register set for Intel IA64
1712     //
1713
1714     CV_IA64_NOREG   =   CV_REG_NONE,
1715
1716     // Branch Registers
1717
1718     CV_IA64_Br0     =   512,
1719     CV_IA64_Br1     =   513,
1720     CV_IA64_Br2     =   514,
1721     CV_IA64_Br3     =   515,
1722     CV_IA64_Br4     =   516,
1723     CV_IA64_Br5     =   517,
1724     CV_IA64_Br6     =   518,
1725     CV_IA64_Br7     =   519,
1726
1727     // Predicate Registers
1728
1729     CV_IA64_P0    =   704,
1730     CV_IA64_P1    =   705,
1731     CV_IA64_P2    =   706,
1732     CV_IA64_P3    =   707,
1733     CV_IA64_P4    =   708,
1734     CV_IA64_P5    =   709,
1735     CV_IA64_P6    =   710,
1736     CV_IA64_P7    =   711,
1737     CV_IA64_P8    =   712,
1738     CV_IA64_P9    =   713,
1739     CV_IA64_P10   =   714,
1740     CV_IA64_P11   =   715,
1741     CV_IA64_P12   =   716,
1742     CV_IA64_P13   =   717,
1743     CV_IA64_P14   =   718,
1744     CV_IA64_P15   =   719,
1745     CV_IA64_P16   =   720,
1746     CV_IA64_P17   =   721,
1747     CV_IA64_P18   =   722,
1748     CV_IA64_P19   =   723,
1749     CV_IA64_P20   =   724,
1750     CV_IA64_P21   =   725,
1751     CV_IA64_P22   =   726,
1752     CV_IA64_P23   =   727,
1753     CV_IA64_P24   =   728,
1754     CV_IA64_P25   =   729,
1755     CV_IA64_P26   =   730,
1756     CV_IA64_P27   =   731,
1757     CV_IA64_P28   =   732,
1758     CV_IA64_P29   =   733,
1759     CV_IA64_P30   =   734,
1760     CV_IA64_P31   =   735,
1761     CV_IA64_P32   =   736,
1762     CV_IA64_P33   =   737,
1763     CV_IA64_P34   =   738,
1764     CV_IA64_P35   =   739,
1765     CV_IA64_P36   =   740,
1766     CV_IA64_P37   =   741,
1767     CV_IA64_P38   =   742,
1768     CV_IA64_P39   =   743,
1769     CV_IA64_P40   =   744,
1770     CV_IA64_P41   =   745,
1771     CV_IA64_P42   =   746,
1772     CV_IA64_P43   =   747,
1773     CV_IA64_P44   =   748,
1774     CV_IA64_P45   =   749,
1775     CV_IA64_P46   =   750,
1776     CV_IA64_P47   =   751,
1777     CV_IA64_P48   =   752,
1778     CV_IA64_P49   =   753,
1779     CV_IA64_P50   =   754,
1780     CV_IA64_P51   =   755,
1781     CV_IA64_P52   =   756,
1782     CV_IA64_P53   =   757,
1783     CV_IA64_P54   =   758,
1784     CV_IA64_P55   =   759,
1785     CV_IA64_P56   =   760,
1786     CV_IA64_P57   =   761,
1787     CV_IA64_P58   =   762,
1788     CV_IA64_P59   =   763,
1789     CV_IA64_P60   =   764,
1790     CV_IA64_P61   =   765,
1791     CV_IA64_P62   =   766,
1792     CV_IA64_P63   =   767,
1793
1794     CV_IA64_Preds   =   768,
1795
1796     // Banked General Registers
1797
1798     CV_IA64_IntH0   =   832,
1799     CV_IA64_IntH1   =   833,
1800     CV_IA64_IntH2   =   834,
1801     CV_IA64_IntH3   =   835,
1802     CV_IA64_IntH4   =   836,
1803     CV_IA64_IntH5   =   837,
1804     CV_IA64_IntH6   =   838,
1805     CV_IA64_IntH7   =   839,
1806     CV_IA64_IntH8   =   840,
1807     CV_IA64_IntH9   =   841,
1808     CV_IA64_IntH10  =   842,
1809     CV_IA64_IntH11  =   843,
1810     CV_IA64_IntH12  =   844,
1811     CV_IA64_IntH13  =   845,
1812     CV_IA64_IntH14  =   846,
1813     CV_IA64_IntH15  =   847,
1814
1815     // Special Registers
1816
1817     CV_IA64_Ip      =   1016,
1818     CV_IA64_Umask   =   1017,
1819     CV_IA64_Cfm     =   1018,
1820     CV_IA64_Psr     =   1019,
1821
1822     // Banked General Registers
1823
1824     CV_IA64_Nats    =   1020,
1825     CV_IA64_Nats2   =   1021,
1826     CV_IA64_Nats3   =   1022,
1827
1828     // General-Purpose Registers
1829
1830     // Integer registers
1831     CV_IA64_IntR0   =   1024,
1832     CV_IA64_IntR1   =   1025,
1833     CV_IA64_IntR2   =   1026,
1834     CV_IA64_IntR3   =   1027,
1835     CV_IA64_IntR4   =   1028,
1836     CV_IA64_IntR5   =   1029,
1837     CV_IA64_IntR6   =   1030,
1838     CV_IA64_IntR7   =   1031,
1839     CV_IA64_IntR8   =   1032,
1840     CV_IA64_IntR9   =   1033,
1841     CV_IA64_IntR10  =   1034,
1842     CV_IA64_IntR11  =   1035,
1843     CV_IA64_IntR12  =   1036,
1844     CV_IA64_IntR13  =   1037,
1845     CV_IA64_IntR14  =   1038,
1846     CV_IA64_IntR15  =   1039,
1847     CV_IA64_IntR16  =   1040,
1848     CV_IA64_IntR17  =   1041,
1849     CV_IA64_IntR18  =   1042,
1850     CV_IA64_IntR19  =   1043,
1851     CV_IA64_IntR20  =   1044,
1852     CV_IA64_IntR21  =   1045,
1853     CV_IA64_IntR22  =   1046,
1854     CV_IA64_IntR23  =   1047,
1855     CV_IA64_IntR24  =   1048,
1856     CV_IA64_IntR25  =   1049,
1857     CV_IA64_IntR26  =   1050,
1858     CV_IA64_IntR27  =   1051,
1859     CV_IA64_IntR28  =   1052,
1860     CV_IA64_IntR29  =   1053,
1861     CV_IA64_IntR30  =   1054,
1862     CV_IA64_IntR31  =   1055,
1863
1864     // Register Stack
1865     CV_IA64_IntR32  =   1056,
1866     CV_IA64_IntR33  =   1057,
1867     CV_IA64_IntR34  =   1058,
1868     CV_IA64_IntR35  =   1059,
1869     CV_IA64_IntR36  =   1060,
1870     CV_IA64_IntR37  =   1061,
1871     CV_IA64_IntR38  =   1062,
1872     CV_IA64_IntR39  =   1063,
1873     CV_IA64_IntR40  =   1064,
1874     CV_IA64_IntR41  =   1065,
1875     CV_IA64_IntR42  =   1066,
1876     CV_IA64_IntR43  =   1067,
1877     CV_IA64_IntR44  =   1068,
1878     CV_IA64_IntR45  =   1069,
1879     CV_IA64_IntR46  =   1070,
1880     CV_IA64_IntR47  =   1071,
1881     CV_IA64_IntR48  =   1072,
1882     CV_IA64_IntR49  =   1073,
1883     CV_IA64_IntR50  =   1074,
1884     CV_IA64_IntR51  =   1075,
1885     CV_IA64_IntR52  =   1076,
1886     CV_IA64_IntR53  =   1077,
1887     CV_IA64_IntR54  =   1078,
1888     CV_IA64_IntR55  =   1079,
1889     CV_IA64_IntR56  =   1080,
1890     CV_IA64_IntR57  =   1081,
1891     CV_IA64_IntR58  =   1082,
1892     CV_IA64_IntR59  =   1083,
1893     CV_IA64_IntR60  =   1084,
1894     CV_IA64_IntR61  =   1085,
1895     CV_IA64_IntR62  =   1086,
1896     CV_IA64_IntR63  =   1087,
1897     CV_IA64_IntR64  =   1088,
1898     CV_IA64_IntR65  =   1089,
1899     CV_IA64_IntR66  =   1090,
1900     CV_IA64_IntR67  =   1091,
1901     CV_IA64_IntR68  =   1092,
1902     CV_IA64_IntR69  =   1093,
1903     CV_IA64_IntR70  =   1094,
1904     CV_IA64_IntR71  =   1095,
1905     CV_IA64_IntR72  =   1096,
1906     CV_IA64_IntR73  =   1097,
1907     CV_IA64_IntR74  =   1098,
1908     CV_IA64_IntR75  =   1099,
1909     CV_IA64_IntR76  =   1100,
1910     CV_IA64_IntR77  =   1101,
1911     CV_IA64_IntR78  =   1102,
1912     CV_IA64_IntR79  =   1103,
1913     CV_IA64_IntR80  =   1104,
1914     CV_IA64_IntR81  =   1105,
1915     CV_IA64_IntR82  =   1106,
1916     CV_IA64_IntR83  =   1107,
1917     CV_IA64_IntR84  =   1108,
1918     CV_IA64_IntR85  =   1109,
1919     CV_IA64_IntR86  =   1110,
1920     CV_IA64_IntR87  =   1111,
1921     CV_IA64_IntR88  =   1112,
1922     CV_IA64_IntR89  =   1113,
1923     CV_IA64_IntR90  =   1114,
1924     CV_IA64_IntR91  =   1115,
1925     CV_IA64_IntR92  =   1116,
1926     CV_IA64_IntR93  =   1117,
1927     CV_IA64_IntR94  =   1118,
1928     CV_IA64_IntR95  =   1119,
1929     CV_IA64_IntR96  =   1120,
1930     CV_IA64_IntR97  =   1121,
1931     CV_IA64_IntR98  =   1122,
1932     CV_IA64_IntR99  =   1123,
1933     CV_IA64_IntR100 =   1124,
1934     CV_IA64_IntR101 =   1125,
1935     CV_IA64_IntR102 =   1126,
1936     CV_IA64_IntR103 =   1127,
1937     CV_IA64_IntR104 =   1128,
1938     CV_IA64_IntR105 =   1129,
1939     CV_IA64_IntR106 =   1130,
1940     CV_IA64_IntR107 =   1131,
1941     CV_IA64_IntR108 =   1132,
1942     CV_IA64_IntR109 =   1133,
1943     CV_IA64_IntR110 =   1134,
1944     CV_IA64_IntR111 =   1135,
1945     CV_IA64_IntR112 =   1136,
1946     CV_IA64_IntR113 =   1137,
1947     CV_IA64_IntR114 =   1138,
1948     CV_IA64_IntR115 =   1139,
1949     CV_IA64_IntR116 =   1140,
1950     CV_IA64_IntR117 =   1141,
1951     CV_IA64_IntR118 =   1142,
1952     CV_IA64_IntR119 =   1143,
1953     CV_IA64_IntR120 =   1144,
1954     CV_IA64_IntR121 =   1145,
1955     CV_IA64_IntR122 =   1146,
1956     CV_IA64_IntR123 =   1147,
1957     CV_IA64_IntR124 =   1148,
1958     CV_IA64_IntR125 =   1149,
1959     CV_IA64_IntR126 =   1150,
1960     CV_IA64_IntR127 =   1151,
1961
1962     // Floating-Point Registers
1963
1964     // Low Floating Point Registers
1965     CV_IA64_FltF0   =   2048,
1966     CV_IA64_FltF1   =   2049,
1967     CV_IA64_FltF2   =   2050,
1968     CV_IA64_FltF3   =   2051,
1969     CV_IA64_FltF4   =   2052,
1970     CV_IA64_FltF5   =   2053,
1971     CV_IA64_FltF6   =   2054,
1972     CV_IA64_FltF7   =   2055,
1973     CV_IA64_FltF8   =   2056,
1974     CV_IA64_FltF9   =   2057,
1975     CV_IA64_FltF10  =   2058,
1976     CV_IA64_FltF11  =   2059,
1977     CV_IA64_FltF12  =   2060,
1978     CV_IA64_FltF13  =   2061,
1979     CV_IA64_FltF14  =   2062,
1980     CV_IA64_FltF15  =   2063,
1981     CV_IA64_FltF16  =   2064,
1982     CV_IA64_FltF17  =   2065,
1983     CV_IA64_FltF18  =   2066,
1984     CV_IA64_FltF19  =   2067,
1985     CV_IA64_FltF20  =   2068,
1986     CV_IA64_FltF21  =   2069,
1987     CV_IA64_FltF22  =   2070,
1988     CV_IA64_FltF23  =   2071,
1989     CV_IA64_FltF24  =   2072,
1990     CV_IA64_FltF25  =   2073,
1991     CV_IA64_FltF26  =   2074,
1992     CV_IA64_FltF27  =   2075,
1993     CV_IA64_FltF28  =   2076,
1994     CV_IA64_FltF29  =   2077,
1995     CV_IA64_FltF30  =   2078,
1996     CV_IA64_FltF31  =   2079,
1997
1998     // High Floating Point Registers
1999     CV_IA64_FltF32  =   2080,
2000     CV_IA64_FltF33  =   2081,
2001     CV_IA64_FltF34  =   2082,
2002     CV_IA64_FltF35  =   2083,
2003     CV_IA64_FltF36  =   2084,
2004     CV_IA64_FltF37  =   2085,
2005     CV_IA64_FltF38  =   2086,
2006     CV_IA64_FltF39  =   2087,
2007     CV_IA64_FltF40  =   2088,
2008     CV_IA64_FltF41  =   2089,
2009     CV_IA64_FltF42  =   2090,
2010     CV_IA64_FltF43  =   2091,
2011     CV_IA64_FltF44  =   2092,
2012     CV_IA64_FltF45  =   2093,
2013     CV_IA64_FltF46  =   2094,
2014     CV_IA64_FltF47  =   2095,
2015     CV_IA64_FltF48  =   2096,
2016     CV_IA64_FltF49  =   2097,
2017     CV_IA64_FltF50  =   2098,
2018     CV_IA64_FltF51  =   2099,
2019     CV_IA64_FltF52  =   2100,
2020     CV_IA64_FltF53  =   2101,
2021     CV_IA64_FltF54  =   2102,
2022     CV_IA64_FltF55  =   2103,
2023     CV_IA64_FltF56  =   2104,
2024     CV_IA64_FltF57  =   2105,
2025     CV_IA64_FltF58  =   2106,
2026     CV_IA64_FltF59  =   2107,
2027     CV_IA64_FltF60  =   2108,
2028     CV_IA64_FltF61  =   2109,
2029     CV_IA64_FltF62  =   2110,
2030     CV_IA64_FltF63  =   2111,
2031     CV_IA64_FltF64  =   2112,
2032     CV_IA64_FltF65  =   2113,
2033     CV_IA64_FltF66  =   2114,
2034     CV_IA64_FltF67  =   2115,
2035     CV_IA64_FltF68  =   2116,
2036     CV_IA64_FltF69  =   2117,
2037     CV_IA64_FltF70  =   2118,
2038     CV_IA64_FltF71  =   2119,
2039     CV_IA64_FltF72  =   2120,
2040     CV_IA64_FltF73  =   2121,
2041     CV_IA64_FltF74  =   2122,
2042     CV_IA64_FltF75  =   2123,
2043     CV_IA64_FltF76  =   2124,
2044     CV_IA64_FltF77  =   2125,
2045     CV_IA64_FltF78  =   2126,
2046     CV_IA64_FltF79  =   2127,
2047     CV_IA64_FltF80  =   2128,
2048     CV_IA64_FltF81  =   2129,
2049     CV_IA64_FltF82  =   2130,
2050     CV_IA64_FltF83  =   2131,
2051     CV_IA64_FltF84  =   2132,
2052     CV_IA64_FltF85  =   2133,
2053     CV_IA64_FltF86  =   2134,
2054     CV_IA64_FltF87  =   2135,
2055     CV_IA64_FltF88  =   2136,
2056     CV_IA64_FltF89  =   2137,
2057     CV_IA64_FltF90  =   2138,
2058     CV_IA64_FltF91  =   2139,
2059     CV_IA64_FltF92  =   2140,
2060     CV_IA64_FltF93  =   2141,
2061     CV_IA64_FltF94  =   2142,
2062     CV_IA64_FltF95  =   2143,
2063     CV_IA64_FltF96  =   2144,
2064     CV_IA64_FltF97  =   2145,
2065     CV_IA64_FltF98  =   2146,
2066     CV_IA64_FltF99  =   2147,
2067     CV_IA64_FltF100 =   2148,
2068     CV_IA64_FltF101 =   2149,
2069     CV_IA64_FltF102 =   2150,
2070     CV_IA64_FltF103 =   2151,
2071     CV_IA64_FltF104 =   2152,
2072     CV_IA64_FltF105 =   2153,
2073     CV_IA64_FltF106 =   2154,
2074     CV_IA64_FltF107 =   2155,
2075     CV_IA64_FltF108 =   2156,
2076     CV_IA64_FltF109 =   2157,
2077     CV_IA64_FltF110 =   2158,
2078     CV_IA64_FltF111 =   2159,
2079     CV_IA64_FltF112 =   2160,
2080     CV_IA64_FltF113 =   2161,
2081     CV_IA64_FltF114 =   2162,
2082     CV_IA64_FltF115 =   2163,
2083     CV_IA64_FltF116 =   2164,
2084     CV_IA64_FltF117 =   2165,
2085     CV_IA64_FltF118 =   2166,
2086     CV_IA64_FltF119 =   2167,
2087     CV_IA64_FltF120 =   2168,
2088     CV_IA64_FltF121 =   2169,
2089     CV_IA64_FltF122 =   2170,
2090     CV_IA64_FltF123 =   2171,
2091     CV_IA64_FltF124 =   2172,
2092     CV_IA64_FltF125 =   2173,
2093     CV_IA64_FltF126 =   2174,
2094     CV_IA64_FltF127 =   2175,
2095
2096     // Application Registers
2097
2098     CV_IA64_ApKR0   =   3072,
2099     CV_IA64_ApKR1   =   3073,
2100     CV_IA64_ApKR2   =   3074,
2101     CV_IA64_ApKR3   =   3075,
2102     CV_IA64_ApKR4   =   3076,
2103     CV_IA64_ApKR5   =   3077,
2104     CV_IA64_ApKR6   =   3078,
2105     CV_IA64_ApKR7   =   3079,
2106     CV_IA64_AR8     =   3080,
2107     CV_IA64_AR9     =   3081,
2108     CV_IA64_AR10    =   3082,
2109     CV_IA64_AR11    =   3083,
2110     CV_IA64_AR12    =   3084,
2111     CV_IA64_AR13    =   3085,
2112     CV_IA64_AR14    =   3086,
2113     CV_IA64_AR15    =   3087,
2114     CV_IA64_RsRSC   =   3088,
2115     CV_IA64_RsBSP   =   3089,
2116     CV_IA64_RsBSPSTORE  =   3090,
2117     CV_IA64_RsRNAT  =   3091,
2118     CV_IA64_AR20    =   3092,
2119     CV_IA64_StFCR   =   3093,
2120     CV_IA64_AR22    =   3094,
2121     CV_IA64_AR23    =   3095,
2122     CV_IA64_EFLAG   =   3096,
2123     CV_IA64_CSD     =   3097,
2124     CV_IA64_SSD     =   3098,
2125     CV_IA64_CFLG    =   3099,
2126     CV_IA64_StFSR   =   3100,
2127     CV_IA64_StFIR   =   3101,
2128     CV_IA64_StFDR   =   3102,
2129     CV_IA64_AR31    =   3103,
2130     CV_IA64_ApCCV   =   3104,
2131     CV_IA64_AR33    =   3105,
2132     CV_IA64_AR34    =   3106,
2133     CV_IA64_AR35    =   3107,
2134     CV_IA64_ApUNAT  =   3108,
2135     CV_IA64_AR37    =   3109,
2136     CV_IA64_AR38    =   3110,
2137     CV_IA64_AR39    =   3111,
2138     CV_IA64_StFPSR  =   3112,
2139     CV_IA64_AR41    =   3113,
2140     CV_IA64_AR42    =   3114,
2141     CV_IA64_AR43    =   3115,
2142     CV_IA64_ApITC   =   3116,
2143     CV_IA64_AR45    =   3117,
2144     CV_IA64_AR46    =   3118,
2145     CV_IA64_AR47    =   3119,
2146     CV_IA64_AR48    =   3120,
2147     CV_IA64_AR49    =   3121,
2148     CV_IA64_AR50    =   3122,
2149     CV_IA64_AR51    =   3123,
2150     CV_IA64_AR52    =   3124,
2151     CV_IA64_AR53    =   3125,
2152     CV_IA64_AR54    =   3126,
2153     CV_IA64_AR55    =   3127,
2154     CV_IA64_AR56    =   3128,
2155     CV_IA64_AR57    =   3129,
2156     CV_IA64_AR58    =   3130,
2157     CV_IA64_AR59    =   3131,
2158     CV_IA64_AR60    =   3132,
2159     CV_IA64_AR61    =   3133,
2160     CV_IA64_AR62    =   3134,
2161     CV_IA64_AR63    =   3135,
2162     CV_IA64_RsPFS   =   3136,
2163     CV_IA64_ApLC    =   3137,
2164     CV_IA64_ApEC    =   3138,
2165     CV_IA64_AR67    =   3139,
2166     CV_IA64_AR68    =   3140,
2167     CV_IA64_AR69    =   3141,
2168     CV_IA64_AR70    =   3142,
2169     CV_IA64_AR71    =   3143,
2170     CV_IA64_AR72    =   3144,
2171     CV_IA64_AR73    =   3145,
2172     CV_IA64_AR74    =   3146,
2173     CV_IA64_AR75    =   3147,
2174     CV_IA64_AR76    =   3148,
2175     CV_IA64_AR77    =   3149,
2176     CV_IA64_AR78    =   3150,
2177     CV_IA64_AR79    =   3151,
2178     CV_IA64_AR80    =   3152,
2179     CV_IA64_AR81    =   3153,
2180     CV_IA64_AR82    =   3154,
2181     CV_IA64_AR83    =   3155,
2182     CV_IA64_AR84    =   3156,
2183     CV_IA64_AR85    =   3157,
2184     CV_IA64_AR86    =   3158,
2185     CV_IA64_AR87    =   3159,
2186     CV_IA64_AR88    =   3160,
2187     CV_IA64_AR89    =   3161,
2188     CV_IA64_AR90    =   3162,
2189     CV_IA64_AR91    =   3163,
2190     CV_IA64_AR92    =   3164,
2191     CV_IA64_AR93    =   3165,
2192     CV_IA64_AR94    =   3166,
2193     CV_IA64_AR95    =   3167,
2194     CV_IA64_AR96    =   3168,
2195     CV_IA64_AR97    =   3169,
2196     CV_IA64_AR98    =   3170,
2197     CV_IA64_AR99    =   3171,
2198     CV_IA64_AR100   =   3172,
2199     CV_IA64_AR101   =   3173,
2200     CV_IA64_AR102   =   3174,
2201     CV_IA64_AR103   =   3175,
2202     CV_IA64_AR104   =   3176,
2203     CV_IA64_AR105   =   3177,
2204     CV_IA64_AR106   =   3178,
2205     CV_IA64_AR107   =   3179,
2206     CV_IA64_AR108   =   3180,
2207     CV_IA64_AR109   =   3181,
2208     CV_IA64_AR110   =   3182,
2209     CV_IA64_AR111   =   3183,
2210     CV_IA64_AR112   =   3184,
2211     CV_IA64_AR113   =   3185,
2212     CV_IA64_AR114   =   3186,
2213     CV_IA64_AR115   =   3187,
2214     CV_IA64_AR116   =   3188,
2215     CV_IA64_AR117   =   3189,
2216     CV_IA64_AR118   =   3190,
2217     CV_IA64_AR119   =   3191,
2218     CV_IA64_AR120   =   3192,
2219     CV_IA64_AR121   =   3193,
2220     CV_IA64_AR122   =   3194,
2221     CV_IA64_AR123   =   3195,
2222     CV_IA64_AR124   =   3196,
2223     CV_IA64_AR125   =   3197,
2224     CV_IA64_AR126   =   3198,
2225     CV_IA64_AR127   =   3199,
2226
2227     // CPUID Registers
2228
2229     CV_IA64_CPUID0  =   3328,
2230     CV_IA64_CPUID1  =   3329,
2231     CV_IA64_CPUID2  =   3330,
2232     CV_IA64_CPUID3  =   3331,
2233     CV_IA64_CPUID4  =   3332,
2234
2235     // Control Registers
2236
2237     CV_IA64_ApDCR   =   4096,
2238     CV_IA64_ApITM   =   4097,
2239     CV_IA64_ApIVA   =   4098,
2240     CV_IA64_CR3     =   4099,
2241     CV_IA64_CR4     =   4100,
2242     CV_IA64_CR5     =   4101,
2243     CV_IA64_CR6     =   4102,
2244     CV_IA64_CR7     =   4103,
2245     CV_IA64_ApPTA   =   4104,
2246     CV_IA64_ApGPTA  =   4105,
2247     CV_IA64_CR10    =   4106,
2248     CV_IA64_CR11    =   4107,
2249     CV_IA64_CR12    =   4108,
2250     CV_IA64_CR13    =   4109,
2251     CV_IA64_CR14    =   4110,
2252     CV_IA64_CR15    =   4111,
2253     CV_IA64_StIPSR  =   4112,
2254     CV_IA64_StISR   =   4113,
2255     CV_IA64_CR18    =   4114,
2256     CV_IA64_StIIP   =   4115,
2257     CV_IA64_StIFA   =   4116,
2258     CV_IA64_StITIR  =   4117,
2259     CV_IA64_StIIPA  =   4118,
2260     CV_IA64_StIFS   =   4119,
2261     CV_IA64_StIIM   =   4120,
2262     CV_IA64_StIHA   =   4121,
2263     CV_IA64_CR26    =   4122,
2264     CV_IA64_CR27    =   4123,
2265     CV_IA64_CR28    =   4124,
2266     CV_IA64_CR29    =   4125,
2267     CV_IA64_CR30    =   4126,
2268     CV_IA64_CR31    =   4127,
2269     CV_IA64_CR32    =   4128,
2270     CV_IA64_CR33    =   4129,
2271     CV_IA64_CR34    =   4130,
2272     CV_IA64_CR35    =   4131,
2273     CV_IA64_CR36    =   4132,
2274     CV_IA64_CR37    =   4133,
2275     CV_IA64_CR38    =   4134,
2276     CV_IA64_CR39    =   4135,
2277     CV_IA64_CR40    =   4136,
2278     CV_IA64_CR41    =   4137,
2279     CV_IA64_CR42    =   4138,
2280     CV_IA64_CR43    =   4139,
2281     CV_IA64_CR44    =   4140,
2282     CV_IA64_CR45    =   4141,
2283     CV_IA64_CR46    =   4142,
2284     CV_IA64_CR47    =   4143,
2285     CV_IA64_CR48    =   4144,
2286     CV_IA64_CR49    =   4145,
2287     CV_IA64_CR50    =   4146,
2288     CV_IA64_CR51    =   4147,
2289     CV_IA64_CR52    =   4148,
2290     CV_IA64_CR53    =   4149,
2291     CV_IA64_CR54    =   4150,
2292     CV_IA64_CR55    =   4151,
2293     CV_IA64_CR56    =   4152,
2294     CV_IA64_CR57    =   4153,
2295     CV_IA64_CR58    =   4154,
2296     CV_IA64_CR59    =   4155,
2297     CV_IA64_CR60    =   4156,
2298     CV_IA64_CR61    =   4157,
2299     CV_IA64_CR62    =   4158,
2300     CV_IA64_CR63    =   4159,
2301     CV_IA64_SaLID   =   4160,
2302     CV_IA64_SaIVR   =   4161,
2303     CV_IA64_SaTPR   =   4162,
2304     CV_IA64_SaEOI   =   4163,
2305     CV_IA64_SaIRR0  =   4164,
2306     CV_IA64_SaIRR1  =   4165,
2307     CV_IA64_SaIRR2  =   4166,
2308     CV_IA64_SaIRR3  =   4167,
2309     CV_IA64_SaITV   =   4168,
2310     CV_IA64_SaPMV   =   4169,
2311     CV_IA64_SaCMCV  =   4170,
2312     CV_IA64_CR75    =   4171,
2313     CV_IA64_CR76    =   4172,
2314     CV_IA64_CR77    =   4173,
2315     CV_IA64_CR78    =   4174,
2316     CV_IA64_CR79    =   4175,
2317     CV_IA64_SaLRR0  =   4176,
2318     CV_IA64_SaLRR1  =   4177,
2319     CV_IA64_CR82    =   4178,
2320     CV_IA64_CR83    =   4179,
2321     CV_IA64_CR84    =   4180,
2322     CV_IA64_CR85    =   4181,
2323     CV_IA64_CR86    =   4182,
2324     CV_IA64_CR87    =   4183,
2325     CV_IA64_CR88    =   4184,
2326     CV_IA64_CR89    =   4185,
2327     CV_IA64_CR90    =   4186,
2328     CV_IA64_CR91    =   4187,
2329     CV_IA64_CR92    =   4188,
2330     CV_IA64_CR93    =   4189,
2331     CV_IA64_CR94    =   4190,
2332     CV_IA64_CR95    =   4191,
2333     CV_IA64_CR96    =   4192,
2334     CV_IA64_CR97    =   4193,
2335     CV_IA64_CR98    =   4194,
2336     CV_IA64_CR99    =   4195,
2337     CV_IA64_CR100   =   4196,
2338     CV_IA64_CR101   =   4197,
2339     CV_IA64_CR102   =   4198,
2340     CV_IA64_CR103   =   4199,
2341     CV_IA64_CR104   =   4200,
2342     CV_IA64_CR105   =   4201,
2343     CV_IA64_CR106   =   4202,
2344     CV_IA64_CR107   =   4203,
2345     CV_IA64_CR108   =   4204,
2346     CV_IA64_CR109   =   4205,
2347     CV_IA64_CR110   =   4206,
2348     CV_IA64_CR111   =   4207,
2349     CV_IA64_CR112   =   4208,
2350     CV_IA64_CR113   =   4209,
2351     CV_IA64_CR114   =   4210,
2352     CV_IA64_CR115   =   4211,
2353     CV_IA64_CR116   =   4212,
2354     CV_IA64_CR117   =   4213,
2355     CV_IA64_CR118   =   4214,
2356     CV_IA64_CR119   =   4215,
2357     CV_IA64_CR120   =   4216,
2358     CV_IA64_CR121   =   4217,
2359     CV_IA64_CR122   =   4218,
2360     CV_IA64_CR123   =   4219,
2361     CV_IA64_CR124   =   4220,
2362     CV_IA64_CR125   =   4221,
2363     CV_IA64_CR126   =   4222,
2364     CV_IA64_CR127   =   4223,
2365
2366     // Protection Key Registers
2367
2368     CV_IA64_Pkr0    =   5120,
2369     CV_IA64_Pkr1    =   5121,
2370     CV_IA64_Pkr2    =   5122,
2371     CV_IA64_Pkr3    =   5123,
2372     CV_IA64_Pkr4    =   5124,
2373     CV_IA64_Pkr5    =   5125,
2374     CV_IA64_Pkr6    =   5126,
2375     CV_IA64_Pkr7    =   5127,
2376     CV_IA64_Pkr8    =   5128,
2377     CV_IA64_Pkr9    =   5129,
2378     CV_IA64_Pkr10   =   5130,
2379     CV_IA64_Pkr11   =   5131,
2380     CV_IA64_Pkr12   =   5132,
2381     CV_IA64_Pkr13   =   5133,
2382     CV_IA64_Pkr14   =   5134,
2383     CV_IA64_Pkr15   =   5135,
2384
2385     // Region Registers
2386
2387     CV_IA64_Rr0     =   6144,
2388     CV_IA64_Rr1     =   6145,
2389     CV_IA64_Rr2     =   6146,
2390     CV_IA64_Rr3     =   6147,
2391     CV_IA64_Rr4     =   6148,
2392     CV_IA64_Rr5     =   6149,
2393     CV_IA64_Rr6     =   6150,
2394     CV_IA64_Rr7     =   6151,
2395
2396     // Performance Monitor Data Registers
2397
2398     CV_IA64_PFD0    =   7168,
2399     CV_IA64_PFD1    =   7169,
2400     CV_IA64_PFD2    =   7170,
2401     CV_IA64_PFD3    =   7171,
2402     CV_IA64_PFD4    =   7172,
2403     CV_IA64_PFD5    =   7173,
2404     CV_IA64_PFD6    =   7174,
2405     CV_IA64_PFD7    =   7175,
2406     CV_IA64_PFD8    =   7176,
2407     CV_IA64_PFD9    =   7177,
2408     CV_IA64_PFD10   =   7178,
2409     CV_IA64_PFD11   =   7179,
2410     CV_IA64_PFD12   =   7180,
2411     CV_IA64_PFD13   =   7181,
2412     CV_IA64_PFD14   =   7182,
2413     CV_IA64_PFD15   =   7183,
2414     CV_IA64_PFD16   =   7184,
2415     CV_IA64_PFD17   =   7185,
2416
2417     // Performance Monitor Config Registers
2418
2419     CV_IA64_PFC0    =   7424,
2420     CV_IA64_PFC1    =   7425,
2421     CV_IA64_PFC2    =   7426,
2422     CV_IA64_PFC3    =   7427,
2423     CV_IA64_PFC4    =   7428,
2424     CV_IA64_PFC5    =   7429,
2425     CV_IA64_PFC6    =   7430,
2426     CV_IA64_PFC7    =   7431,
2427     CV_IA64_PFC8    =   7432,
2428     CV_IA64_PFC9    =   7433,
2429     CV_IA64_PFC10   =   7434,
2430     CV_IA64_PFC11   =   7435,
2431     CV_IA64_PFC12   =   7436,
2432     CV_IA64_PFC13   =   7437,
2433     CV_IA64_PFC14   =   7438,
2434     CV_IA64_PFC15   =   7439,
2435
2436     // Instruction Translation Registers
2437
2438     CV_IA64_TrI0    =   8192,
2439     CV_IA64_TrI1    =   8193,
2440     CV_IA64_TrI2    =   8194,
2441     CV_IA64_TrI3    =   8195,
2442     CV_IA64_TrI4    =   8196,
2443     CV_IA64_TrI5    =   8197,
2444     CV_IA64_TrI6    =   8198,
2445     CV_IA64_TrI7    =   8199,
2446
2447     // Data Translation Registers
2448
2449     CV_IA64_TrD0    =   8320,
2450     CV_IA64_TrD1    =   8321,
2451     CV_IA64_TrD2    =   8322,
2452     CV_IA64_TrD3    =   8323,
2453     CV_IA64_TrD4    =   8324,
2454     CV_IA64_TrD5    =   8325,
2455     CV_IA64_TrD6    =   8326,
2456     CV_IA64_TrD7    =   8327,
2457
2458     // Instruction Breakpoint Registers
2459
2460     CV_IA64_DbI0    =   8448,
2461     CV_IA64_DbI1    =   8449,
2462     CV_IA64_DbI2    =   8450,
2463     CV_IA64_DbI3    =   8451,
2464     CV_IA64_DbI4    =   8452,
2465     CV_IA64_DbI5    =   8453,
2466     CV_IA64_DbI6    =   8454,
2467     CV_IA64_DbI7    =   8455,
2468
2469     // Data Breakpoint Registers
2470
2471     CV_IA64_DbD0    =   8576,
2472     CV_IA64_DbD1    =   8577,
2473     CV_IA64_DbD2    =   8578,
2474     CV_IA64_DbD3    =   8579,
2475     CV_IA64_DbD4    =   8580,
2476     CV_IA64_DbD5    =   8581,
2477     CV_IA64_DbD6    =   8582,
2478     CV_IA64_DbD7    =   8583,
2479
2480     //
2481     // Register set for the TriCore processor.
2482     //
2483
2484     CV_TRI_NOREG    =   CV_REG_NONE,
2485
2486     // General Purpose Data Registers
2487
2488     CV_TRI_D0   =   10,
2489     CV_TRI_D1   =   11,
2490     CV_TRI_D2   =   12,
2491     CV_TRI_D3   =   13,
2492     CV_TRI_D4   =   14,
2493     CV_TRI_D5   =   15,
2494     CV_TRI_D6   =   16,
2495     CV_TRI_D7   =   17,
2496     CV_TRI_D8   =   18,
2497     CV_TRI_D9   =   19,
2498     CV_TRI_D10  =   20,
2499     CV_TRI_D11  =   21,
2500     CV_TRI_D12  =   22,
2501     CV_TRI_D13  =   23,
2502     CV_TRI_D14  =   24,
2503     CV_TRI_D15  =   25,
2504
2505     // General Purpose Address Registers
2506
2507     CV_TRI_A0   =   26,
2508     CV_TRI_A1   =   27,
2509     CV_TRI_A2   =   28,
2510     CV_TRI_A3   =   29,
2511     CV_TRI_A4   =   30,
2512     CV_TRI_A5   =   31,
2513     CV_TRI_A6   =   32,
2514     CV_TRI_A7   =   33,
2515     CV_TRI_A8   =   34,
2516     CV_TRI_A9   =   35,
2517     CV_TRI_A10  =   36,
2518     CV_TRI_A11  =   37,
2519     CV_TRI_A12  =   38,
2520     CV_TRI_A13  =   39,
2521     CV_TRI_A14  =   40,
2522     CV_TRI_A15  =   41,
2523
2524     // Extended (64-bit) data registers
2525
2526     CV_TRI_E0   =   42,
2527     CV_TRI_E2   =   43,
2528     CV_TRI_E4   =   44,
2529     CV_TRI_E6   =   45,
2530     CV_TRI_E8   =   46,
2531     CV_TRI_E10  =   47,
2532     CV_TRI_E12  =   48,
2533     CV_TRI_E14  =   49,
2534
2535     // Extended (64-bit) address registers
2536
2537     CV_TRI_EA0  =   50,
2538     CV_TRI_EA2  =   51,
2539     CV_TRI_EA4  =   52,
2540     CV_TRI_EA6  =   53,
2541     CV_TRI_EA8  =   54,
2542     CV_TRI_EA10 =   55,
2543     CV_TRI_EA12 =   56,
2544     CV_TRI_EA14 =   57,
2545
2546     CV_TRI_PSW  =   58,
2547     CV_TRI_PCXI =   59,
2548     CV_TRI_PC   =   60,
2549     CV_TRI_FCX  =   61,
2550     CV_TRI_LCX  =   62,
2551     CV_TRI_ISP  =   63,
2552     CV_TRI_ICR  =   64,
2553     CV_TRI_BIV  =   65,
2554     CV_TRI_BTV  =   66,
2555     CV_TRI_SYSCON   =   67,
2556     CV_TRI_DPRx_0   =   68,
2557     CV_TRI_DPRx_1   =   69,
2558     CV_TRI_DPRx_2   =   70,
2559     CV_TRI_DPRx_3   =   71,
2560     CV_TRI_CPRx_0   =   68,
2561     CV_TRI_CPRx_1   =   69,
2562     CV_TRI_CPRx_2   =   70,
2563     CV_TRI_CPRx_3   =   71,
2564     CV_TRI_DPMx_0   =   68,
2565     CV_TRI_DPMx_1   =   69,
2566     CV_TRI_DPMx_2   =   70,
2567     CV_TRI_DPMx_3   =   71,
2568     CV_TRI_CPMx_0   =   68,
2569     CV_TRI_CPMx_1   =   69,
2570     CV_TRI_CPMx_2   =   70,
2571     CV_TRI_CPMx_3   =   71,
2572     CV_TRI_DBGSSR   =   72,
2573     CV_TRI_EXEVT    =   73,
2574     CV_TRI_SWEVT    =   74,
2575     CV_TRI_CREVT    =   75,
2576     CV_TRI_TRnEVT   =   76,
2577     CV_TRI_MMUCON   =   77,
2578     CV_TRI_ASI      =   78,
2579     CV_TRI_TVA      =   79,
2580     CV_TRI_TPA      =   80,
2581     CV_TRI_TPX      =   81,
2582     CV_TRI_TFA      =   82,
2583
2584     //
2585     // Register set for the AM33 and related processors.
2586     //
2587
2588     CV_AM33_NOREG   =   CV_REG_NONE,
2589
2590     // "Extended" (general purpose integer) registers
2591     CV_AM33_E0      =   10,
2592     CV_AM33_E1      =   11,
2593     CV_AM33_E2      =   12,
2594     CV_AM33_E3      =   13,
2595     CV_AM33_E4      =   14,
2596     CV_AM33_E5      =   15,
2597     CV_AM33_E6      =   16,
2598     CV_AM33_E7      =   17,
2599
2600     // Address registers
2601     CV_AM33_A0      =   20,
2602     CV_AM33_A1      =   21,
2603     CV_AM33_A2      =   22,
2604     CV_AM33_A3      =   23,
2605
2606     // Integer data registers
2607     CV_AM33_D0      =   30,
2608     CV_AM33_D1      =   31,
2609     CV_AM33_D2      =   32,
2610     CV_AM33_D3      =   33,
2611
2612     // (Single-precision) floating-point registers
2613     CV_AM33_FS0     =   40,
2614     CV_AM33_FS1     =   41,
2615     CV_AM33_FS2     =   42,
2616     CV_AM33_FS3     =   43,
2617     CV_AM33_FS4     =   44,
2618     CV_AM33_FS5     =   45,
2619     CV_AM33_FS6     =   46,
2620     CV_AM33_FS7     =   47,
2621     CV_AM33_FS8     =   48,
2622     CV_AM33_FS9     =   49,
2623     CV_AM33_FS10    =   50,
2624     CV_AM33_FS11    =   51,
2625     CV_AM33_FS12    =   52,
2626     CV_AM33_FS13    =   53,
2627     CV_AM33_FS14    =   54,
2628     CV_AM33_FS15    =   55,
2629     CV_AM33_FS16    =   56,
2630     CV_AM33_FS17    =   57,
2631     CV_AM33_FS18    =   58,
2632     CV_AM33_FS19    =   59,
2633     CV_AM33_FS20    =   60,
2634     CV_AM33_FS21    =   61,
2635     CV_AM33_FS22    =   62,
2636     CV_AM33_FS23    =   63,
2637     CV_AM33_FS24    =   64,
2638     CV_AM33_FS25    =   65,
2639     CV_AM33_FS26    =   66,
2640     CV_AM33_FS27    =   67,
2641     CV_AM33_FS28    =   68,
2642     CV_AM33_FS29    =   69,
2643     CV_AM33_FS30    =   70,
2644     CV_AM33_FS31    =   71,
2645
2646     // Special purpose registers
2647
2648     // Stack pointer
2649     CV_AM33_SP      =   80,
2650
2651     // Program counter
2652     CV_AM33_PC      =   81,
2653
2654     // Multiply-divide/accumulate registers
2655     CV_AM33_MDR     =   82,
2656     CV_AM33_MDRQ    =   83,
2657     CV_AM33_MCRH    =   84,
2658     CV_AM33_MCRL    =   85,
2659     CV_AM33_MCVF    =   86,
2660
2661     // CPU status words
2662     CV_AM33_EPSW    =   87,
2663     CV_AM33_FPCR    =   88,
2664
2665     // Loop buffer registers
2666     CV_AM33_LIR     =   89,
2667     CV_AM33_LAR     =   90,
2668
2669     //
2670     // Register set for the Mitsubishi M32R
2671     //
2672
2673     CV_M32R_NOREG    =   CV_REG_NONE,
2674
2675     CV_M32R_R0    =   10,
2676     CV_M32R_R1    =   11,
2677     CV_M32R_R2    =   12,
2678     CV_M32R_R3    =   13,
2679     CV_M32R_R4    =   14,
2680     CV_M32R_R5    =   15,
2681     CV_M32R_R6    =   16,
2682     CV_M32R_R7    =   17,
2683     CV_M32R_R8    =   18,
2684     CV_M32R_R9    =   19,
2685     CV_M32R_R10   =   20,
2686     CV_M32R_R11   =   21,
2687     CV_M32R_R12   =   22,   // Gloabal Pointer, if used
2688     CV_M32R_R13   =   23,   // Frame Pointer, if allocated
2689     CV_M32R_R14   =   24,   // Link Register
2690     CV_M32R_R15   =   25,   // Stack Pointer
2691     CV_M32R_PSW   =   26,   // Preocessor Status Register
2692     CV_M32R_CBR   =   27,   // Condition Bit Register
2693     CV_M32R_SPI   =   28,   // Interrupt Stack Pointer
2694     CV_M32R_SPU   =   29,   // User Stack Pointer
2695     CV_M32R_SPO   =   30,   // OS Stack Pointer
2696     CV_M32R_BPC   =   31,   // Backup Program Counter
2697     CV_M32R_ACHI  =   32,   // Accumulator High
2698     CV_M32R_ACLO  =   33,   // Accumulator Low
2699     CV_M32R_PC    =   34,   // Program Counter
2700
2701     //
2702     // Register set for the SuperH SHMedia processor including compact
2703     // mode
2704     //
2705
2706     // Integer - 64 bit general registers
2707     CV_SHMEDIA_NOREG   =   CV_REG_NONE,
2708     CV_SHMEDIA_R0      =   10,
2709     CV_SHMEDIA_R1      =   11,
2710     CV_SHMEDIA_R2      =   12,
2711     CV_SHMEDIA_R3      =   13,
2712     CV_SHMEDIA_R4      =   14,
2713     CV_SHMEDIA_R5      =   15,
2714     CV_SHMEDIA_R6      =   16,
2715     CV_SHMEDIA_R7      =   17,
2716     CV_SHMEDIA_R8      =   18,
2717     CV_SHMEDIA_R9      =   19,
2718     CV_SHMEDIA_R10     =   20,
2719     CV_SHMEDIA_R11     =   21,
2720     CV_SHMEDIA_R12     =   22,
2721     CV_SHMEDIA_R13     =   23,
2722     CV_SHMEDIA_R14     =   24,
2723     CV_SHMEDIA_R15     =   25,
2724     CV_SHMEDIA_R16     =   26,
2725     CV_SHMEDIA_R17     =   27,
2726     CV_SHMEDIA_R18     =   28,
2727     CV_SHMEDIA_R19     =   29,
2728     CV_SHMEDIA_R20     =   30,
2729     CV_SHMEDIA_R21     =   31,
2730     CV_SHMEDIA_R22     =   32,
2731     CV_SHMEDIA_R23     =   33,
2732     CV_SHMEDIA_R24     =   34,
2733     CV_SHMEDIA_R25     =   35,
2734     CV_SHMEDIA_R26     =   36,
2735     CV_SHMEDIA_R27     =   37,
2736     CV_SHMEDIA_R28     =   38,
2737     CV_SHMEDIA_R29     =   39,
2738     CV_SHMEDIA_R30     =   40,
2739     CV_SHMEDIA_R31     =   41,
2740     CV_SHMEDIA_R32     =   42,
2741     CV_SHMEDIA_R33     =   43,
2742     CV_SHMEDIA_R34     =   44,
2743     CV_SHMEDIA_R35     =   45,
2744     CV_SHMEDIA_R36     =   46,
2745     CV_SHMEDIA_R37     =   47,
2746     CV_SHMEDIA_R38     =   48,
2747     CV_SHMEDIA_R39     =   49,
2748     CV_SHMEDIA_R40     =   50,
2749     CV_SHMEDIA_R41     =   51,
2750     CV_SHMEDIA_R42     =   52,
2751     CV_SHMEDIA_R43     =   53,
2752     CV_SHMEDIA_R44     =   54,
2753     CV_SHMEDIA_R45     =   55,
2754     CV_SHMEDIA_R46     =   56,
2755     CV_SHMEDIA_R47     =   57,
2756     CV_SHMEDIA_R48     =   58,
2757     CV_SHMEDIA_R49     =   59,
2758     CV_SHMEDIA_R50     =   60,
2759     CV_SHMEDIA_R51     =   61,
2760     CV_SHMEDIA_R52     =   62,
2761     CV_SHMEDIA_R53     =   63,
2762     CV_SHMEDIA_R54     =   64,
2763     CV_SHMEDIA_R55     =   65,
2764     CV_SHMEDIA_R56     =   66,
2765     CV_SHMEDIA_R57     =   67,
2766     CV_SHMEDIA_R58     =   68,
2767     CV_SHMEDIA_R59     =   69,
2768     CV_SHMEDIA_R60     =   70,
2769     CV_SHMEDIA_R61     =   71,
2770     CV_SHMEDIA_R62     =   72,
2771     CV_SHMEDIA_R63     =   73,
2772     
2773     // Target Registers - 32 bit
2774     CV_SHMEDIA_TR0     =   74,
2775     CV_SHMEDIA_TR1     =   75,
2776     CV_SHMEDIA_TR2     =   76,
2777     CV_SHMEDIA_TR3     =   77,
2778     CV_SHMEDIA_TR4     =   78,
2779     CV_SHMEDIA_TR5     =   79,
2780     CV_SHMEDIA_TR6     =   80,
2781     CV_SHMEDIA_TR7     =   81,
2782     CV_SHMEDIA_TR8     =   82, // future-proof
2783     CV_SHMEDIA_TR9     =   83, // future-proof
2784     CV_SHMEDIA_TR10    =   84, // future-proof
2785     CV_SHMEDIA_TR11    =   85, // future-proof
2786     CV_SHMEDIA_TR12    =   86, // future-proof
2787     CV_SHMEDIA_TR13    =   87, // future-proof
2788     CV_SHMEDIA_TR14    =   88, // future-proof
2789     CV_SHMEDIA_TR15    =   89, // future-proof
2790
2791     // Single - 32 bit fp registers
2792     CV_SHMEDIA_FR0     =   128,
2793     CV_SHMEDIA_FR1     =   129,
2794     CV_SHMEDIA_FR2     =   130,
2795     CV_SHMEDIA_FR3     =   131,
2796     CV_SHMEDIA_FR4     =   132,
2797     CV_SHMEDIA_FR5     =   133,
2798     CV_SHMEDIA_FR6     =   134,
2799     CV_SHMEDIA_FR7     =   135,
2800     CV_SHMEDIA_FR8     =   136,
2801     CV_SHMEDIA_FR9     =   137,
2802     CV_SHMEDIA_FR10    =   138,
2803     CV_SHMEDIA_FR11    =   139,
2804     CV_SHMEDIA_FR12    =   140,
2805     CV_SHMEDIA_FR13    =   141,
2806     CV_SHMEDIA_FR14    =   142,
2807     CV_SHMEDIA_FR15    =   143,
2808     CV_SHMEDIA_FR16    =   144,
2809     CV_SHMEDIA_FR17    =   145,
2810     CV_SHMEDIA_FR18    =   146,
2811     CV_SHMEDIA_FR19    =   147,
2812     CV_SHMEDIA_FR20    =   148,
2813     CV_SHMEDIA_FR21    =   149,
2814     CV_SHMEDIA_FR22    =   150,
2815     CV_SHMEDIA_FR23    =   151,
2816     CV_SHMEDIA_FR24    =   152,
2817     CV_SHMEDIA_FR25    =   153,
2818     CV_SHMEDIA_FR26    =   154,
2819     CV_SHMEDIA_FR27    =   155,
2820     CV_SHMEDIA_FR28    =   156,
2821     CV_SHMEDIA_FR29    =   157,
2822     CV_SHMEDIA_FR30    =   158,
2823     CV_SHMEDIA_FR31    =   159,
2824     CV_SHMEDIA_FR32    =   160,
2825     CV_SHMEDIA_FR33    =   161,
2826     CV_SHMEDIA_FR34    =   162,
2827     CV_SHMEDIA_FR35    =   163,
2828     CV_SHMEDIA_FR36    =   164,
2829     CV_SHMEDIA_FR37    =   165,
2830     CV_SHMEDIA_FR38    =   166,
2831     CV_SHMEDIA_FR39    =   167,
2832     CV_SHMEDIA_FR40    =   168,
2833     CV_SHMEDIA_FR41    =   169,
2834     CV_SHMEDIA_FR42    =   170,
2835     CV_SHMEDIA_FR43    =   171,
2836     CV_SHMEDIA_FR44    =   172,
2837     CV_SHMEDIA_FR45    =   173,
2838     CV_SHMEDIA_FR46    =   174,
2839     CV_SHMEDIA_FR47    =   175,
2840     CV_SHMEDIA_FR48    =   176,
2841     CV_SHMEDIA_FR49    =   177,
2842     CV_SHMEDIA_FR50    =   178,
2843     CV_SHMEDIA_FR51    =   179,
2844     CV_SHMEDIA_FR52    =   180,
2845     CV_SHMEDIA_FR53    =   181,
2846     CV_SHMEDIA_FR54    =   182,
2847     CV_SHMEDIA_FR55    =   183,
2848     CV_SHMEDIA_FR56    =   184,
2849     CV_SHMEDIA_FR57    =   185,
2850     CV_SHMEDIA_FR58    =   186,
2851     CV_SHMEDIA_FR59    =   187,
2852     CV_SHMEDIA_FR60    =   188,
2853     CV_SHMEDIA_FR61    =   189,
2854     CV_SHMEDIA_FR62    =   190,
2855     CV_SHMEDIA_FR63    =   191,
2856
2857     // Double - 64 bit synonyms for 32bit fp register pairs
2858     //          subtract 128 to find first base single register
2859     CV_SHMEDIA_DR0     =   256,
2860     CV_SHMEDIA_DR2     =   258,
2861     CV_SHMEDIA_DR4     =   260,
2862     CV_SHMEDIA_DR6     =   262,
2863     CV_SHMEDIA_DR8     =   264,
2864     CV_SHMEDIA_DR10    =   266,
2865     CV_SHMEDIA_DR12    =   268,
2866     CV_SHMEDIA_DR14    =   270,
2867     CV_SHMEDIA_DR16    =   272,
2868     CV_SHMEDIA_DR18    =   274,
2869     CV_SHMEDIA_DR20    =   276,
2870     CV_SHMEDIA_DR22    =   278,
2871     CV_SHMEDIA_DR24    =   280,
2872     CV_SHMEDIA_DR26    =   282,
2873     CV_SHMEDIA_DR28    =   284,
2874     CV_SHMEDIA_DR30    =   286,
2875     CV_SHMEDIA_DR32    =   288,
2876     CV_SHMEDIA_DR34    =   290,
2877     CV_SHMEDIA_DR36    =   292,
2878     CV_SHMEDIA_DR38    =   294,
2879     CV_SHMEDIA_DR40    =   296,
2880     CV_SHMEDIA_DR42    =   298,
2881     CV_SHMEDIA_DR44    =   300,
2882     CV_SHMEDIA_DR46    =   302,
2883     CV_SHMEDIA_DR48    =   304,
2884     CV_SHMEDIA_DR50    =   306,
2885     CV_SHMEDIA_DR52    =   308,
2886     CV_SHMEDIA_DR54    =   310,
2887     CV_SHMEDIA_DR56    =   312,
2888     CV_SHMEDIA_DR58    =   314,
2889     CV_SHMEDIA_DR60    =   316,
2890     CV_SHMEDIA_DR62    =   318,
2891
2892     // Vector - 128 bit synonyms for 32bit fp register quads
2893     //          subtract 384 to find first base single register
2894     CV_SHMEDIA_FV0     =   512,
2895     CV_SHMEDIA_FV4     =   516,
2896     CV_SHMEDIA_FV8     =   520,
2897     CV_SHMEDIA_FV12    =   524,
2898     CV_SHMEDIA_FV16    =   528,
2899     CV_SHMEDIA_FV20    =   532,
2900     CV_SHMEDIA_FV24    =   536,
2901     CV_SHMEDIA_FV28    =   540,
2902     CV_SHMEDIA_FV32    =   544,
2903     CV_SHMEDIA_FV36    =   548,
2904     CV_SHMEDIA_FV40    =   552,
2905     CV_SHMEDIA_FV44    =   556,
2906     CV_SHMEDIA_FV48    =   560,
2907     CV_SHMEDIA_FV52    =   564,
2908     CV_SHMEDIA_FV56    =   568,
2909     CV_SHMEDIA_FV60    =   572,
2910
2911     // Matrix - 512 bit synonyms for 16 adjacent 32bit fp registers
2912     //          subtract 896 to find first base single register
2913     CV_SHMEDIA_MTRX0   =   1024,
2914     CV_SHMEDIA_MTRX16  =   1040,
2915     CV_SHMEDIA_MTRX32  =   1056,
2916     CV_SHMEDIA_MTRX48  =   1072,
2917
2918     // Control - Implementation defined 64bit control registers
2919     CV_SHMEDIA_CR0     =   2000,
2920     CV_SHMEDIA_CR1     =   2001,
2921     CV_SHMEDIA_CR2     =   2002,
2922     CV_SHMEDIA_CR3     =   2003,
2923     CV_SHMEDIA_CR4     =   2004,
2924     CV_SHMEDIA_CR5     =   2005,
2925     CV_SHMEDIA_CR6     =   2006,
2926     CV_SHMEDIA_CR7     =   2007,
2927     CV_SHMEDIA_CR8     =   2008,
2928     CV_SHMEDIA_CR9     =   2009,
2929     CV_SHMEDIA_CR10    =   2010,
2930     CV_SHMEDIA_CR11    =   2011,
2931     CV_SHMEDIA_CR12    =   2012,
2932     CV_SHMEDIA_CR13    =   2013,
2933     CV_SHMEDIA_CR14    =   2014,
2934     CV_SHMEDIA_CR15    =   2015,
2935     CV_SHMEDIA_CR16    =   2016,
2936     CV_SHMEDIA_CR17    =   2017,
2937     CV_SHMEDIA_CR18    =   2018,
2938     CV_SHMEDIA_CR19    =   2019,
2939     CV_SHMEDIA_CR20    =   2020,
2940     CV_SHMEDIA_CR21    =   2021,
2941     CV_SHMEDIA_CR22    =   2022,
2942     CV_SHMEDIA_CR23    =   2023,
2943     CV_SHMEDIA_CR24    =   2024,
2944     CV_SHMEDIA_CR25    =   2025,
2945     CV_SHMEDIA_CR26    =   2026,
2946     CV_SHMEDIA_CR27    =   2027,
2947     CV_SHMEDIA_CR28    =   2028,
2948     CV_SHMEDIA_CR29    =   2029,
2949     CV_SHMEDIA_CR30    =   2030,
2950     CV_SHMEDIA_CR31    =   2031,
2951     CV_SHMEDIA_CR32    =   2032,
2952     CV_SHMEDIA_CR33    =   2033,
2953     CV_SHMEDIA_CR34    =   2034,
2954     CV_SHMEDIA_CR35    =   2035,
2955     CV_SHMEDIA_CR36    =   2036,
2956     CV_SHMEDIA_CR37    =   2037,
2957     CV_SHMEDIA_CR38    =   2038,
2958     CV_SHMEDIA_CR39    =   2039,
2959     CV_SHMEDIA_CR40    =   2040,
2960     CV_SHMEDIA_CR41    =   2041,
2961     CV_SHMEDIA_CR42    =   2042,
2962     CV_SHMEDIA_CR43    =   2043,
2963     CV_SHMEDIA_CR44    =   2044,
2964     CV_SHMEDIA_CR45    =   2045,
2965     CV_SHMEDIA_CR46    =   2046,
2966     CV_SHMEDIA_CR47    =   2047,
2967     CV_SHMEDIA_CR48    =   2048,
2968     CV_SHMEDIA_CR49    =   2049,
2969     CV_SHMEDIA_CR50    =   2050,
2970     CV_SHMEDIA_CR51    =   2051,
2971     CV_SHMEDIA_CR52    =   2052,
2972     CV_SHMEDIA_CR53    =   2053,
2973     CV_SHMEDIA_CR54    =   2054,
2974     CV_SHMEDIA_CR55    =   2055,
2975     CV_SHMEDIA_CR56    =   2056,
2976     CV_SHMEDIA_CR57    =   2057,
2977     CV_SHMEDIA_CR58    =   2058,
2978     CV_SHMEDIA_CR59    =   2059,
2979     CV_SHMEDIA_CR60    =   2060,
2980     CV_SHMEDIA_CR61    =   2061,
2981     CV_SHMEDIA_CR62    =   2062,
2982     CV_SHMEDIA_CR63    =   2063,
2983
2984     CV_SHMEDIA_FPSCR   =   2064,
2985
2986     // Compact mode synonyms
2987     CV_SHMEDIA_GBR     =   CV_SHMEDIA_R16,
2988     CV_SHMEDIA_MACL    =   90, // synonym for lower 32bits of media R17
2989     CV_SHMEDIA_MACH    =   91, // synonym for upper 32bits of media R17
2990     CV_SHMEDIA_PR      =   CV_SHMEDIA_R18,
2991     CV_SHMEDIA_T       =   92, // synonym for lowest bit of media R19
2992     CV_SHMEDIA_FPUL    =   CV_SHMEDIA_FR32,
2993     CV_SHMEDIA_PC      =   93,
2994     CV_SHMEDIA_SR      =   CV_SHMEDIA_CR0,
2995
2996     //
2997     // AMD64 registers
2998     //
2999
3000     CV_AMD64_AL       =   1,
3001     CV_AMD64_CL       =   2,
3002     CV_AMD64_DL       =   3,
3003     CV_AMD64_BL       =   4,
3004     CV_AMD64_AH       =   5,
3005     CV_AMD64_CH       =   6,
3006     CV_AMD64_DH       =   7,
3007     CV_AMD64_BH       =   8,
3008     CV_AMD64_AX       =   9,
3009     CV_AMD64_CX       =  10,
3010     CV_AMD64_DX       =  11,
3011     CV_AMD64_BX       =  12,
3012     CV_AMD64_SP       =  13,
3013     CV_AMD64_BP       =  14,
3014     CV_AMD64_SI       =  15,
3015     CV_AMD64_DI       =  16,
3016     CV_AMD64_EAX      =  17,
3017     CV_AMD64_ECX      =  18,
3018     CV_AMD64_EDX      =  19,
3019     CV_AMD64_EBX      =  20,
3020     CV_AMD64_ESP      =  21,
3021     CV_AMD64_EBP      =  22,
3022     CV_AMD64_ESI      =  23,
3023     CV_AMD64_EDI      =  24,
3024     CV_AMD64_ES       =  25,
3025     CV_AMD64_CS       =  26,
3026     CV_AMD64_SS       =  27,
3027     CV_AMD64_DS       =  28,
3028     CV_AMD64_FS       =  29,
3029     CV_AMD64_GS       =  30,
3030     CV_AMD64_FLAGS    =  32,
3031     CV_AMD64_RIP      =  33,
3032     CV_AMD64_EFLAGS   =  34,
3033
3034     // Control registers
3035     CV_AMD64_CR0      =  80,
3036     CV_AMD64_CR1      =  81,
3037     CV_AMD64_CR2      =  82,
3038     CV_AMD64_CR3      =  83,
3039     CV_AMD64_CR4      =  84,
3040     CV_AMD64_CR8      =  88,
3041
3042     // Debug registers
3043     CV_AMD64_DR0      =  90,
3044     CV_AMD64_DR1      =  91,
3045     CV_AMD64_DR2      =  92,
3046     CV_AMD64_DR3      =  93,
3047     CV_AMD64_DR4      =  94,
3048     CV_AMD64_DR5      =  95,
3049     CV_AMD64_DR6      =  96,
3050     CV_AMD64_DR7      =  97,
3051     CV_AMD64_DR8      =  98,
3052     CV_AMD64_DR9      =  99,
3053     CV_AMD64_DR10     =  100,
3054     CV_AMD64_DR11     =  101,
3055     CV_AMD64_DR12     =  102,
3056     CV_AMD64_DR13     =  103,
3057     CV_AMD64_DR14     =  104,
3058     CV_AMD64_DR15     =  105,
3059
3060     CV_AMD64_GDTR     =  110,
3061     CV_AMD64_GDTL     =  111,
3062     CV_AMD64_IDTR     =  112,
3063     CV_AMD64_IDTL     =  113,
3064     CV_AMD64_LDTR     =  114,
3065     CV_AMD64_TR       =  115,
3066
3067     CV_AMD64_ST0      =  128,
3068     CV_AMD64_ST1      =  129,
3069     CV_AMD64_ST2      =  130,
3070     CV_AMD64_ST3      =  131,
3071     CV_AMD64_ST4      =  132,
3072     CV_AMD64_ST5      =  133,
3073     CV_AMD64_ST6      =  134,
3074     CV_AMD64_ST7      =  135,
3075     CV_AMD64_CTRL     =  136,
3076     CV_AMD64_STAT     =  137,
3077     CV_AMD64_TAG      =  138,
3078     CV_AMD64_FPIP     =  139,
3079     CV_AMD64_FPCS     =  140,
3080     CV_AMD64_FPDO     =  141,
3081     CV_AMD64_FPDS     =  142,
3082     CV_AMD64_ISEM     =  143,
3083     CV_AMD64_FPEIP    =  144,
3084     CV_AMD64_FPEDO    =  145,
3085
3086     CV_AMD64_MM0      =  146,
3087     CV_AMD64_MM1      =  147,
3088     CV_AMD64_MM2      =  148,
3089     CV_AMD64_MM3      =  149,
3090     CV_AMD64_MM4      =  150,
3091     CV_AMD64_MM5      =  151,
3092     CV_AMD64_MM6      =  152,
3093     CV_AMD64_MM7      =  153,
3094
3095     CV_AMD64_XMM0     =  154,   // KATMAI registers
3096     CV_AMD64_XMM1     =  155,
3097     CV_AMD64_XMM2     =  156,
3098     CV_AMD64_XMM3     =  157,
3099     CV_AMD64_XMM4     =  158,
3100     CV_AMD64_XMM5     =  159,
3101     CV_AMD64_XMM6     =  160,
3102     CV_AMD64_XMM7     =  161,
3103
3104     CV_AMD64_XMM0_0   =  162,   // KATMAI sub-registers
3105     CV_AMD64_XMM0_1   =  163,
3106     CV_AMD64_XMM0_2   =  164,
3107     CV_AMD64_XMM0_3   =  165,
3108     CV_AMD64_XMM1_0   =  166,
3109     CV_AMD64_XMM1_1   =  167,
3110     CV_AMD64_XMM1_2   =  168,
3111     CV_AMD64_XMM1_3   =  169,
3112     CV_AMD64_XMM2_0   =  170,
3113     CV_AMD64_XMM2_1   =  171,
3114     CV_AMD64_XMM2_2   =  172,
3115     CV_AMD64_XMM2_3   =  173,
3116     CV_AMD64_XMM3_0   =  174,
3117     CV_AMD64_XMM3_1   =  175,
3118     CV_AMD64_XMM3_2   =  176,
3119     CV_AMD64_XMM3_3   =  177,
3120     CV_AMD64_XMM4_0   =  178,
3121     CV_AMD64_XMM4_1   =  179,
3122     CV_AMD64_XMM4_2   =  180,
3123     CV_AMD64_XMM4_3   =  181,
3124     CV_AMD64_XMM5_0   =  182,
3125     CV_AMD64_XMM5_1   =  183,
3126     CV_AMD64_XMM5_2   =  184,
3127     CV_AMD64_XMM5_3   =  185,
3128     CV_AMD64_XMM6_0   =  186,
3129     CV_AMD64_XMM6_1   =  187,
3130     CV_AMD64_XMM6_2   =  188,
3131     CV_AMD64_XMM6_3   =  189,
3132     CV_AMD64_XMM7_0   =  190,
3133     CV_AMD64_XMM7_1   =  191,
3134     CV_AMD64_XMM7_2   =  192,
3135     CV_AMD64_XMM7_3   =  193,
3136
3137     CV_AMD64_XMM0L    =  194,
3138     CV_AMD64_XMM1L    =  195,
3139     CV_AMD64_XMM2L    =  196,
3140     CV_AMD64_XMM3L    =  197,
3141     CV_AMD64_XMM4L    =  198,
3142     CV_AMD64_XMM5L    =  199,
3143     CV_AMD64_XMM6L    =  200,
3144     CV_AMD64_XMM7L    =  201,
3145
3146     CV_AMD64_XMM0H    =  202,
3147     CV_AMD64_XMM1H    =  203,
3148     CV_AMD64_XMM2H    =  204,
3149     CV_AMD64_XMM3H    =  205,
3150     CV_AMD64_XMM4H    =  206,
3151     CV_AMD64_XMM5H    =  207,
3152     CV_AMD64_XMM6H    =  208,
3153     CV_AMD64_XMM7H    =  209,
3154
3155     CV_AMD64_MXCSR    =  211,   // XMM status register
3156
3157     CV_AMD64_EMM0L    =  220,   // XMM sub-registers (WNI integer)
3158     CV_AMD64_EMM1L    =  221,
3159     CV_AMD64_EMM2L    =  222,
3160     CV_AMD64_EMM3L    =  223,
3161     CV_AMD64_EMM4L    =  224,
3162     CV_AMD64_EMM5L    =  225,
3163     CV_AMD64_EMM6L    =  226,
3164     CV_AMD64_EMM7L    =  227,
3165
3166     CV_AMD64_EMM0H    =  228,
3167     CV_AMD64_EMM1H    =  229,
3168     CV_AMD64_EMM2H    =  230,
3169     CV_AMD64_EMM3H    =  231,
3170     CV_AMD64_EMM4H    =  232,
3171     CV_AMD64_EMM5H    =  233,
3172     CV_AMD64_EMM6H    =  234,
3173     CV_AMD64_EMM7H    =  235,
3174
3175     // do not change the order of these regs, first one must be even too
3176     CV_AMD64_MM00     =  236,
3177     CV_AMD64_MM01     =  237,
3178     CV_AMD64_MM10     =  238,
3179     CV_AMD64_MM11     =  239,
3180     CV_AMD64_MM20     =  240,
3181     CV_AMD64_MM21     =  241,
3182     CV_AMD64_MM30     =  242,
3183     CV_AMD64_MM31     =  243,
3184     CV_AMD64_MM40     =  244,
3185     CV_AMD64_MM41     =  245,
3186     CV_AMD64_MM50     =  246,
3187     CV_AMD64_MM51     =  247,
3188     CV_AMD64_MM60     =  248,
3189     CV_AMD64_MM61     =  249,
3190     CV_AMD64_MM70     =  250,
3191     CV_AMD64_MM71     =  251,
3192
3193     // Extended KATMAI registers
3194     CV_AMD64_XMM8     =  252,   // KATMAI registers
3195     CV_AMD64_XMM9     =  253,
3196     CV_AMD64_XMM10    =  254,
3197     CV_AMD64_XMM11    =  255,
3198     CV_AMD64_XMM12    =  256,
3199     CV_AMD64_XMM13    =  257,
3200     CV_AMD64_XMM14    =  258,
3201     CV_AMD64_XMM15    =  259,
3202
3203     CV_AMD64_XMM8_0   =  260,   // KATMAI sub-registers
3204     CV_AMD64_XMM8_1   =  261,
3205     CV_AMD64_XMM8_2   =  262,
3206     CV_AMD64_XMM8_3   =  263,
3207     CV_AMD64_XMM9_0   =  264,
3208     CV_AMD64_XMM9_1   =  265,
3209     CV_AMD64_XMM9_2   =  266,
3210     CV_AMD64_XMM9_3   =  267,
3211     CV_AMD64_XMM10_0  =  268,
3212     CV_AMD64_XMM10_1  =  269,
3213     CV_AMD64_XMM10_2  =  270,
3214     CV_AMD64_XMM10_3  =  271,
3215     CV_AMD64_XMM11_0  =  272,
3216     CV_AMD64_XMM11_1  =  273,
3217     CV_AMD64_XMM11_2  =  274,
3218     CV_AMD64_XMM11_3  =  275,
3219     CV_AMD64_XMM12_0  =  276,
3220     CV_AMD64_XMM12_1  =  277,
3221     CV_AMD64_XMM12_2  =  278,
3222     CV_AMD64_XMM12_3  =  279,
3223     CV_AMD64_XMM13_0  =  280,
3224     CV_AMD64_XMM13_1  =  281,
3225     CV_AMD64_XMM13_2  =  282,
3226     CV_AMD64_XMM13_3  =  283,
3227     CV_AMD64_XMM14_0  =  284,
3228     CV_AMD64_XMM14_1  =  285,
3229     CV_AMD64_XMM14_2  =  286,
3230     CV_AMD64_XMM14_3  =  287,
3231     CV_AMD64_XMM15_0  =  288,
3232     CV_AMD64_XMM15_1  =  289,
3233     CV_AMD64_XMM15_2  =  290,
3234     CV_AMD64_XMM15_3  =  291,
3235
3236     CV_AMD64_XMM8L    =  292,
3237     CV_AMD64_XMM9L    =  293,
3238     CV_AMD64_XMM10L   =  294,
3239     CV_AMD64_XMM11L   =  295,
3240     CV_AMD64_XMM12L   =  296,
3241     CV_AMD64_XMM13L   =  297,
3242     CV_AMD64_XMM14L   =  298,
3243     CV_AMD64_XMM15L   =  299,
3244
3245     CV_AMD64_XMM8H    =  300,
3246     CV_AMD64_XMM9H    =  301,
3247     CV_AMD64_XMM10H   =  302,
3248     CV_AMD64_XMM11H   =  303,
3249     CV_AMD64_XMM12H   =  304,
3250     CV_AMD64_XMM13H   =  305,
3251     CV_AMD64_XMM14H   =  306,
3252     CV_AMD64_XMM15H   =  307,
3253
3254     CV_AMD64_EMM8L    =  308,   // XMM sub-registers (WNI integer)
3255     CV_AMD64_EMM9L    =  309,
3256     CV_AMD64_EMM10L   =  310,
3257     CV_AMD64_EMM11L   =  311,
3258     CV_AMD64_EMM12L   =  312,
3259     CV_AMD64_EMM13L   =  313,
3260     CV_AMD64_EMM14L   =  314,
3261     CV_AMD64_EMM15L   =  315,
3262
3263     CV_AMD64_EMM8H    =  316,
3264     CV_AMD64_EMM9H    =  317,
3265     CV_AMD64_EMM10H   =  318,
3266     CV_AMD64_EMM11H   =  319,
3267     CV_AMD64_EMM12H   =  320,
3268     CV_AMD64_EMM13H   =  321,
3269     CV_AMD64_EMM14H   =  322,
3270     CV_AMD64_EMM15H   =  323,
3271
3272     // Low byte forms of some standard registers
3273     CV_AMD64_SIL      =  324,
3274     CV_AMD64_DIL      =  325,
3275     CV_AMD64_BPL      =  326,
3276     CV_AMD64_SPL      =  327,
3277
3278     // 64-bit regular registers
3279     CV_AMD64_RAX      =  328,
3280     CV_AMD64_RBX      =  329,
3281     CV_AMD64_RCX      =  330,
3282     CV_AMD64_RDX      =  331,
3283     CV_AMD64_RSI      =  332,
3284     CV_AMD64_RDI      =  333,
3285     CV_AMD64_RBP      =  334,
3286     CV_AMD64_RSP      =  335,
3287
3288     // 64-bit integer registers with 8-, 16-, and 32-bit forms (B, W, and D)
3289     CV_AMD64_R8       =  336,
3290     CV_AMD64_R9       =  337,
3291     CV_AMD64_R10      =  338,
3292     CV_AMD64_R11      =  339,
3293     CV_AMD64_R12      =  340,
3294     CV_AMD64_R13      =  341,
3295     CV_AMD64_R14      =  342,
3296     CV_AMD64_R15      =  343,
3297
3298     CV_AMD64_R8B      =  344,
3299     CV_AMD64_R9B      =  345,
3300     CV_AMD64_R10B     =  346,
3301     CV_AMD64_R11B     =  347,
3302     CV_AMD64_R12B     =  348,
3303     CV_AMD64_R13B     =  349,
3304     CV_AMD64_R14B     =  350,
3305     CV_AMD64_R15B     =  351,
3306
3307     CV_AMD64_R8W      =  352,
3308     CV_AMD64_R9W      =  353,
3309     CV_AMD64_R10W     =  354,
3310     CV_AMD64_R11W     =  355,
3311     CV_AMD64_R12W     =  356,
3312     CV_AMD64_R13W     =  357,
3313     CV_AMD64_R14W     =  358,
3314     CV_AMD64_R15W     =  359,
3315
3316     CV_AMD64_R8D      =  360,
3317     CV_AMD64_R9D      =  361,
3318     CV_AMD64_R10D     =  362,
3319     CV_AMD64_R11D     =  363,
3320     CV_AMD64_R12D     =  364,
3321     CV_AMD64_R13D     =  365,
3322     CV_AMD64_R14D     =  366,
3323     CV_AMD64_R15D     =  367,
3324
3325     // AVX registers 256 bits
3326     CV_AMD64_YMM0     =  368,
3327     CV_AMD64_YMM1     =  369,
3328     CV_AMD64_YMM2     =  370,
3329     CV_AMD64_YMM3     =  371,
3330     CV_AMD64_YMM4     =  372,
3331     CV_AMD64_YMM5     =  373,
3332     CV_AMD64_YMM6     =  374,
3333     CV_AMD64_YMM7     =  375,
3334     CV_AMD64_YMM8     =  376, 
3335     CV_AMD64_YMM9     =  377,
3336     CV_AMD64_YMM10    =  378,
3337     CV_AMD64_YMM11    =  379,
3338     CV_AMD64_YMM12    =  380,
3339     CV_AMD64_YMM13    =  381,
3340     CV_AMD64_YMM14    =  382,
3341     CV_AMD64_YMM15    =  383,
3342
3343     // AVX registers upper 128 bits
3344     CV_AMD64_YMM0H    =  384,
3345     CV_AMD64_YMM1H    =  385,
3346     CV_AMD64_YMM2H    =  386,
3347     CV_AMD64_YMM3H    =  387,
3348     CV_AMD64_YMM4H    =  388,
3349     CV_AMD64_YMM5H    =  389,
3350     CV_AMD64_YMM6H    =  390,
3351     CV_AMD64_YMM7H    =  391,
3352     CV_AMD64_YMM8H    =  392, 
3353     CV_AMD64_YMM9H    =  393,
3354     CV_AMD64_YMM10H   =  394,
3355     CV_AMD64_YMM11H   =  395,
3356     CV_AMD64_YMM12H   =  396,
3357     CV_AMD64_YMM13H   =  397,
3358     CV_AMD64_YMM14H   =  398,
3359     CV_AMD64_YMM15H   =  399,
3360
3361     //Lower/upper 8 bytes of XMM registers.  Unlike CV_AMD64_XMM<regnum><H/L>, these
3362     //values reprsesent the bit patterns of the registers as 64-bit integers, not
3363     //the representation of these registers as a double.
3364     CV_AMD64_XMM0IL    = 400,
3365     CV_AMD64_XMM1IL    = 401,
3366     CV_AMD64_XMM2IL    = 402,
3367     CV_AMD64_XMM3IL    = 403,
3368     CV_AMD64_XMM4IL    = 404,
3369     CV_AMD64_XMM5IL    = 405,
3370     CV_AMD64_XMM6IL    = 406,
3371     CV_AMD64_XMM7IL    = 407,
3372     CV_AMD64_XMM8IL    = 408,
3373     CV_AMD64_XMM9IL    = 409,
3374     CV_AMD64_XMM10IL    = 410,
3375     CV_AMD64_XMM11IL    = 411,
3376     CV_AMD64_XMM12IL    = 412,
3377     CV_AMD64_XMM13IL    = 413,
3378     CV_AMD64_XMM14IL    = 414,
3379     CV_AMD64_XMM15IL    = 415,
3380
3381     CV_AMD64_XMM0IH    = 416,
3382     CV_AMD64_XMM1IH    = 417,
3383     CV_AMD64_XMM2IH    = 418,
3384     CV_AMD64_XMM3IH    = 419,
3385     CV_AMD64_XMM4IH    = 420,
3386     CV_AMD64_XMM5IH    = 421,
3387     CV_AMD64_XMM6IH    = 422,
3388     CV_AMD64_XMM7IH    = 423,
3389     CV_AMD64_XMM8IH    = 424,
3390     CV_AMD64_XMM9IH    = 425,
3391     CV_AMD64_XMM10IH    = 426,
3392     CV_AMD64_XMM11IH    = 427,
3393     CV_AMD64_XMM12IH    = 428,
3394     CV_AMD64_XMM13IH    = 429,
3395     CV_AMD64_XMM14IH    = 430,
3396     CV_AMD64_XMM15IH    = 431,
3397
3398     CV_AMD64_YMM0I0    =  432,        // AVX integer registers
3399     CV_AMD64_YMM0I1    =  433,
3400     CV_AMD64_YMM0I2    =  434,
3401     CV_AMD64_YMM0I3    =  435,
3402     CV_AMD64_YMM1I0    =  436,
3403     CV_AMD64_YMM1I1    =  437,
3404     CV_AMD64_YMM1I2    =  438,
3405     CV_AMD64_YMM1I3    =  439,
3406     CV_AMD64_YMM2I0    =  440,
3407     CV_AMD64_YMM2I1    =  441,
3408     CV_AMD64_YMM2I2    =  442,
3409     CV_AMD64_YMM2I3    =  443,
3410     CV_AMD64_YMM3I0    =  444,
3411     CV_AMD64_YMM3I1    =  445,
3412     CV_AMD64_YMM3I2    =  446,
3413     CV_AMD64_YMM3I3    =  447,
3414     CV_AMD64_YMM4I0    =  448,
3415     CV_AMD64_YMM4I1    =  449,
3416     CV_AMD64_YMM4I2    =  450,
3417     CV_AMD64_YMM4I3    =  451,
3418     CV_AMD64_YMM5I0    =  452,
3419     CV_AMD64_YMM5I1    =  453,
3420     CV_AMD64_YMM5I2    =  454,
3421     CV_AMD64_YMM5I3    =  455,
3422     CV_AMD64_YMM6I0    =  456,
3423     CV_AMD64_YMM6I1    =  457,
3424     CV_AMD64_YMM6I2    =  458,
3425     CV_AMD64_YMM6I3    =  459,
3426     CV_AMD64_YMM7I0    =  460,
3427     CV_AMD64_YMM7I1    =  461,
3428     CV_AMD64_YMM7I2    =  462,
3429     CV_AMD64_YMM7I3    =  463,
3430     CV_AMD64_YMM8I0    =  464,
3431     CV_AMD64_YMM8I1    =  465,
3432     CV_AMD64_YMM8I2    =  466,
3433     CV_AMD64_YMM8I3    =  467,
3434     CV_AMD64_YMM9I0    =  468,
3435     CV_AMD64_YMM9I1    =  469,
3436     CV_AMD64_YMM9I2    =  470,
3437     CV_AMD64_YMM9I3    =  471,
3438     CV_AMD64_YMM10I0    =  472,
3439     CV_AMD64_YMM10I1    =  473,
3440     CV_AMD64_YMM10I2    =  474,
3441     CV_AMD64_YMM10I3    =  475,
3442     CV_AMD64_YMM11I0    =  476,
3443     CV_AMD64_YMM11I1    =  477,
3444     CV_AMD64_YMM11I2    =  478,
3445     CV_AMD64_YMM11I3    =  479,
3446     CV_AMD64_YMM12I0    =  480,
3447     CV_AMD64_YMM12I1    =  481,
3448     CV_AMD64_YMM12I2    =  482,
3449     CV_AMD64_YMM12I3    =  483,
3450     CV_AMD64_YMM13I0    =  484,
3451     CV_AMD64_YMM13I1    =  485,
3452     CV_AMD64_YMM13I2    =  486,
3453     CV_AMD64_YMM13I3    =  487,
3454     CV_AMD64_YMM14I0    =  488,
3455     CV_AMD64_YMM14I1    =  489,
3456     CV_AMD64_YMM14I2    =  490,
3457     CV_AMD64_YMM14I3    =  491,
3458     CV_AMD64_YMM15I0    =  492,
3459     CV_AMD64_YMM15I1    =  493,
3460     CV_AMD64_YMM15I2    =  494,
3461     CV_AMD64_YMM15I3    =  495,
3462
3463     CV_AMD64_YMM0F0    =  496,        // AVX floating-point single precise registers
3464     CV_AMD64_YMM0F1    =  497,
3465     CV_AMD64_YMM0F2    =  498,
3466     CV_AMD64_YMM0F3    =  499,
3467     CV_AMD64_YMM0F4    =  500,
3468     CV_AMD64_YMM0F5    =  501,
3469     CV_AMD64_YMM0F6    =  502,
3470     CV_AMD64_YMM0F7    =  503,
3471     CV_AMD64_YMM1F0    =  504,
3472     CV_AMD64_YMM1F1    =  505,
3473     CV_AMD64_YMM1F2    =  506,
3474     CV_AMD64_YMM1F3    =  507,
3475     CV_AMD64_YMM1F4    =  508,
3476     CV_AMD64_YMM1F5    =  509,
3477     CV_AMD64_YMM1F6    =  510,
3478     CV_AMD64_YMM1F7    =  511,
3479     CV_AMD64_YMM2F0    =  512,
3480     CV_AMD64_YMM2F1    =  513,
3481     CV_AMD64_YMM2F2    =  514,
3482     CV_AMD64_YMM2F3    =  515,
3483     CV_AMD64_YMM2F4    =  516,
3484     CV_AMD64_YMM2F5    =  517,
3485     CV_AMD64_YMM2F6    =  518,
3486     CV_AMD64_YMM2F7    =  519,
3487     CV_AMD64_YMM3F0    =  520,
3488     CV_AMD64_YMM3F1    =  521,
3489     CV_AMD64_YMM3F2    =  522,
3490     CV_AMD64_YMM3F3    =  523,
3491     CV_AMD64_YMM3F4    =  524,
3492     CV_AMD64_YMM3F5    =  525,
3493     CV_AMD64_YMM3F6    =  526,
3494     CV_AMD64_YMM3F7    =  527,
3495     CV_AMD64_YMM4F0    =  528,
3496     CV_AMD64_YMM4F1    =  529,
3497     CV_AMD64_YMM4F2    =  530,
3498     CV_AMD64_YMM4F3    =  531,
3499     CV_AMD64_YMM4F4    =  532,
3500     CV_AMD64_YMM4F5    =  533,
3501     CV_AMD64_YMM4F6    =  534,
3502     CV_AMD64_YMM4F7    =  535,
3503     CV_AMD64_YMM5F0    =  536,
3504     CV_AMD64_YMM5F1    =  537,
3505     CV_AMD64_YMM5F2    =  538,
3506     CV_AMD64_YMM5F3    =  539,
3507     CV_AMD64_YMM5F4    =  540,
3508     CV_AMD64_YMM5F5    =  541,
3509     CV_AMD64_YMM5F6    =  542,
3510     CV_AMD64_YMM5F7    =  543,
3511     CV_AMD64_YMM6F0    =  544,
3512     CV_AMD64_YMM6F1    =  545,
3513     CV_AMD64_YMM6F2    =  546,
3514     CV_AMD64_YMM6F3    =  547,
3515     CV_AMD64_YMM6F4    =  548,
3516     CV_AMD64_YMM6F5    =  549,
3517     CV_AMD64_YMM6F6    =  550,
3518     CV_AMD64_YMM6F7    =  551,
3519     CV_AMD64_YMM7F0    =  552,
3520     CV_AMD64_YMM7F1    =  553,
3521     CV_AMD64_YMM7F2    =  554,
3522     CV_AMD64_YMM7F3    =  555,
3523     CV_AMD64_YMM7F4    =  556,
3524     CV_AMD64_YMM7F5    =  557,
3525     CV_AMD64_YMM7F6    =  558,
3526     CV_AMD64_YMM7F7    =  559,
3527     CV_AMD64_YMM8F0    =  560,
3528     CV_AMD64_YMM8F1    =  561,
3529     CV_AMD64_YMM8F2    =  562,
3530     CV_AMD64_YMM8F3    =  563,
3531     CV_AMD64_YMM8F4    =  564,
3532     CV_AMD64_YMM8F5    =  565,
3533     CV_AMD64_YMM8F6    =  566,
3534     CV_AMD64_YMM8F7    =  567,
3535     CV_AMD64_YMM9F0    =  568,
3536     CV_AMD64_YMM9F1    =  569,
3537     CV_AMD64_YMM9F2    =  570,
3538     CV_AMD64_YMM9F3    =  571,
3539     CV_AMD64_YMM9F4    =  572,
3540     CV_AMD64_YMM9F5    =  573,
3541     CV_AMD64_YMM9F6    =  574,
3542     CV_AMD64_YMM9F7    =  575,
3543     CV_AMD64_YMM10F0    =  576,
3544     CV_AMD64_YMM10F1    =  577,
3545     CV_AMD64_YMM10F2    =  578,
3546     CV_AMD64_YMM10F3    =  579,
3547     CV_AMD64_YMM10F4    =  580,
3548     CV_AMD64_YMM10F5    =  581,
3549     CV_AMD64_YMM10F6    =  582,
3550     CV_AMD64_YMM10F7    =  583,
3551     CV_AMD64_YMM11F0    =  584,
3552     CV_AMD64_YMM11F1    =  585,
3553     CV_AMD64_YMM11F2    =  586,
3554     CV_AMD64_YMM11F3    =  587,
3555     CV_AMD64_YMM11F4    =  588,
3556     CV_AMD64_YMM11F5    =  589,
3557     CV_AMD64_YMM11F6    =  590,
3558     CV_AMD64_YMM11F7    =  591,
3559     CV_AMD64_YMM12F0    =  592,
3560     CV_AMD64_YMM12F1    =  593,
3561     CV_AMD64_YMM12F2    =  594,
3562     CV_AMD64_YMM12F3    =  595,
3563     CV_AMD64_YMM12F4    =  596,
3564     CV_AMD64_YMM12F5    =  597,
3565     CV_AMD64_YMM12F6    =  598,
3566     CV_AMD64_YMM12F7    =  599,
3567     CV_AMD64_YMM13F0    =  600,
3568     CV_AMD64_YMM13F1    =  601,
3569     CV_AMD64_YMM13F2    =  602,
3570     CV_AMD64_YMM13F3    =  603,
3571     CV_AMD64_YMM13F4    =  604,
3572     CV_AMD64_YMM13F5    =  605,
3573     CV_AMD64_YMM13F6    =  606,
3574     CV_AMD64_YMM13F7    =  607,
3575     CV_AMD64_YMM14F0    =  608,
3576     CV_AMD64_YMM14F1    =  609,
3577     CV_AMD64_YMM14F2    =  610,
3578     CV_AMD64_YMM14F3    =  611,
3579     CV_AMD64_YMM14F4    =  612,
3580     CV_AMD64_YMM14F5    =  613,
3581     CV_AMD64_YMM14F6    =  614,
3582     CV_AMD64_YMM14F7    =  615,
3583     CV_AMD64_YMM15F0    =  616,
3584     CV_AMD64_YMM15F1    =  617,
3585     CV_AMD64_YMM15F2    =  618,
3586     CV_AMD64_YMM15F3    =  619,
3587     CV_AMD64_YMM15F4    =  620,
3588     CV_AMD64_YMM15F5    =  621,
3589     CV_AMD64_YMM15F6    =  622,
3590     CV_AMD64_YMM15F7    =  623,
3591     
3592     CV_AMD64_YMM0D0    =  624,        // AVX floating-point double precise registers
3593     CV_AMD64_YMM0D1    =  625,
3594     CV_AMD64_YMM0D2    =  626,
3595     CV_AMD64_YMM0D3    =  627,
3596     CV_AMD64_YMM1D0    =  628,
3597     CV_AMD64_YMM1D1    =  629,
3598     CV_AMD64_YMM1D2    =  630,
3599     CV_AMD64_YMM1D3    =  631,
3600     CV_AMD64_YMM2D0    =  632,
3601     CV_AMD64_YMM2D1    =  633,
3602     CV_AMD64_YMM2D2    =  634,
3603     CV_AMD64_YMM2D3    =  635,
3604     CV_AMD64_YMM3D0    =  636,
3605     CV_AMD64_YMM3D1    =  637,
3606     CV_AMD64_YMM3D2    =  638,
3607     CV_AMD64_YMM3D3    =  639,
3608     CV_AMD64_YMM4D0    =  640,
3609     CV_AMD64_YMM4D1    =  641,
3610     CV_AMD64_YMM4D2    =  642,
3611     CV_AMD64_YMM4D3    =  643,
3612     CV_AMD64_YMM5D0    =  644,
3613     CV_AMD64_YMM5D1    =  645,
3614     CV_AMD64_YMM5D2    =  646,
3615     CV_AMD64_YMM5D3    =  647,
3616     CV_AMD64_YMM6D0    =  648,
3617     CV_AMD64_YMM6D1    =  649,
3618     CV_AMD64_YMM6D2    =  650,
3619     CV_AMD64_YMM6D3    =  651,
3620     CV_AMD64_YMM7D0    =  652,
3621     CV_AMD64_YMM7D1    =  653,
3622     CV_AMD64_YMM7D2    =  654,
3623     CV_AMD64_YMM7D3    =  655,
3624     CV_AMD64_YMM8D0    =  656,
3625     CV_AMD64_YMM8D1    =  657,
3626     CV_AMD64_YMM8D2    =  658,
3627     CV_AMD64_YMM8D3    =  659,
3628     CV_AMD64_YMM9D0    =  660,
3629     CV_AMD64_YMM9D1    =  661,
3630     CV_AMD64_YMM9D2    =  662,
3631     CV_AMD64_YMM9D3    =  663,
3632     CV_AMD64_YMM10D0    =  664,
3633     CV_AMD64_YMM10D1    =  665,
3634     CV_AMD64_YMM10D2    =  666,
3635     CV_AMD64_YMM10D3    =  667,
3636     CV_AMD64_YMM11D0    =  668,
3637     CV_AMD64_YMM11D1    =  669,
3638     CV_AMD64_YMM11D2    =  670,
3639     CV_AMD64_YMM11D3    =  671,
3640     CV_AMD64_YMM12D0    =  672,
3641     CV_AMD64_YMM12D1    =  673,
3642     CV_AMD64_YMM12D2    =  674,
3643     CV_AMD64_YMM12D3    =  675,
3644     CV_AMD64_YMM13D0    =  676,
3645     CV_AMD64_YMM13D1    =  677,
3646     CV_AMD64_YMM13D2    =  678,
3647     CV_AMD64_YMM13D3    =  679,
3648     CV_AMD64_YMM14D0    =  680,
3649     CV_AMD64_YMM14D1    =  681,
3650     CV_AMD64_YMM14D2    =  682,
3651     CV_AMD64_YMM14D3    =  683,
3652     CV_AMD64_YMM15D0    =  684,
3653     CV_AMD64_YMM15D1    =  685,
3654     CV_AMD64_YMM15D2    =  686,
3655     CV_AMD64_YMM15D3    =  687
3656
3657
3658     // Note:  Next set of platform registers need to go into a new enum...
3659     // this one is above 44K now.
3660
3661 } CV_HREG_e;
3662
3663 typedef enum CV_HLSLREG_e {
3664     CV_HLSLREG_TEMP                                = 0,  
3665     CV_HLSLREG_INPUT                               = 1,  
3666     CV_HLSLREG_OUTPUT                              = 2,  
3667     CV_HLSLREG_INDEXABLE_TEMP                      = 3,  
3668     CV_HLSLREG_IMMEDIATE32                         = 4,  
3669     CV_HLSLREG_IMMEDIATE64                         = 5,  
3670     CV_HLSLREG_SAMPLER                             = 6,  
3671     CV_HLSLREG_RESOURCE                            = 7,  
3672     CV_HLSLREG_CONSTANT_BUFFER                     = 8,  
3673     CV_HLSLREG_IMMEDIATE_CONSTANT_BUFFER           = 9,  
3674     CV_HLSLREG_LABEL                               = 10, 
3675     CV_HLSLREG_INPUT_PRIMITIVEID                   = 11, 
3676     CV_HLSLREG_OUTPUT_DEPTH                        = 12, 
3677     CV_HLSLREG_NULL                                = 13, 
3678     CV_HLSLREG_RASTERIZER                          = 14, 
3679     CV_HLSLREG_OUTPUT_COVERAGE_MASK                = 15, 
3680     CV_HLSLREG_STREAM                              = 16, 
3681     CV_HLSLREG_FUNCTION_BODY                       = 17, 
3682     CV_HLSLREG_FUNCTION_TABLE                      = 18, 
3683     CV_HLSLREG_INTERFACE                           = 19, 
3684     CV_HLSLREG_FUNCTION_INPUT                      = 20, 
3685     CV_HLSLREG_FUNCTION_OUTPUT                     = 21, 
3686     CV_HLSLREG_OUTPUT_CONTROL_POINT_ID             = 22, 
3687     CV_HLSLREG_INPUT_FORK_INSTANCE_ID              = 23, 
3688     CV_HLSLREG_INPUT_JOIN_INSTANCE_ID              = 24, 
3689     CV_HLSLREG_INPUT_CONTROL_POINT                 = 25, 
3690     CV_HLSLREG_OUTPUT_CONTROL_POINT                = 26, 
3691     CV_HLSLREG_INPUT_PATCH_CONSTANT                = 27, 
3692     CV_HLSLREG_INPUT_DOMAIN_POINT                  = 28, 
3693     CV_HLSLREG_THIS_POINTER                        = 29, 
3694     CV_HLSLREG_UNORDERED_ACCESS_VIEW               = 30, 
3695     CV_HLSLREG_THREAD_GROUP_SHARED_MEMORY          = 31, 
3696     CV_HLSLREG_INPUT_THREAD_ID                     = 32, 
3697     CV_HLSLREG_INPUT_THREAD_GROUP_ID               = 33, 
3698     CV_HLSLREG_INPUT_THREAD_ID_IN_GROUP            = 34, 
3699     CV_HLSLREG_INPUT_COVERAGE_MASK                 = 35, 
3700     CV_HLSLREG_INPUT_THREAD_ID_IN_GROUP_FLATTENED  = 36,
3701     CV_HLSLREG_INPUT_GS_INSTANCE_ID                = 37, 
3702     CV_HLSLREG_OUTPUT_DEPTH_GREATER_EQUAL          = 38, 
3703     CV_HLSLREG_OUTPUT_DEPTH_LESS_EQUAL             = 39, 
3704     CV_HLSLREG_CYCLE_COUNTER                       = 40, 
3705 } CV_HLSLREG_e;
3706
3707 enum StackFrameTypeEnum
3708 {
3709     FrameTypeFPO,                   // Frame pointer omitted, FPO info available
3710     FrameTypeTrap,                  // Kernel Trap frame
3711     FrameTypeTSS,                   // Kernel Trap frame
3712     FrameTypeStandard,              // Standard EBP stackframe
3713     FrameTypeFrameData,             // Frame pointer omitted, FrameData info available
3714
3715     FrameTypeUnknown = -1,          // Frame which does not have any debug info
3716 };
3717
3718 enum MemoryTypeEnum
3719 {
3720     MemTypeCode,                    // Read only code memory
3721     MemTypeData,                    // Read only data/stack memory
3722     MemTypeStack,                   // Read only stack memory
3723     MemTypeCodeOnHeap,              // Read only memory for code generated on heap by runtime
3724
3725     MemTypeAny = -1,
3726 };
3727
3728 typedef enum CV_HLSLMemorySpace_e
3729 {
3730     // HLSL specific memory spaces
3731
3732     CV_HLSL_MEMSPACE_DATA         = 0x00,
3733     CV_HLSL_MEMSPACE_SAMPLER      = 0x01,
3734     CV_HLSL_MEMSPACE_RESOURCE     = 0x02,
3735     CV_HLSL_MEMSPACE_RWRESOURCE   = 0x03,
3736
3737     CV_HLSL_MEMSPACE_MAX          = 0x0F,
3738 } CV_HLSLMemorySpace_e;
3739
3740 #endif