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30 #include "RoseInsnFactory.h"
31 //#include "../rose/x86InstructionSemantics.h"
32 //#include "../rose/powerpcInstructionSemantics.h"
34 #include "Instruction.h"
36 #include "Expression.h"
37 #include "Dereference.h"
38 #include "Immediate.h"
41 #include "../rose/SgAsmInstruction.h"
42 #include "../rose/SgAsmPowerpcInstruction.h"
43 #include "../rose/SgAsmx86Instruction.h"
44 #include "../rose/SgAsmExpression.h"
46 #include "ExpressionConversionVisitor.h"
48 using namespace Dyninst;
49 using namespace InstructionAPI;
50 using namespace DataflowAPI;
52 SgAsmInstruction *RoseInsnFactory::convert(const InstructionAPI::Instruction::Ptr &insn, uint64_t addr) {
53 SgAsmInstruction *rinsn = createInsn();
55 rinsn->set_address(addr);
56 rinsn->set_mnemonic(insn->format());
57 setOpcode(rinsn, insn->getOperation().getID(), insn->getOperation().getPrefixID(), insn->getOperation().format());
59 // semantics don't support 64-bit code
62 //rinsn->set_operandSize(x86_insnsize_32);
63 //rinsn->set_addressSize(x86_insnsize_32);
65 std::vector<unsigned char> rawBytes;
66 for (unsigned i = 0; i < insn->size(); ++i) rawBytes.push_back(insn->rawByte(i));
67 rinsn->set_raw_bytes(rawBytes);
70 SgAsmOperandList *roperands = new SgAsmOperandList;
72 // std::cerr << "Converting " << insn->format(addr) << " @" << std::hex << addr << std::dec << std::endl;
74 // std::cerr << "checking instruction: " << insn->format(addr) << " for special handling" << std::endl;
75 if (handleSpecialCases(insn->getOperation().getID(), rinsn, roperands)) {
76 rinsn->set_operandList(roperands);
80 // std::cerr << "no special handling by opcode, checking if we should mangle operands..." << std::endl;
81 std::vector<InstructionAPI::Operand> operands;
82 insn->getOperands(operands);
83 // std::cerr << "\t " << operands.size() << " operands" << std::endl;
84 massageOperands(insn, operands);
86 // std::cerr << "converting insn " << insn->format(addr) << std::endl;
87 for (std::vector<InstructionAPI::Operand>::iterator opi = operands.begin();
88 opi != operands.end();
90 InstructionAPI::Operand &currOperand = *opi;
91 // std::cerr << "Converting operand " << currOperand.format(Arch_x86, addr) << std::endl;
92 roperands->append_operand(convertOperand(currOperand.getValue(), addr));
94 rinsn->set_operandList(roperands);
98 SgAsmExpression *RoseInsnFactory::convertOperand(const Expression::Ptr expression, uint64_t addr) {
99 if(!expression) return NULL;
100 ExpressionConversionVisitor visitor(arch(), addr);
101 expression->apply(&visitor);
102 return visitor.getRoseExpression();
105 ///////////// X86 //////////////////
107 SgAsmInstruction *RoseInsnX86Factory::createInsn() {
108 return new SgAsmx86Instruction;
111 // Note: convertKind is defined in convertOpcodes.C
113 void RoseInsnX86Factory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID prefix, std::string) {
114 SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
116 tmp->set_kind(convertKind(opcode, prefix));
119 void RoseInsnX86Factory::setSizes(SgAsmInstruction *insn) {
120 // FIXME when we go 64-bit...
121 SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
122 tmp->set_operandSize(x86_insnsize_32);
123 tmp->set_addressSize(x86_insnsize_32);
126 bool RoseInsnX86Factory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsmOperandList *) {
132 void RoseInsnX86Factory::massageOperands(const InstructionAPI::Instruction::Ptr &insn,
133 std::vector<InstructionAPI::Operand> &operands) {
134 switch (insn->getOperation().getID()) {
136 // ROSE expects there to be a "memory reference" statement wrapping the
137 // address calculation. It then unwraps it.
138 Dereference::Ptr tmp = Dereference::Ptr(new Dereference(operands[1].getValue(), u32));
139 operands[1] = Operand(tmp, operands[1].isRead(), operands[1].isWritten());
202 if (operands.size() == 2) {
203 operands[0]=operands[1];
213 //////////// PPC ///////////////////
214 // Note: convertKind is defined in convertOpcodes.C
216 SgAsmInstruction *RoseInsnPPCFactory::createInsn() {
217 return new SgAsmPowerpcInstruction;
220 void RoseInsnPPCFactory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID /*prefix*/, std::string mnem) {
221 SgAsmPowerpcInstruction *tmp = static_cast<SgAsmPowerpcInstruction *>(insn);
222 kind = convertKind(opcode, mnem);
227 void RoseInsnPPCFactory::setSizes(SgAsmInstruction *) {
231 bool RoseInsnPPCFactory::handleSpecialCases(entryID iapi_opcode,
232 SgAsmInstruction *insn,
233 SgAsmOperandList *rose_operands) {
234 SgAsmPowerpcInstruction *rose_insn = static_cast<SgAsmPowerpcInstruction *>(insn);
236 switch(iapi_opcode) {
240 case power_op_bclr: {
241 unsigned int raw = 0;
242 int branch_target = 0;
243 unsigned int bo = 0, bi = 0;
244 std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
245 for(unsigned i = 0; i < bytes.size(); i++) {
249 bool isAbsolute = (bool)(raw & 0x00000002);
250 bool isLink = (bool)(raw & 0x00000001);
251 rose_insn->set_kind(makeRoseBranchOpcode(iapi_opcode, isAbsolute, isLink));
252 if(power_op_b == iapi_opcode) {
253 branch_target = ((raw >> 2) & 0x00FFFFFF) << 2;
254 branch_target = (branch_target << 8) >> 8;
256 if(power_op_bc == iapi_opcode) {
257 branch_target = ((raw >> 2) & 0x00003FFF) << 2;
258 branch_target = (branch_target << 18) >> 18;
259 //cerr << "14-bit branch target: " << branch_target << endl;
261 bo = ((raw >> 21) & 0x0000001F);
262 bi = ((raw >> 16) & 0x0000001F);
263 rose_operands->append_operand(new SgAsmByteValueExpression(bo));
264 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_cr, bi,
265 powerpc_condreggranularity_bit));
268 rose_operands->append_operand(new SgAsmDoubleWordValueExpression(branch_target));
269 } else if(power_op_bcctr == iapi_opcode) {
270 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_ctr));
272 assert(power_op_bclr == iapi_opcode);
273 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_lr));
279 case power_op_svcs: {
280 //cerr << "special-casing syscall insn" << endl;
281 unsigned int raw = 0;
282 std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
283 for(unsigned i = 0; i < bytes.size(); i++) {
287 unsigned int lev = (raw >> 5) & 0x7F;
288 rose_operands->append_operand(new SgAsmByteValueExpression(lev));
289 //cerr << "LEV = " << lev << endl;
298 void RoseInsnPPCFactory::massageOperands(const InstructionAPI::Instruction::Ptr &insn,
299 std::vector<InstructionAPI::Operand> &operands) {
301 if(insn->writesMemory())
302 std::swap(operands[0], operands[1]);
304 entryID opcode = insn->getOperation().getID();
305 // Anything that's writing RA, ROSE expects in RA, RS, RB/immediates form.
306 // Any store, however, ROSE expects in RS, RA, RB/displacement form. Very confusing,
307 // but we handle it cleanly here.
308 if(!operands[0].isWritten() && operands.size() >= 2 &&
309 operands[1].isWritten() && !operands[1].writesMemory()) {
310 //std::cerr << "swapping RS and RA in " << insn->format() << std::endl;
311 std::swap(operands[0], operands[1]);
313 if(opcode == power_op_cmp ||
314 opcode == power_op_cmpl ||
315 opcode == power_op_cmpi ||
316 opcode == power_op_cmpli) {
317 operands.push_back(Operand(Immediate::makeImmediate(Result(u8, 1)), false, false));
318 std::swap(operands[2], operands[3]);
319 std::swap(operands[1], operands[2]);
321 if(insn->getOperation().format().find(".") != std::string::npos &&
322 insn->getOperation().getID() != power_op_stwcx_rc) {
326 // Convert to ROSE so we can use numeric greater than/less than
328 if(kind >= powerpc_lbz && kind <= powerpc_lwzx) {
331 if(kind >= powerpc_stb && kind <= powerpc_stwx) {