Minor fixes
[dyninst.git] / dataflowAPI / src / RoseInsnFactory.C
1 #include "RoseInsnFactory.h"
2 //#include "../rose/x86InstructionSemantics.h"
3 //#include "../rose/powerpcInstructionSemantics.h"
4
5 #include "Instruction.h"
6 #include "Operand.h"
7 #include "Expression.h"
8 #include "Dereference.h"
9 #include "Immediate.h"
10 #include <vector>
11
12 #include "../rose/SgAsmInstruction.h"
13 #include "../rose/SgAsmPowerpcInstruction.h"
14 #include "../rose/SgAsmx86Instruction.h"
15 #include "../rose/SgAsmExpression.h"
16
17 #include "ExpressionConversionVisitor.h"
18
19 using namespace Dyninst;
20 using namespace InstructionAPI;
21 using namespace DataflowAPI;
22
23 SgAsmInstruction *RoseInsnFactory::convert(const InstructionAPI::Instruction::Ptr &insn, uint64_t addr) {
24   SgAsmInstruction *rinsn = createInsn();
25   
26   rinsn->set_address(addr);
27   rinsn->set_mnemonic(insn->format());
28   setOpcode(rinsn, insn->getOperation().getID(), insn->getOperation().getPrefixID(), insn->getOperation().format());
29
30   // semantics don't support 64-bit code
31   setSizes(rinsn);
32
33   //rinsn->set_operandSize(x86_insnsize_32);
34   //rinsn->set_addressSize(x86_insnsize_32);
35   
36   std::vector<unsigned char> rawBytes;
37   for (unsigned i = 0; i < insn->size(); ++i) rawBytes.push_back(insn->rawByte(i));
38   rinsn->set_raw_bytes(rawBytes);
39   
40   // operand list
41   SgAsmOperandList *roperands = new SgAsmOperandList;
42   
43   //cerr << "Converting " << insn->format() << " @" << hex << addr << dec << endl;
44   
45   //cerr << "checking instruction: " << insn->format() << " for special handling" << endl;
46   if (handleSpecialCases(insn->getOperation().getID(), rinsn, roperands)) {
47     rinsn->set_operandList(roperands);
48     return rinsn;
49   }
50
51   //cerr << "no special handling by opcode, checking if we should mangle operands..." << endl;
52   std::vector<InstructionAPI::Operand> operands;
53   insn->getOperands(operands);
54   //cerr << "\t " << operands.size() << " operands" << endl;
55   massageOperands(insn, operands);
56   int i = 0;
57   //cerr << "converting insn " << insn->format() << endl;
58   for (std::vector<InstructionAPI::Operand>::iterator opi = operands.begin();
59        opi != operands.end();
60        ++opi, ++i) {
61     InstructionAPI::Operand &currOperand = *opi;
62     //cerr << "Converting operand " << currOperand.format() << endl;
63     roperands->append_operand(convertOperand(currOperand.getValue(), addr));
64   }  
65   rinsn->set_operandList(roperands);
66   return rinsn;
67 }
68
69 SgAsmExpression *RoseInsnFactory::convertOperand(const Expression::Ptr expression, uint64_t addr) {
70   if(!expression) return NULL;
71   ExpressionConversionVisitor visitor(arch(), addr);
72   expression->apply(&visitor);
73   return visitor.getRoseExpression();
74 }
75
76 ///////////// X86 //////////////////
77
78 SgAsmInstruction *RoseInsnX86Factory::createInsn() {
79   return new SgAsmx86Instruction;
80 }
81
82 // Note: convertKind is defined in convertOpcodes.C
83
84 void RoseInsnX86Factory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID prefix, std::string) {
85   SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
86   
87   tmp->set_kind(convertKind(opcode, prefix));
88 }
89
90 void RoseInsnX86Factory::setSizes(SgAsmInstruction *insn) {
91   // FIXME when we go 64-bit...
92   SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
93   tmp->set_operandSize(x86_insnsize_32);
94   tmp->set_addressSize(x86_insnsize_32);
95 }
96
97 bool RoseInsnX86Factory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsmOperandList *) {
98   // Does nothing?
99   return false;
100 }
101
102 void RoseInsnX86Factory::massageOperands(const InstructionAPI::Instruction::Ptr &insn, 
103                                          std::vector<InstructionAPI::Operand> &operands) {
104   switch (insn->getOperation().getID()) {
105   case e_lea: {
106                   // ROSE expects there to be a "memory reference" statement wrapping the 
107                   // address calculation. It then unwraps it.
108                   Dereference::Ptr tmp = Dereference::Ptr(new Dereference(operands[1].getValue(), u32));
109                   operands[1] = Operand(tmp, operands[1].isRead(), operands[1].isWritten());
110                   operands.resize(2);
111                   break;
112               }
113   case e_push:
114   case e_pop:
115     operands.resize(1);
116     break;
117   case e_cmpxch:
118     operands.resize(2);
119     break;
120   case e_movsb:
121   case e_movsd:
122   case e_movsw:
123     // No operands
124     operands.clear();
125     break;
126   case e_cmpsb:
127   case e_cmpsw:
128   case e_cmpsd:
129     // No operands
130     operands.clear();
131     break;
132   case e_scasb:
133   case e_scasd:
134   case e_scasw:
135     // Same here
136     operands.clear();
137     break;
138   case e_stosb:
139   case e_stosd:
140   case e_stosw:
141     // Also, no operands
142     operands.clear();
143     break;
144   case e_jcxz_jec:
145     operands.resize(1);
146     break;
147   case e_cbw:
148   case e_cwde:
149   case e_cdq:
150     // Nada
151     operands.clear();
152     break;
153   case e_popad:
154     operands.clear();
155     break;
156   default:
157     break;
158   }
159 }
160
161
162 //////////// PPC ///////////////////
163 // Note: convertKind is defined in convertOpcodes.C
164
165 SgAsmInstruction *RoseInsnPPCFactory::createInsn() {
166   return new SgAsmPowerpcInstruction;
167 }
168
169 void RoseInsnPPCFactory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID /*prefix*/, std::string mnem) {
170   SgAsmPowerpcInstruction *tmp = static_cast<SgAsmPowerpcInstruction *>(insn);
171   kind = convertKind(opcode, mnem);
172   tmp->set_kind(kind);
173 }
174
175
176 void RoseInsnPPCFactory::setSizes(SgAsmInstruction *) {
177 }
178
179
180 bool RoseInsnPPCFactory::handleSpecialCases(entryID iapi_opcode, 
181                                             SgAsmInstruction *insn, 
182                                             SgAsmOperandList *rose_operands) {
183   SgAsmPowerpcInstruction *rose_insn = static_cast<SgAsmPowerpcInstruction *>(insn);
184
185   switch(iapi_opcode) {
186   case power_op_b:
187   case power_op_bc:
188   case power_op_bcctr:
189   case power_op_bclr: {
190     unsigned int raw = 0;
191     int branch_target = 0;
192     unsigned int bo = 0, bi = 0;
193     std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
194     for(unsigned i = 0; i < bytes.size(); i++) {
195       raw = raw << 8;
196       raw |= bytes[i];
197     }
198     bool isAbsolute = (bool)(raw & 0x00000002);
199     bool isLink = (bool)(raw & 0x00000001);
200     rose_insn->set_kind(makeRoseBranchOpcode(iapi_opcode, isAbsolute, isLink));
201     if(power_op_b == iapi_opcode) {
202       branch_target = ((raw >> 2) & 0x00FFFFFF) << 2;
203       branch_target = (branch_target << 8) >> 8;
204     } else {
205       if(power_op_bc == iapi_opcode) {
206         branch_target = ((raw >> 2) & 0x00003FFF) << 2;
207         branch_target = (branch_target << 18) >> 18;
208         //cerr << "14-bit branch target: " << branch_target << endl;
209       }
210       bo = ((raw >> 21) & 0x0000001F);
211       bi = ((raw >> 16) & 0x0000001F);
212       rose_operands->append_operand(new SgAsmByteValueExpression(bo));
213       rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_cr, bi,
214                                                                                 powerpc_condreggranularity_bit));
215     }
216     if(branch_target) {
217       rose_operands->append_operand(new SgAsmDoubleWordValueExpression(branch_target));
218     } else if(power_op_bcctr == iapi_opcode) {
219       rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_ctr));
220     } else {
221       assert(power_op_bclr == iapi_opcode);
222       rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_lr));
223     }
224     return true;
225   }
226     break;
227   case power_op_sc:
228   case power_op_svcs: {
229     //cerr << "special-casing syscall insn" << endl;
230     unsigned int raw = 0;
231     std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
232     for(unsigned i = 0; i < bytes.size(); i++) {
233       raw = raw << 8;
234       raw |= bytes[i];
235     }
236     unsigned int lev = (raw >> 5) & 0x7F;
237     rose_operands->append_operand(new SgAsmByteValueExpression(lev));
238     //cerr << "LEV = " << lev << endl;
239     return true;
240   }
241   default:
242     return false;
243   }
244   
245 }  
246
247 void RoseInsnPPCFactory::massageOperands(const InstructionAPI::Instruction::Ptr &insn, 
248                                          std::vector<InstructionAPI::Operand> &operands) {
249   /*
250   if(insn->writesMemory())
251     std::swap(operands[0], operands[1]);
252   */
253   entryID opcode = insn->getOperation().getID();
254   // Anything that's writing RA, ROSE expects in RA, RS, RB/immediates form.
255   // Any store, however, ROSE expects in RS, RA, RB/displacement form.  Very confusing,
256   // but we handle it cleanly here.
257   if(!operands[0].isWritten() && operands.size() >= 2 &&
258      operands[1].isWritten() && !operands[1].writesMemory()) {
259     //std::cerr << "swapping RS and RA in " << insn->format() << std::endl;
260     std::swap(operands[0], operands[1]);
261   }
262   if(opcode == power_op_cmp ||
263      opcode == power_op_cmpl ||
264      opcode == power_op_cmpi ||
265      opcode == power_op_cmpli) {
266     operands.push_back(Operand(Immediate::makeImmediate(Result(u8, 1)), false, false));
267     std::swap(operands[2], operands[3]);
268     std::swap(operands[1], operands[2]);
269   }
270   if(insn->getOperation().format().find(".") != std::string::npos &&
271      insn->getOperation().getID() != power_op_stwcx_rc) {
272     operands.pop_back();
273   }
274
275   // Convert to ROSE so we can use numeric greater than/less than
276
277   if(kind >= powerpc_lbz && kind <= powerpc_lwzx) {
278     operands.resize(2);
279   }
280   if(kind >= powerpc_stb && kind <= powerpc_stwx) {
281     operands.resize(2);
282   }
283
284   return;
285 }
286