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30 #include "RoseInsnFactory.h"
31 //#include "../rose/x86InstructionSemantics.h"
32 //#include "../rose/powerpcInstructionSemantics.h"
34 #include "Instruction.h"
36 #include "Expression.h"
37 #include "Dereference.h"
38 #include "Immediate.h"
41 #include "../rose/SgAsmInstruction.h"
42 #include "../rose/SgAsmPowerpcInstruction.h"
43 #include "../rose/SgAsmx86Instruction.h"
44 #include "../rose/SgAsmExpression.h"
46 #include "ExpressionConversionVisitor.h"
48 using namespace Dyninst;
49 using namespace InstructionAPI;
50 using namespace DataflowAPI;
52 SgAsmInstruction *RoseInsnFactory::convert(const InstructionAPI::Instruction::Ptr &insn, uint64_t addr) {
53 SgAsmInstruction *rinsn = createInsn();
55 rinsn->set_address(addr);
56 rinsn->set_mnemonic(insn->format());
57 setOpcode(rinsn, insn->getOperation().getID(), insn->getOperation().getPrefixID(), insn->getOperation().format());
59 // semantics don't support 64-bit code
62 //rinsn->set_operandSize(x86_insnsize_32);
63 //rinsn->set_addressSize(x86_insnsize_32);
65 std::vector<unsigned char> rawBytes;
66 for (unsigned i = 0; i < insn->size(); ++i) rawBytes.push_back(insn->rawByte(i));
67 rinsn->set_raw_bytes(rawBytes);
70 SgAsmOperandList *roperands = new SgAsmOperandList;
72 // std::cerr << "Converting " << insn->format(addr) << " @" << std::hex << addr << std::dec << std::endl;
74 // std::cerr << "checking instruction: " << insn->format(addr) << " for special handling" << std::endl;
75 if (handleSpecialCases(insn->getOperation().getID(), rinsn, roperands)) {
76 rinsn->set_operandList(roperands);
80 // std::cerr << "no special handling by opcode, checking if we should mangle operands..." << std::endl;
81 std::vector<InstructionAPI::Operand> operands;
82 insn->getOperands(operands);
83 // std::cerr << "\t " << operands.size() << " operands" << std::endl;
84 massageOperands(insn, operands);
86 // std::cerr << "converting insn " << insn->format(addr) << std::endl;
87 for (std::vector<InstructionAPI::Operand>::iterator opi = operands.begin();
88 opi != operands.end();
90 InstructionAPI::Operand &currOperand = *opi;
91 // std::cerr << "Converting operand " << currOperand.format(arch(), addr) << std::endl;
92 roperands->append_operand(convertOperand(currOperand.getValue(), addr, insn->size()));
94 rinsn->set_operandList(roperands);
98 SgAsmExpression *RoseInsnFactory::convertOperand(const Expression::Ptr expression, int64_t addr, size_t insnSize) {
99 if(!expression) return NULL;
100 ExpressionConversionVisitor visitor(arch(), addr, insnSize);
101 expression->apply(&visitor);
102 return visitor.getRoseExpression();
105 ///////////// X86 //////////////////
107 SgAsmInstruction *RoseInsnX86Factory::createInsn() {
108 return new SgAsmx86Instruction;
111 // Note: convertKind is defined in convertOpcodes.C
113 void RoseInsnX86Factory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID prefix, std::string) {
114 SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
116 tmp->set_kind(convertKind(opcode, prefix));
119 void RoseInsnX86Factory::setSizes(SgAsmInstruction *insn) {
120 SgAsmx86Instruction *tmp = static_cast<SgAsmx86Instruction *>(insn);
121 if (a == Arch_x86_64) {
122 tmp->set_operandSize(x86_insnsize_64);
123 tmp->set_addressSize(x86_insnsize_64);
125 tmp->set_operandSize(x86_insnsize_32);
126 tmp->set_addressSize(x86_insnsize_32);
130 bool RoseInsnX86Factory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsmOperandList *) {
136 void RoseInsnX86Factory::massageOperands(const InstructionAPI::Instruction::Ptr &insn,
137 std::vector<InstructionAPI::Operand> &operands) {
138 switch (insn->getOperation().getID()) {
140 // ROSE expects there to be a "memory reference" statement wrapping the
141 // address calculation. It then unwraps it.
142 Dereference::Ptr tmp = Dereference::Ptr(new Dereference(operands[1].getValue(), u32));
143 operands[1] = Operand(tmp, operands[1].isRead(), operands[1].isWritten());
206 if (operands.size() == 2) {
207 operands[0]=operands[1];
213 // ROSE does not expect implicit operand rax/eax to be treated as an operand
218 // ROSE does not expect implicit operand rax/eax to be treated as an operand
219 std::set<RegisterAST::Ptr> regs;
220 operands[0].getReadSet(regs);
221 operands[0].getWriteSet(regs);
223 operands[0] = operands[1];
234 //////////// PPC ///////////////////
235 // Note: convertKind is defined in convertOpcodes.C
237 SgAsmInstruction *RoseInsnPPCFactory::createInsn() {
238 return new SgAsmPowerpcInstruction;
241 void RoseInsnPPCFactory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID /*prefix*/, std::string mnem) {
242 SgAsmPowerpcInstruction *tmp = static_cast<SgAsmPowerpcInstruction *>(insn);
243 kind = convertKind(opcode, mnem);
248 void RoseInsnPPCFactory::setSizes(SgAsmInstruction *) {
252 bool RoseInsnPPCFactory::handleSpecialCases(entryID iapi_opcode,
253 SgAsmInstruction *insn,
254 SgAsmOperandList *rose_operands) {
255 SgAsmPowerpcInstruction *rose_insn = static_cast<SgAsmPowerpcInstruction *>(insn);
257 switch(iapi_opcode) {
261 case power_op_bclr: {
262 unsigned int raw = 0;
263 int branch_target = 0;
264 unsigned int bo = 0, bi = 0;
265 std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
266 for(unsigned i = 0; i < bytes.size(); i++) {
270 bool isAbsolute = (bool)(raw & 0x00000002);
271 bool isLink = (bool)(raw & 0x00000001);
272 rose_insn->set_kind(makeRoseBranchOpcode(iapi_opcode, isAbsolute, isLink));
273 if(power_op_b == iapi_opcode) {
274 branch_target = ((raw >> 2) & 0x00FFFFFF) << 2;
275 branch_target = (branch_target << 8) >> 8;
277 if(power_op_bc == iapi_opcode) {
278 branch_target = ((raw >> 2) & 0x00003FFF) << 2;
279 branch_target = (branch_target << 18) >> 18;
280 //cerr << "14-bit branch target: " << branch_target << endl;
282 bo = ((raw >> 21) & 0x0000001F);
283 bi = ((raw >> 16) & 0x0000001F);
284 rose_operands->append_operand(new SgAsmByteValueExpression(bo));
285 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_cr, bi,
286 powerpc_condreggranularity_bit));
289 rose_operands->append_operand(new SgAsmDoubleWordValueExpression(branch_target));
290 } else if(power_op_bcctr == iapi_opcode) {
291 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_ctr));
293 assert(power_op_bclr == iapi_opcode);
294 rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_lr));
300 case power_op_svcs: {
301 //cerr << "special-casing syscall insn" << endl;
302 unsigned int raw = 0;
303 std::vector<unsigned char> bytes = rose_insn->get_raw_bytes();
304 for(unsigned i = 0; i < bytes.size(); i++) {
308 unsigned int lev = (raw >> 5) & 0x7F;
309 rose_operands->append_operand(new SgAsmByteValueExpression(lev));
310 //cerr << "LEV = " << lev << endl;
319 void RoseInsnPPCFactory::massageOperands(const InstructionAPI::Instruction::Ptr &insn,
320 std::vector<InstructionAPI::Operand> &operands) {
322 if(insn->writesMemory())
323 std::swap(operands[0], operands[1]);
325 entryID opcode = insn->getOperation().getID();
326 // Anything that's writing RA, ROSE expects in RA, RS, RB/immediates form.
327 // Any store, however, ROSE expects in RS, RA, RB/displacement form. Very confusing,
328 // but we handle it cleanly here.
329 if(!operands[0].isWritten() && operands.size() >= 2 &&
330 operands[1].isWritten() && !operands[1].writesMemory()) {
331 //std::cerr << "swapping RS and RA in " << insn->format() << std::endl;
332 std::swap(operands[0], operands[1]);
334 if(opcode == power_op_cmp ||
335 opcode == power_op_cmpl ||
336 opcode == power_op_cmpi ||
337 opcode == power_op_cmpli) {
338 operands.push_back(Operand(Immediate::makeImmediate(Result(u8, 1)), false, false));
339 std::swap(operands[2], operands[3]);
340 std::swap(operands[1], operands[2]);
342 if(insn->getOperation().format().find(".") != std::string::npos &&
343 insn->getOperation().getID() != power_op_stwcx_rc) {
347 // Convert to ROSE so we can use numeric greater than/less than
349 if(kind >= powerpc_lbz && kind <= powerpc_lwzx) {
352 if(kind >= powerpc_stb && kind <= powerpc_stwx) {