dataflowAPI/src/ExpressionConversionVisitor.C

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  30 #include "ExpressionConversionVisitor.h"
  31
  32 #include "Register.h"
  33 #include "Immediate.h"
  34 #include "BinaryFunction.h"
  35 #include "Dereference.h"
  36
  37 #include <list>
  38
  39 #include "../rose/SgAsmExpression.h"
  40
  41 using namespace Dyninst;
  42 using namespace Dyninst::InstructionAPI;
  43 using namespace DataflowAPI;
  44
  45 void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) {
  46     // no children
  47
  48     const Result &value = immed->eval();
  49
  50     // TODO rose doesn't distinguish signed/unsigned within the value itself,
  51     // only at operations?
  52
  53     // TODO rose doesn't handle large values (XMM?)
  54
  55     // build different kind of rose value object based on type
  56     if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64) {
  57         bool isSigned = false;
  58         switch (value.type) {
  59             case s8:
  60                 isSigned = true;
  61             case u8:
  62                 roseExpression = new SgAsmIntegerValueExpression(value.val.u8val,
  63                                                                  new SgAsmIntegerType(ByteOrder::ORDER_UNSPECIFIED, 8,
  64                                                                                       isSigned));
  65                 break;
  66             case s16:
  67                 isSigned = true;
  68             case u16:
  69                 roseExpression = new SgAsmIntegerValueExpression(value.val.u16val,
  70                                                                  new SgAsmIntegerType(ByteOrder::ORDER_LSB, 16,
  71                                                                                       isSigned));
  72                 break;
  73             case s32:
  74                 isSigned = true;
  75             case u32:
  76                 roseExpression = new SgAsmIntegerValueExpression(value.val.u32val,
  77                                                                  new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32,
  78                                                                                       isSigned));
  79                 break;
  80             case s48:
  81                 isSigned = true;
  82             case u48:
  83                 roseExpression = new SgAsmIntegerValueExpression(value.val.u32val,
  84                                                                  new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32,
  85                                                                                       isSigned));
  86                 break;
  87             case s64:
  88                 isSigned = true;
  89             case u64:
  90                 roseExpression = new SgAsmIntegerValueExpression(value.val.u64val,
  91                                                                  new SgAsmIntegerType(ByteOrder::ORDER_LSB, 64,
  92                                                                                       isSigned));
  93                 break;
  94             case sp_float:
  95                 roseExpression = new SgAsmSingleFloatValueExpression(value.val.floatval);
  96                 break;
  97             case dp_float:
  98                 roseExpression = new SgAsmDoubleFloatValueExpression(value.val.dblval);
  99                 break;
 100             default:
 101                 roseExpression = NULL;
 102                 assert(0);
 103         }
 104     } else {
 105         switch (value.type) {
 106             case s8:
 107             case u8:
 108                 roseExpression = new SgAsmByteValueExpression(value.val.u8val);
 109                 break;
 110             case s16:
 111             case u16:
 112                 roseExpression = new SgAsmWordValueExpression(value.val.u16val);
 113                 break;
 114             case s32:
 115             case u32:
 116                 roseExpression = new SgAsmDoubleWordValueExpression(value.val.u32val);
 117                 break;
 118             case s48:
 119             case u48:
 120                 // This only happens with far calls. ROSE appears to be set up to
 121                 // expect a 32-bit absolute destination (or doesn't handle far call at
 122                 // all), so give it what it wants.
 123                 roseExpression = new SgAsmDoubleWordValueExpression(value.val.u32val);
 124                 break;
 125             case s64:
 126             case u64:
 127                 roseExpression = new SgAsmQuadWordValueExpression(value.val.u64val);
 128                 break;
 129             case sp_float:
 130                 roseExpression = new SgAsmSingleFloatValueExpression(value.val.floatval);
 131                 break;
 132             case dp_float:
 133                 roseExpression = new SgAsmDoubleFloatValueExpression(value.val.dblval);
 134                 break;
 135             default:
 136                 roseExpression = NULL;
 137                 assert(0);
 138                 // error!
 139         }
 140     }
 141     m_stack.push_front(roseExpression);
 142 }
 143
 144
 145 void ExpressionConversionVisitor::visit(RegisterAST *regast) {
 146     // has no children
 147
 148     m_stack.push_front(archSpecificRegisterProc(regast, addr, size));
 149     roseExpression = m_stack.front();
 150     return;
 151 }
 152
 153 void ExpressionConversionVisitor::visit(Dereference *deref) {
 154     // get child
 155     assert(m_stack.size());
 156     SgAsmExpression *toderef = m_stack.front();
 157     m_stack.pop_front();
 158     if (toderef == NULL) {
 159         roseExpression = NULL;
 160         return;
 161     }
 162     SgAsmType *type;
 163
 164     // TODO fix some mismatched types?
 165     // pick correct type
 166     if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64) {
 167         bool isSigned = false;
 168         switch (deref->eval().type) {
 169             case s8:
 170                 isSigned = true;
 171             case u8:
 172                 type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 8, isSigned);
 173                 break;
 174             case s16:
 175                 isSigned = true;
 176             case u16:
 177                 type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 16, isSigned);
 178                 break;
 179             case s32:
 180                 isSigned = true;
 181             case u32:
 182                 type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32, isSigned);
 183                 break;
 184             case s64:
 185                 isSigned = true;
 186             case u64:
 187                 type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 64, isSigned);
 188                 break;
 189             case sp_float:
 190                 type = new SgAsmFloatType(ByteOrder::ORDER_LSB, 64,
 191                                           SgAsmFloatType::BitRange::baseSize(0, 52),  // significand
 192                                           SgAsmFloatType::BitRange::baseSize(52, 11), // exponent
 193                                           63,                                         // sign bit
 194                                           1023,                                       // exponent bias
 195                                           SgAsmFloatType::NORMALIZED_SIGNIFICAND | SgAsmFloatType::GRADUAL_UNDERFLOW);
 196                 break;
 197             case dp_float:
 198                 type = new SgAsmFloatType(ByteOrder::ORDER_LSB, 80,
 199                                           SgAsmFloatType::BitRange::baseSize(0, 64),  // significand
 200                                           SgAsmFloatType::BitRange::baseSize(64, 15), // exponent
 201                                           79,                                         // sign bit
 202                                           16383,                                      // exponent bias
 203                                           SgAsmFloatType::NORMALIZED_SIGNIFICAND | SgAsmFloatType::GRADUAL_UNDERFLOW);
 204                 break;
 205             default:
 206                 type = NULL;
 207         }
 208     } else {
 209         switch (deref->eval().type) {
 210             case s8:
 211             case u8:
 212                 type = new SgAsmTypeByte();
 213                 break;
 214             case s16:
 215             case u16:
 216                 type = new SgAsmTypeWord();
 217                 break;
 218             case s32:
 219             case u32:
 220                 type = new SgAsmTypeDoubleWord();
 221                 break;
 222             case s64:
 223             case u64:
 224                 type = new SgAsmTypeQuadWord();
 225                 break;
 226             case sp_float:
 227                 type = new SgAsmTypeSingleFloat();
 228                 break;
 229             case dp_float:
 230                 type = new SgAsmTypeDoubleFloat();
 231                 break;
 232             default:
 233                 type = NULL;
 234                 // error
 235         }
 236     }
 237
 238     SgAsmExpression *segReg = makeSegRegExpr();
 239     SgAsmMemoryReferenceExpression *result = new SgAsmMemoryReferenceExpression(toderef, segReg);
 240     result->set_type(type);
 241     roseExpression = result;
 242 }
 243
 244 SgAsmExpression *ExpressionConversionVisitor::archSpecificRegisterProc(InstructionAPI::RegisterAST *regast,
 245                                                                        uint64_t addr, uint64_t size) {
 246
 247     MachRegister machReg = regast->getID();
 248
 249     switch (arch) {
 250         case Arch_x86:
 251         case Arch_x86_64: {
 252             int regClass;
 253             int regNum;
 254             int regPos;
 255
 256             MachRegister machReg = regast->getID();
 257             if (machReg.isPC()) {
 258                 // ideally this would be symbolic
 259                 // When ip is read, the value read is not the address of the current instruction,
 260                 // but the address of the next instruction.
 261                 SgAsmExpression *constAddrExpr;
 262                 if (arch == Arch_x86)
 263                     constAddrExpr = new SgAsmDoubleWordValueExpression(addr + size);
 264                 else
 265                     constAddrExpr = new SgAsmQuadWordValueExpression(addr + size);
 266
 267                 return constAddrExpr;
 268             }
 269             machReg.getROSERegister(regClass, regNum, regPos);
 270
 271             return new SgAsmx86RegisterReferenceExpression((X86RegisterClass) regClass,
 272                                                            regNum,
 273                                                            (X86PositionInRegister) regPos);
 274         }
 275         case Arch_ppc32:
 276         case Arch_ppc64: {
 277             int regClass;
 278             int regNum;
 279             int regPos;
 280             SgAsmDirectRegisterExpression *dre;
 281             machReg.getROSERegister(regClass, regNum, regPos);
 282             if (regClass == powerpc_regclass_cr) {
 283                 dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, 4));
 284             } else {
 285                 dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, machReg.size() * 8));
 286             }
 287             dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, machReg.size() * 8, false));
 288             return dre;
 289         }
 290         case Arch_aarch64: {
 291             int regClass;
 292             int regNum;
 293             int regPos;
 294
 295             if((machReg & 0xFF) == (aarch64::pstate & 0xFF) && (machReg & 0xFF0000) == (aarch64::SPR))
 296                 return NULL;
 297
 298             machReg.getROSERegister(regClass, regNum, regPos);
 299
 300             SgAsmDirectRegisterExpression *dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, machReg.size() * 8));
 301             dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, machReg.size() * 8, false));
 302             return dre;
 303         }
 304         default:
 305             return NULL;
 306     }
 307 }
 308
 309 SgAsmExpression *ExpressionConversionVisitor::makeSegRegExpr() {
 310     if (arch == Arch_x86 || arch == Arch_x86_64) {
 311         return new SgAsmx86RegisterReferenceExpression(x86_regclass_segment,
 312                                                        x86_segreg_none, x86_regpos_all);
 313     }
 314     else {
 315         return NULL;
 316     }
 317 }
 318
 319 /////////////// Visitor class /////////////////
 320
 321 void ExpressionConversionVisitor::visit(BinaryFunction *binfunc) {
 322     assert(m_stack.size() >= 2);
 323     SgAsmExpression *rhs = m_stack.front();
 324     m_stack.pop_front();
 325     SgAsmExpression *lhs = m_stack.front();
 326     m_stack.pop_front();
 327     // If the RHS didn't convert, that means it should disappear
 328     // And we are just left with the LHS
 329     if (!rhs && !lhs) {
 330         roseExpression = NULL;
 331     }
 332     else if (!rhs) {
 333         roseExpression = lhs;
 334     }
 335     else if (!lhs) {
 336         roseExpression = rhs;
 337     }
 338     else {
 339         // now build either add or multiply
 340         if (binfunc->isAdd())
 341             roseExpression = new SgAsmBinaryAdd(lhs, rhs);
 342         else if (binfunc->isMultiply())
 343             roseExpression = new SgAsmBinaryMultiply(lhs, rhs);
 344         else if (binfunc->isLeftShift())
 345             roseExpression = new SgAsmBinaryLsl(lhs, rhs);
 346         else if (binfunc->isRightArithmeticShift())
 347             roseExpression = new SgAsmBinaryAsr(lhs, rhs);
 348         else if (binfunc->isRightLogicalShift())
 349             roseExpression = new SgAsmBinaryLsr(lhs, rhs);
 350         else if (binfunc->isRightRotate())
 351             roseExpression = new SgAsmBinaryRor(lhs, rhs);
 352         else roseExpression = NULL; // error
 353     }
 354     m_stack.push_front(roseExpression);
 355 }